W83626F/W83626D

Publication Release Date:Feb. 2000

-I - Preliminary Revision 0.50

W83626F/W83626D Data Sheet Revision History

Pages

Dates

Version

Version
on Web

Main Contents

n.a.

02/25/00

0.50

First published.

1
0

Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 1 - Revision 0.50

GENERAL DESCRIPTION

W83626F/W83626D is a transparent LPC-to-ISA bus conversion IC.

For the new generation Intel chipset Camino and Whitney, SiS Super South 960,
featuring LPC bus, there is no support for ISA bus and slots. However the demand of
ISA devices still exist. For such case, W83626F is the best companion solution for the
non-ISA chipset. Also the packages of W83626F had been chosen to be the most
economic solution for save the M/B board layout size and cost.

For the new generation chipset featuring LPC interface and support no ISA bus,
W83627HF (Winbond LPC I/O) together with the set of W83626F is the complete
solution.

FEATURES

LPC to ISA Bridge

Meet LPC Spec. 1.1

Support LDRQ# (LPC DMA), SERIRQ (serial IRQ)

Full ISA Bus Support except ISA Bus Masters

5V ISA and 3.3V LPC interfaces

All

Software Transparent

IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ

Supports 3 fully ISA Compatible Slots without Buffering

LPC

Bus at 33MHz

Supports Programmable ISA Bus Divide the PCI Clock into 3 or 4

All ISA Signals can be Isolate

14.318MHz in to generate two 14.318MHz buffer out and one 24.576MHz

Specific Keyboard Functions supported

Support 8 programmable general purpose I/O pins

Supports Configuration registers for programming performance

PACKAGE

128-pin PQFP for W83626F

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 3 - Revision 0.50

PIN CONFIGURATION FOR 626F

GPIO6/RTCCS#

64
63

62
61

59
58

56
55

54
53

52
51

50
49

47
46
45

44
43
42

40
39

103

104
105

106

107
108

109
110

111
112
113
114

115

116

117

118

119

120

121
122
123

124
125

126

127
128

2 1 0

9
7

8
5

7
8

7
7

7
6

7
3

1 2 3 4 5 6 7 8 9

1
0

1
1

1
2

1
3

1
4

1
5

1
6

1
7

1
8

1
9

2
0

2
1

2
2

2
3

2
4

2
5

2
6

2
7

2
8

2
9

3
0

3
1

3
2

3
3

3
4

3
5

3
6

3
7

3
8

DRQ5

DACK5#

DRQ0

DACK0#

VCC5

IRQ14

IRQ15

IRQ11

IRQ12

IRQ10

IOCS16#

MEMCS16#

LFRAM#

PCIRST#

GND

LAD3

LAD2 LAD1 LAD0 VCC3

PCICLK LDRQ# SERIRQ

PWRDN#

14.318M

14MOUT1

14MOUT2

24.576M

SA0

AVCC3

SA1

SA2 SA3 SA4

GPIO0/IRQ1

ROMCS#

AGND

80PCS#/KBEN#

GPIO5/IRQ8

GPIO4/PLED

GPIO3/IRQIN

IOCHRDY

GND
AEN

SA19

SA18

SA17

VCC5

SA16
SA15

SA14

SA13
GND
SA12
SA11
SA10
SA9

VCC5

SA8

SA7

SA6
SA5

GPIO2/MCCS#

GPIO1/KBCS#

GPIO7/IOHCS#

SD0

SD1

SD2

VCC5

SD3

SD5

SD4

SD6

OWS#

SD7

IOCHCK#

RSTDRV

IRQ9

DRQ2

GND

SMEMW#

SMEMR#

VCC5 IOW#

IOR#

DACK3#

DRQ3

DACK2#

BALE

IRQ3

IRQ4 IRQ5

GND IRQ6

REFRESH#

SYSCLK

IRQ7

DRQ1

DACK1#

SBHE#

LA23
LA22

VCC5

LA21
LA20

LA19

LA18

GND

LA17

MEMR#

MEMW#

SD8

SD10

SD9

SD11
SD12
SD13

VCC5

SD14
SD15

MASTER#/RTCEN

DRQ7

GND

DACK7#

DRQ6

DACK6#/HEFRAS

W83626F

LPC to ISA

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 4 - Revision 0.50

1. PIN DESCRIPTION

I/O12t - TTL level bi-directional pin with 12 m A source-sink capability

I/O24t - TTL level bi-directional pin with 24 m A source-sink capability

I/O12tp3 - 3.3V TTL level bi-directional pin with 12 m A source-sink capability

I/O24tp3 - 3.3V TTL level bi-directional pin with 24 m A source-sink capability

I/OD12t - TTL level bi-directional pin open drain output with 12 m A sink capability

I/O24t - TTL level bi-directional pin with 24 m A source-sink capability

OUT12 - TTL level output pin with 12 m A source-sink capability
OUT24 - TTL level output pin with 24 m A source-sink capability

O12p3 - 3.3V TTL level output pin with 12 m A source-sink capability
O24p3 - 3.3V TTL level output pin with 24 m A source-sink capability

OD12 - Open-drain output pin with 12 m A sink capability
OD24 - Open-drain output pin with 24 m A sink capability

INcs - CMOS level Schmitt-trigger input pin
INt - TTL level input pin

INtd - TTL level input pin with internal pull down resistor
INtu - TTL level input pin with internal pull up resistor

INts - TTL level Schmitt-trigger input pin

INtsp3 - 3.3V TTL level Schmitt-trigger input pin

W83626F PIN DESCRIPTION

LPC Interface

SYMBOL

PIN

I/O

FUNCTION

LAD[3:0]

16-19

I/O

12tp3

These signal lines communicate address, control and data
information over the LPC bus between a host and a peripheral.

LFRAME#

tsp3

Indicates start of a new cycle or termination of a broken cycle.

PCICLK

INt

PCICLK provides timing for all transactions on the LPC bus. All
LPC signals are sampled on the rising edge of PCICLK, and all
timing parameters are defined with respect to this edge.

PCIRST#

INtsp3 Reset signal. It can connect to PCIRST# signal on the host.

SERIRQ

I/OD12t Serial IRQ Input/Output.

LDRQ#

12tp3

Encoded DMA Request signal.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 5 - Revision 0.50

LPC Interface, continued

SYMBOL

PIN

I/O

FUNCTION

PWRDN#

INtu

Power Down. The signal is active low according to CR 44 Bit 7and
wake-up enable by hardware setting. There are eight different
power-down states (Power down Mode 3).

ISA Interface Signals

SYMBOL

PIN

I/O

FUNCTION

SA[19:17]

58-56

OUT24 System Address Bus. These are the upper address lines that

define the ISA's byte granular address space (up to 1 M byte).
SA[19:17] are at an unknown state upon PCIRST#.

SA[16:0]

54-51

49-46

44-41

35-31

OUT24 System Address Bus. These are the bi-directional lower address

lines that define the ISA's byte granular address space (up to 1 M
byte). SA[16:0] are at an unknown state upon PCIRST#.

SD[15:0]

122-1

119-1

75-71

69-67

OUT24 System Data. SD[15:0] provide the 16-bit data path for devices

residing on the ISA Bus. The W83626F tri-states SD[15:0] during
PCIRST#.

AEN

OUT24 Address Enable. AEN is asserted during DMA cycles. This signal

is also driven high during W83626F initiated refresh cycles. AEN is
driven low upon PCIRST#.

IOR#

OUT24 I/O Read. IOR# is the command to an ISA I/O slave device that the

slave may drive data on to the ISA data bus (SD[15:0]).

IOW#

OUT24 I/O Write. IOW# is the command to an ISA I/O slave device that

the slave may latch data from the ISA data bus (SD[15:0]).

IOCHRDY

INt

I/O Channel Ready. Resources on the ISA Bus negate IOCHRDY
to indicate that additional time (wait states) is required to complete
the cycle.

SYSCLK

OUT24 ISA System Clock. SYSCLK is the reference clock for the ISA

bus. The SYSCLK is generated by dividing PCICLK by 3 or 4.

RSTDRV

OUT24

Reset Drive. W83628F asserts RSTDRV to reset devices that
reside on the ISA Bus. The W83628F asserts this signal while the
PCIRST# is asserted.

IOCS16#

INt

16-bit I/O Chip Select. This signal is driven by I/O devices on the
ISA Bus to indicate that they support 16-bit I/O bus cycles.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 6 - Revision 0.50

ISA Interface Signals , continued

SYMBOL

PIN

I/O

FUNCTION

MEMCS16#

INt

Memory Chip Select 16. MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.

IOCHCK#

INt

I/O Channel Check. IOCHK# can be driven by any resource on

the ISA bus during on detection of an error.

OWS#

INt

Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate that
the current cycle can be executed as an ISA zero wait state cycle.
ZEROWS# has no effect during 16-bit I/O cycles.

LA[23:17]

103-1

106-1

111

OUT24 Unlatched Address. The LA[23:17] address lines are

bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.

SMEMW#

OUT24 Standard Memory Write. SMEMW# asserted indicates the

current ISA bus cycle is a memory write cycle to an address below
1 Mbyte.

SMEMR#

OUT24 Standard Memory Read. SMEMR# asserted indicates the

current ISA bus cycle is a memory read cycle to an address below
1 Mbyte.

REFRESH#

OUT24 Refresh. REFRESH# asserted indicates that a refresh cycle is in

progress, or that an ISA master is requesting W83626F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.

BALE

101

OUT24 Bus Address Latch Enable. BALE is an active high signal

asserted by the W83626F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.

SBHE#

102

OUT24 System Byte High Enable. SBHE# asserted indicates that a byte

is being transferred on the upper byte (SD[15:8]) of the data bus.
SBHE# is at an unknown state upon PCIRST#.

MEMR#

112

OUT24 Memory Read. MEMR# asserted indicates the current ISA bus

cycle is a memory read.

MEMW#

113

OUT24 Memory Write. MEMW# asserted indicates the current ISA bus

cycle is a memory write.

MASTER#

RTCEN#

123

INt

MASTER#. This signal is used with a DREQ line by an ISA master
to gain control of the ISA Bus.

RTC Function Enable.The pin applies a pull-down resistor (4.7K
ohm) to enable RTC functions ( RTCCS#,and IRQ8)

IRQ3

INt

Parallel Interrupt Requested Input 3.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 7 - Revision 0.50

ISA Interface Signals , continued

SYMBOL

PIN

I/O

FUNCTION

IRQ4

INt

Parallel Interrupt Requested Input 4.

IRQ5

INt

Parallel Interrupt Requested Input 5.

IRQ6

INt

Parallel Interrupt Requested Input 6.

IRQ7

INt

Parallel Interrupt Requested Input 7.

IRQ9

INt

Parallel Interrupt Requested Input 9.

IRQ10

INt

Parallel Interrupt Requested Input 10.

IRQ11

INt

Parallel Interrupt Requested Input 11.

IRQ12

INt

Parallel Interrupt Requested Input 12.

IRQ14

INt

Parallel Interrupt Requested Input 14.

IRQ15

INt

Parallel Interrupt Requested Input 15.

DRQ0

INt

DMA Request 0. The DREQ signal indicates that either a slave
DMA device is requesting DMA services, or an ISA bus master is
requesting use of the ISA bus.

DRQ1

INt

DMA Request 1.

DRQ2

INt

DMA Request 2.

DRQ3

INt

DMA Request 3.

DRQ5

INt

DMA Request 5.

DRQ6

127

INt

DMA Request 6.

DRQ7

124

INt

DMA Request 7.

DACK0#

OUT24 DMA Acknowledge 0. The DACK# signal indicates that either a

DMA channel or an ISA bus master has been granted the ISA bus.

DACK1#

OUT24 DMA Acknowledge 1.

DACK2#

OUT24 DMA Acknowledge 2.

DACK3#

OUT24 DMA Acknowledge 3.

DACK5#

OUT24 DMA Acknowledge 5.

DACK6#

HERFRA

127

I/OD24t DMA Acknowledge 6.

During power-on reset,this is pulled-hi internally(Select 4Eh) and
is defined as HEFRAS which provides the power-on value for
CR3 bit4 .A 4.7k ohm is recommended if intends to pull down
.(Select 2Eh)

DACK7#

126

OUT24 DMA Acknowledge 7.

100

OUT24 Terminal Count. The W83628F asserts TC to DMA slaves as a

terminal count indicator.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 8 - Revision 0.50

K/B , GPIO AND 80h PCS# Function

SYMBOL

PIN

I/O

FUNCTION

80PCS#

KBEN#

I/OD12t 80h PORT Chip Select.(Default)

K/B Functions Enable. During power-on reset this pin is weak
pulled-up internally. The pin applied a pull-down resistor (4.7K
ohm) to enable K/B functions. (IRQ1,KBCS#,and MCCS#)

ROMCS#

I/OD12t ROMCS#, this pin enable positive decoder of BIOS address range

[depend on CR03 ,bit 1 or external weak pulled-up during PCIRST
is asserted] .

GPIO0

IRQ1

I/OD12t General purpose I/O pin 0.

Parallel Interrupt Requested Input 1. This interrupt request is used
for specific K/B functions.

GPIO1

KBCS#

I/O12t

General purpose I/O pin 1.

Decode the address 60h and 64h to output chip selected signal.
Enable by KBEN# power-on setting.

GPIO2

MCCS#

I/OD12t General purpose I/O pin 2.

Decode the address 62h and 66h to output chip selected signal
Enable by KBEN# power-on setting

GPIO3

IRQIN

I/OD12t General purpose I/O pin 3.

Programmable parallel IRQ input transfers to serial IRQ
Enable by KBEN# power-on setting

GPIO4

PLED

I/OD12t General purpose I/O pin 4.

Power LED output, this signal is low after system reset.

GPIO5

IRQ8

I/OD12t General purpose I/O pin 5.

Parallel Interrupt Requested Input 8. This interrupt request is used
for specific RTC functions. Enable by RTCEN# power-on setting

GPIO6

RTCCS#

I/OD12t General purpose I/O pin 6.

Decode the address 70h and 71h to output chip selected signal
Enable by RTCEN# power-on setting

GPIO7

IOHCS#

I/OD12t General purpose I/O pin 7.

Decode SA[15-11] are all 0 and setting by CR04 Bit 6.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 9 - Revision 0.50

Clock Buffer and Generator

SYMBOL

PIN

I/O

FUNCTION

14.318M

INt

Main 14.318 MHz Clock Input.

14MOUT 1

OUT12t 14.318 MHz Buffer Output 1.

14MOUT 2

OUT12t 14.318 MHz Buffer Output 2.

24.576M
25.000M

OUT12t This pin is weak pull-up during 3 V

ramp-up period. The default

setting is 24.576 MHz and selected 25.000 MHz by external
pull-down with 4.7K ohm (recommended) during power ramp-up
period.
24.576 MHz Clock Output for Audio Codec or selected 25.000
MHz Clock Output for LAN on board solution.

Power Signals

SYMBOL

PIN

I/O

FUNCTION

VCC5

5, 45, 55, 70, 85, 105, 120,

PWR

Digital 5V Supply.

VCC3

PWR

Digital 3.3V Supply.

GND

15, 50, 60, 80, 95, 110, 125

PWR

Digital Ground.

AVCC3

PWR

Analog 3.3V Supply.

AGND

PWR

Analog Ground.

Power-on strapping Signals

SYMBOL

PIN

I/O

FUNCTION

80PCS#/KBEN#

I/OD12t

Power-on strapping with

pulled-down register will enable

K/B and mouse functions. When it

is set, pin 38 , 39 and 40 will do
IRQ1, KBCS# and MCCS# signals.

ROMCS#

I/OD12t

If there is a boot-ROM (BIOS) ,the

signal must power-on with a weak
pulled-high register.

MASTER/RTCEN#

123

INt

Power-on strapping with

pulled-down register will enable

RTC functions. When it is set, pin

64 and 65 will do IRQ8 and RTCCS#

signals.

DACK6#/HEFRAS

128

I/OD24t

Set this function will change the

port that is used to access

configuration-registers . Default

setting is 4Eh ,but by power-on

strapping with a pulled-down
register change to 2Eh.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 10 - Revision 0.50

CONFIGURATION REGISTER

1 Chip (Global) Control Register

Enable the following configuration registers by writing 26h to the location 4Eh twice.

Change the location to 2Eh by setting bit4 of CR03 or power-on strapping with a
pulled-down register on pin 128

CR03 (ROM Decoder Register, Default , 100011s0b)

Bit 7-5

Reserved.

Bit4

Configure Address and Value

= 0 Write 26h to the location 4E twice. (4Eh and 4Fh are index and data port)

= 1 Write 26h to the location 2E twice(By DACK6 power-on setting with

weak pull-down resistor).(The pair are 2Eh and 2Fh)

Bit 3-2

BIOS Decode Range of High Memory.

= 00 1MB BIOS ROM positive decode.
= 01 2MB BIOS ROM positive decode.
= 10 4MB BIOS ROM positive decode.
= 11 8MB BIOS ROM positive decode. (Default setting)

Bit 1

BIOS ROM decoder Enable.

= 0 Disable BIOS ROM decoder. (Default setting)
=1 Enable BIOS ROM decoder.

Bit 0

BIOS Protected Mode.

=0 BIOS Writed Disable. (Default setting)
=1 BIOS Writed Enable.
This bit set to " 1 " for updated BIOS used allow Memory R/W to the range
of BIOS decoded. This bit is always set to " 0 " after reset.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 11 - Revision 0.50

CR04

(

GPIO Status Register

, Default 0ss00sssb)

If the GPIO is selected GPIO function, it will be controlled by CR10,13,14,15,and 16.The pins were

set non-GPIO functions by power-on setting pin or software programmed.

Bit 7(GPIO7) : = 1 Signal used as IOHCS# (Set by software only)

= 0 Signal used as GPIO function (Default)

Bit 6 (GPIO6): = 1 Signal used as RTCCS# (Set by pin123 RTCEN# )

= 0 Signal used as GPIO function (Default)

Bit 5 (GPIO5): = 1 Signal used as IRQ8 (Set by Pin 123 RTCEN# )

= 0 Signal used as GPIO function (Default)

Bit 4 (GPIO4): = 1 Signal used as PLED ( Set by software only and programmed by CR CR17 bit [5,4])

= 0 Signal used as GPIO function . (Default)

Bit 3 (GPIO3): = 1 Signal used as IRQIN (depended on CR17 bit[3..0])

= 0 Signal used as GPIO function (Default)

Bit 2 (GPIO2): = 1 Signal used as MCCS# (decode address 62h and 66h )

by Pin 36 KBEN# power-on setting

= 0 Signal used as GPIO function (Default)

Bit 1 (GPIO1): = 1 Signal used as KBCS# (decode address 60h and 64h)

by Pin 36 KBEN# power-on setting

= 0 Signal used as GPIO (Default)

Bit 0 (GPIO0): = 1 Signal used as IRQ1 by Pin 36 KBEN# power-on setting

= 0 Signal used as GPIO (Default)

CR05

(

System Clock Register ,

Default 0x4D)

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 12 - Revision 0.50

Bit 7

SYSCLK Divider.

= 0 SYSCLK is equal to PCICLK divided by 4.

= 1 SYSCLK is equal to PCICLK divided by 3.

Bit 6

8-bit I/O Recovery Enable

= 0 Disable bit [5:3] setting and uses 3.5 SYSCLKs for 8 bit I/O recovery time.

= 1 Enable bit [5:3] setting.

Bit 5:3

8-bit I/O Recovery Times .

When bit 6= 1 , these 3 bits field define the additional number of SYSCLKs added

to standard 3.5 SYSCLK recovery time for 8 bit I/O

= 000 0 SYSCLK

= 001 1 SYSCLK

= 010 2 SYSCLKs

= 011 3 SYSCLKs

= 100 4 SYSCLKs

= 101 5 SYSCLKs

= 110 6 SYSCLKs

= 111 7 SYSCLKs

Bit 2 = 0 Ignore bits [1:0] setting and uses 3.5 SYSCLKs for 16-bit I/O recovery
time.

= 1 The 16-bit I/O recovery time is decided by bits 1:0.

Bit 1:0

16-bit I/O Recovery Times.

When bit 2 = 1 , this 2-bit field defines the additional number of SYSCLKs added

to standard 3.5 SYSCLK recovery time for 16 bit I/O

= 01 1 SYSCLK

= 10 2 SYSCLKs

= 11 3 SYSCLKs

= 00 4 SYSCLKs

CR10

(

GPIO0-GPIO7 Function Enable Register,

Default 0x00)

Bit 7 - 1: Reserved.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 13 - Revision 0.50

Bit 0:

GPIO Function Activity.

= 1 All GPIO functions are activated . All registers (CR 11,12,13,14,15,16)

about GPIO function will be set default value .

= 0 All GPIO functions are inactive except the signals by power-on setting.

If any one of CR04 bit [7..0] was set non-GPIO function,the bit just affect

which was set GPIO function .

CR11, CR12

(

Reserved Register For GPIO Control Without Configure Mode Entry

)

The register is programmable when the bit 0 of CR10 is set to " 1 " and affected by
the settings of CR14 ( I/O Selectioin ) and CR16 ( Inversion ).

User defines port address to control GPIO functions. To control GPIO state without entry

configure mode. SA [0..7] can be defined on the bit [0..7] of CR11 and SA [8..15] on the bit [

0..7] of CR12.
For example:
Define address 50h in CR11 and 01h in CR12 after reset.
bit 0= -GPIO0 (=0 low state,
=1 Hi state )
bit 1=-GPIO1 (=0 low state
=1 Hi state)
,bit 2=GPIO2,.........,bit 7=GPIO7 the same definition as bit 0.
Set CR14 to " 00h " (output port) and CR16 to " 00h " (incoming/outgoing)
-o 150 aa ------(10101010) b indicated GP7,GP5,GP3 and GP1 are Hi state.
-o 150 55 ------(01010101) b indicated GP6,GP4,GP2,and GP0 are Hi state.
- i 150 ------show all states of GPIO[7..0]

CR13

(

GPIO0-GPIO7 Address Decoder Rester,

Default 0x00 )

The register is programmable when the bit 0 of CR10 is set to " 1 ".

Bit 7:

Address Decoder 2

=1 Enable address decoder .Generate a CS# signal to GPIO port which

decided by bit[6..4] ,the specify address in CR34 and CR35 and mask
range in CR 33.

0 Disable address decoder.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 14 - Revision 0.50

Bit 6 -Bit 4 :

Address Decoder 2 Output Selection.

Define which GP port as address decoder depended on CR33,CR34 and CR35.

= 000 Selected GPIO 0 as CS# output

= 001 Selected GPIO 1 as CS# output

= 010 Selected GPIO 2 as CS# output

= 011 Selected GPIO 3 as CS# output

= 100 Selected GPIO 4 as CS# output

= 101 Selected GPIO 5 as CS# output

= 110 Selected GPIO 6 as CS# output

= 111 Selected GPIO 7 as CS# output

Bit 3:

Address Decoder 1

=1 Enable address decoder . Generate a CS# signal to GPIO port which

decided by bit[6..4] ,the specify address in CR31 and CR32 and mask
range in CR 30.

0 Disable address decoder.

Bit 2 -Bit 0 :

Address Decoder 1 Output Selection.

Define which GP port as address decoder depend on CR30,CR31 and CR32.

= 000 Selected GPIO 0 as CS# output

= 001 Selected GPIO 1 as CS# output

= 010 Selected GPIO 2 as CS# output

= 011 Selected GPIO 3 as CS# output

= 100 Selected GPIO 4 as CS# output

= 101 Selected GPIO 5 as CS# output

= 110 Selected GPIO 6 as CS# output

= 111 Selected GPIO 7 as CS# output

CR14

(

GPI0-GPIO7 I/O Selection Register,

Default 0xFF)

The register is programmable when the bit 0 of CR10 is set to " 1 ".

Bit [7..0] are corresponding with GPIO [7..0] .

When set to a '1', respective GPIO port is programmed as an input port.

When set to a '0', respective GPIO port is programmed as an output port.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 15 - Revision 0.50

CR15

(

GPIO0-GPIO7 Data Register,

Default 0x00)

The register is programmable when the bit 0 of CR10 is set to " 1 ".

Bit [7..0] are corresponding with GPIO [7..0] .

If a port is programmed to be an output port, then its respective bit can be read/written.

If a port is programmed to be an input port, then its respective bit can only be read.

CR16

(

GPIO0-GPIO7 Inversion Register,

Default 0x00)

The register is programmable when the bit 0 of CR10 is set to " 1 ".

Bit [7..0] are corresponding with GPIO [7..0] .

When set to a '1', the incoming/outgoing port value is inverted.

When set to a '0', the incoming/outgoing port value is the same as in data register.

CR17

(

Power LED & IRQIN Control Register,

Default 0x00)

Bit 7 -6:Reserved

Bit 5 -4: =00 Power LED pin is tri-stated.

=01 Power LED pin is driven low.

=10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle.

=11 Power LED pin is a 1/4 Hz toggle pulse with 50 duty cycle.

Bit 3 - 0: These bits select IRQ resource for IRQIN. Four bits transfer the decimal value to octal

system. For example: Bit [3..0] = 1001b = 0x9h means IRQ 9 be selected.

Bit [3..0] = 1100b = 0xCh means IRQ12 be selected

CR20

(

Chip ID Register 1,

Default 0x62)

Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 =

0x 62

(read only).

CR21

(

Chip ID Register 2 ,

Default 0x6x)

Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 =

0x61

(read only).

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 16 - Revision 0.50

Bit [3..0] indicate the version of the chip.

CR30

(

Mask Range of Address Decoder 1 Register,

Default 0x00)

This register is used to mask address bits (A7~A0) for specify address decoder, if the corresponding bit
of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the specify address
decoder.

For example: If the decoding range is 0x3F8 ~ 0x3FF,you can set 0x3F8 to CR 31, 32 and 07h to

CR30 .

CR31, 32

(

Address Decoder 1 Specification Register ,

Default 0x00)

This register contains the address for specify decoder.

CR 31 Bit [7..0] are used to define low byte of specity address.

CR 32 Bit [7..0] are used to define high byte of specify address.

For example: Decoding address was set to be 0x3F5h and write F5h to CR 31 and 03h to CR 32 .

CR33

((

Mask Range of Address Decoder 2 Register,

Default 0x00)

This register is used to mask address bits(A7~A0) for specify address decoder , if the corresponding bit
of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the specify address
decoder .

For example: If the decoding range is 0x3F8 ~ 0x3FF,you can set 0x3F8 to CR 34, 35 and 07h to

CR33 .

CR34, 35

Address Decoder 2 Specification Register ,

Default 0x00)

This register contains the address for specify decoder.

CR 34 Bit [7..0] are used to define low byte of specity address.

CR 35 Bit [7..0] are used to define high byte of specify address.

For example: Decoding address was set to be 0x3F5h and write F5h to CR34 and 03h to CR35.

This register contains the address for specify decoder.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 17 - Revision 0.50

CR40

(

Clock controllable Register ,

Default 0x00)

This register is used to enable clock power-down state of the chip. It will shut down 14.318MHz.

Bit 7 -1: Reserved.

Bit 0 : =1 Power down mode.When entry power down mode , clock output will be turn off.

=0 Normal used.

CR41

(

Clock tested Register ,

:Reserved for Winbond internal test)

CR42

(

Tristate controllable Register(Power-down Mode1) ,

Default 0x1B)

Bit 7 : REFRESH Cycles Tristated.

Bit 6 : SYSCLK Output Tristated.

Bit 5 : Address Signals Tristated Enable.

Bit 4 - 0 : Defined tristated address signals range.(See Table 1)

For example:
Define address Bit[4..0] = 0x10h
SA [19..16] and LA [23..17] signals will be tristated.
Table 1

Set value(Hex)

Tri_state range

Workable

SA[19..0] and LA[23..17]

None one

SA[19..1] and LA[23..17]

SA[0]

SA[19..2] and LA[23..17]

SA[1..0]

.
.

LA[23..17]

SA[19..0]

Set value(Hex)

Tri_state range

Workable

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 18 - Revision 0.50

LA[23]

SA[19..0] and LA[22..17]

None one

SA[19..0] and LA[23..17]

CR43

(

Tristate controllable Register(Power-down Mode2

)

Default 0x07)

The Fast mode is used to improve the performance of transferable interface, because some
applications will do fast transaction . To set the suitable bits to decide on specify range or all ISA cycles
will meet the requested I/O cycles.

Bit 7 : Reserved.

Bit 6 : = 1 Enable Fast mode by ADDRESS DECODER 2 and SYSCLK is depended on

the state of Bit 3 .

= 0 ADDRESS DECORDER 2 doesn't affect Fast Mode and do original operation.

Bit 5 : = 1 Enable Fast mode by ADDRESS DECODER 1 and SYSCLK is depended on

the state of Bit 3.

= 0 ADDRESS DECORDER 1 doesn't affect Fast Mode and do original operatio

Bit 4 : = 1 Enable Fast Mode of whole chip, whole ISA cycle of this bridge will be done

Fast Mode operation and SYSCLK is depended on the state of Bit 3.

= 0 Normal operation, just Bit 6 and Bit 5 can affect Fast Mode operation.

Bit 3 : = 1 SYSCLK is equal to PCICLK divided by 1 when decoding range is in Fast Mode.

= 0 SYSCLK is equal to PCICLK divided by 2 when decoding range is in Fast Mode.

Bit 2 : = 1 Disabled Memory cycles.

= 0 Normal used.

Bit 1 : = 1 Forced 16 bit cycles .

= 0 Normal used.

Bit 0 : = 1 8-bit data bus decode only. Only SD [7..0] signals are active.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 19 - Revision 0.50

= 0 Normal used.

CR44

(

Tristate controllable Register(Power-down Mode3) ,

Default 0x07)

Bit 7 : =1 Enable Power-down functions.(ISOLATE# was power-on setting.)

=0 Normal used.

Bit 6 : Reserved.

Bit 5 : =1 SA10 is set as mask (ignored) bit in ADDRESS DECODER 2. The function is used to improved

the performance of ECP mode of LPT. If the decoding range is 0x378-0x37F and 0x778-0x77F

,you can set this bit to 1 for Fast Mode operation.

= 0 Normal operation.

Bit 4 : =1 SA10 is set as mask (ignored) bit in ADDRESS DECODER 1. The function is used to improved

the performance of ECP mode of LPT. If the decoding range is 0x378-0x37F and 0x778-0x77F

,you can set this bit to 1 for Fast Mode operation.

= 0 Normal operation.

Bit 3 : SERIRQ POWER DOWN SELECT.

=1 When the chip is in power down mode, the SERIRQ block is inactive.

=0 When the chip is in power down mode, the SERIRQ block is active.

Bit 2 -0 : Set SYSCLK divided ratio.(2,4,8,16,32,64)

= 000 Disable Power-down Mode3.

= 001 SYSCLK divided by 2.

= 010 SYSCLK divided by 4.

= 010 SYSCLK divided by 4

= 011 SYSCLK divided by 8

= 100 SYSCLK divided by 16

= 101 SYSCLK divided by 32

= 110 SYSCLK divided by 64

= 111 LPC I/F,all clocks and signals will be tristated.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 20 - Revision 0.50

CR45

(

Wake-Up Event Register,

Default 0x01)

Bit 7 :=0 Normal used.

=1 Wake up from power-down mode by IRQ 7 occurred.

Bit 6 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 6 occurred.

Bit 5 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 5 occurred.

Bit 4 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 4 occurred .

Bit 3 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 3 occurred.

Bit 2 :Reserved.

Bit 1 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 1 occurred.

Bit 0 : =0 Normal used.

=1 Wake up from power-down mode by rising edge of ISOLATE# signal occurred.

CR46

(

Wake-Up Event Register,

Default 0x00)

Bit 7 -5:Reserved

Bit 4 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 12 occurred .

Bit 3 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 11 occurred.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 21 - Revision 0.50

Bit 2 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 10 occurred.

Bit 1 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 9 occurred.

Bit 0 : =0 Normal used.

=1 Wake up from power-down mode by IRQ 8 occurred.

CR48

(

DMA CYCLES FAST MODE SELECT,

Default 0x00) (

Write only

)

Bit 7 : = 0 Normal used.

= 1 The DMA cycles of channel 7 is in fast mode.

Bit 6 : = 0 Normal used.

= 1 The DMA cycles of channel 6 is in fast mode.

Bit 5 : = 0 Normal used.

= 1 The DMA cycles of channel 5 is in fast mode.

Bit 4 : Reserved.

Bit 3 : = 0 Normal used.

= 1 The DMA cycles of channel 3 is in fast mode.

Bit 2 : = 0 Normal used.

= 1 The DMA cycles of channel 2 is in fast mode.

Bit 1 : = 0 Normal used.

= 1 The DMA cycles of channel 1 is in fast mode.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 23 - Revision 0.50

REVISION NOTICES.

a. 4/16/1999 modified page 2, 3 to correct wrong typewrite and changed to Rev 0.02.

b. 5/18/1999 modified page 1,3 to define K/B functions , 80portCS# and IRQINX.Changed

ROMCS#from pin 39 to pin37.page 8,added and modified the function description and

changed to Rev0.03

c.5/27/1999 modified page 7 to add power-on setting function in DACK6# for entry port of

configure mode(HERFRA). In page 6,Master# was added RTCEN power-on setting function.

In page 8,80PCS# was added KBEN power-on setting function and GPIO 5 added a new

function IRQ8,GPIO6 added RTCCS#,and GPIO7 added IOHCS#.Rev 0.04 changed.

d.5/31/1999 Added Power-Down functin in islate#( page 5)and PLED function in GPIO3(page 8)

IRQIN2 was removed and IRQIN1 modified to IRQIN.

e.6/8/1999 Renamed ISOLATE# to PWRDN# and corrected RTCCS# decode address

(71,72--> 70,71),

f. 6/9/1999 modified the function descriptioin of pin 29.Rev 0.05 changed.

g.7/9/1999 Combined configuration register and modified new schematic.Rev 0.06.

h.7/21/1999 Modified default value of CR and add ed some descriptions and corresponding table.

Rev 0.07.

i. 8/24/1999 Modified recommended circuit and register descriptions. Corrected power-on setting

description of signal ROMCS# . Rev 0.10.

j.10/08/1999 modified pin configuration ,pin62 and 63.Rev 0.11

k. 11/16/1999 Modified schematic circuit and added the function description of CR43 and CR44. Rev

0.12.

l. 02/20/2000 Add new pacake 100-LQFP (W83626D) dimention

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 24 - Revision 0.50

Package DIMENSIONS 1 for W83626F (128-pin PQFP)

Detail F

102

1.Dimension D & E do not include interlead

flash.

2.Dimension b does not include dambar

protrusion/intrusion

3.Controlling dimension : Millimeter

4.General appearance spec. should be based

on final visual inspection spec.

Note:

Seating Plane

See Detail F

128

103

5. PCB layout please use the "mm".

Symbol

c
D

e
H

y
0

A
A

0.08

1.60

0.95

17.40

0.80

17.20

0.65

17.00

14.10

0.20

0.30

2.87

14.00

2.72

0.50

13.90

0.10

2.57

0.25

Min

Nom

Max

Dimension in mm

0.20

0.15

19.90

20.00

20.10

23.00

23.20

23.40

0.35

0.45

0.003

0.063

0.037

0.685

0.031

0.677

0.025

0.669

0.020

0.555

0.008

0.012

0.113

0.551

0.107

0.547

0.004

0.101

0.010

Max

Nom

Min

Dimension in inch

0.006

0.008

0.783

0.787

0.791

0.905

0.913

0.921

0.014

0.018

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 25 - Revision 0.50

Package DIMENSIONS 2 for W83626D (128-pin LQFP)

Detail F

102

1.Dimension D & E do not include interlead

flash.

2.Dimension b does not include dambar

protrusion/intrusion

3.Controlling dimension : Millimeter

4.General appearance spec. should be based

on final visual inspection spec.

Note:

Seating Plane

See Detail F

128

103

5. PCB layout please use the "mm".

Symbol

c
D

e
H

y
0

0.08

1.00

0.75

-----

0.60

16.00

0.45

-----

14.10

0.20

0.23

1.45

14.00

1.40

0.40 BSC

13.90

0.10

0.13

1.35

0.05 -----

Min

Nom

Max

Dimension in mm

0.16

-----

19.90

20.00

20.10

-----

22.00

-----

0.15

0.003

0.039

0.030

-----

0.024

0.630

0.018

-----

0.016

0.555

0.008

0.009

0.057

0.551

0.055

0.547

0.004

0.005

0.053

0.002

Max

Nom

Min

Dimension in inch

-----

0.006

0.783

0.787

0.791

-----

0.866

-----

----

0.006

-----

Headquarters

No. 4, Creation Rd. III

Science-Based Industrial Park

Hsinchu, Taiwan

TEL: 886-35-770066

FAX: 886-35-789467

www: http://www.winbond.com.tw/

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.

Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502

TLX: 16485 WINTPE

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II

123 Hoi Bun Rd., Kwun Tong

Kowloon, Hong Kong

TEL: 852-27516023-7

FAX: 852-27552064

Winbond Electronics
(North America) Corp.

2730 Orchard Parkway

San Jose, CA 95134 U.S.A.

TEL: 1-408-9436666

FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the trade marks of
products and companies mentioned in this data sheet belong to their original owners

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 15 - Revision 0.50

Recommended circuit for Desktop

626_1.SCH

W83626F FOR LPC TO ISA BRIDGE

Tuesday, November 16, 1999

Title

Size

Document Number

Date:

VCC3
VCC5

VCC5

AVCC3

VCC5

C1
0.1UF

C2
0.1UF

C3
0.1UF

C4
0.1UF

C5
0.1UF

C6
10UF/16V

W83626F

100

101

102

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

DRQ5

DACK5#

DRQ0

DACK0#

VCC5

IRQ14

IRQ15

IRQ12

IRQ11

IRQ10

IOCS16#

MEMCS16#

LFRAM#

PCIRST#

GND

LAD3

LAD2

LAD1

LAD0

VCC3

PCICLK

LDRQ#

SERIRQ

PWRDN#

AVCC3

14.318M

14MOUT1

14MOUT2

24.576M

AGND

SA0

SA1

SA2

SA3

SA4

80PCS#/KBEN#

ROMCS#

GPIO0/IRQ1

GPIO1/KBCS#

GPIO2/MCCS#

SA5

SA6

SA7

SA8

VCC5

SA9

SA10

SA11

SA12

GND

SA13

SA14

SA15

SA16

VCC5

SA17

SA18

SA19

AEN

GND

IOCHRDY

GPIO3/IRQIN

GPIO4/PLED

GPIO5/IRQ8

GPIO6/RTCCS#

GPIO7/IOHCS#

SD0

SD1

SD2

VCC5

SD3

SD4

SD5

SD6

SD7

IOCHCK#

RSTDRV

IRQ9

DRQ2

GND

OWS#

SMEMW#

SMEMR#

IOW#

VCC5

IOR#

DACK3#

DRQ3

DACK1#

DRQ1

REFRESH#

SYSCLK

IRQ7

IRQ6

GND

IRQ5

IRQ4

IRQ3

DACK2#

BALE

SBHE#

LA23
LA22
VCC5
LA21
LA20
LA19
LA18
GND
LA17
MEMR#
MEMW#
SD8
SD9
SD10
SD11
SD12
SD13
VCC5
SD14
SD15
MASTER#/RTCEN#
DRQ7
GND
DACK7#
DRQ6
DACK6#/HEFRAS

4.7K

DRQ0

DACK0#

IRQ11
IRQ10

LFRAM#

24.576M

OSC
14.318M

SERIRQ
LDRQ#
PCICLK

IOCHRDY

AEN

RSTDRV

IRQ9

DRQ2

DACK2#

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

DRQ1

DACK1#

DACK3#

IOR#

IOW#

PCIRST#

DRQ3

LAD[3..0]

IOHCS#

PWRDN#

ROMCS#

IRQ1

KBCS#

MCCS#

MEMR#

MEMW#

OWS#

DRQ5

DACK0#

IRQ14
IRQ15
IRQ12

IOCS16#

MEMCS16#

DACK6#

DACK7#

DRQ6

DRQ7

MASTER#

IOCHCK#

FOR AC97 CODEC

LAD[3..0]

SA[19..0]

SD[7..0]

If do not use the GPIO function pin
please pull-down with a resistor.

NOTE1:

NOTE2:
If do not use the clock output function
,please connect to GND.(Pin 27,28&29)

NOTE9 :
For RTC functions power-on
setting used .

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 16 - Revision 0.50

626_2.SCH

0.3

W83626 FOR LPC TO ISA BRIDGE

Tuesday, August 17, 1999

Title

Size

Document Number

Rev

Date:

Sheet

VCC3

VCC5

VCC3

VCC5

VCC3

-5V

-12V

+12V

VCC5

5VSB

-5V

+12V
VCC3

-12V

+3.3V

PULL HIGH or PULL DOWN RESISTOR

For 8M BIOS

ROM decode

seeting used

For ROMCS# power-on

Flash ROM Decoder

(PLCC)

NOTE4:

LPC I/F

ISA SLOT

Resvered for wake-up

CB1
0.1uF

CB2
0.1uF

CB3
0.1uF

CB4
0.1uF

RP1

8.2K

2
3
4
5
6
7
8
9

RP2

8.2K

2
3
4
5
6
7
8
9

RP3

8.2K

2
3
4
5
6
7
8
9

RP4

8.2K

2
3
4
5
6
7
8
9

RP5

8.2K

2
3
4
5
6
7
8
9

RP6

8.2K

2
3
4
5
6
7
8
9

A/B CHANNEL

IOCHCK#

GND

RESDRV

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

IORDY

AEN

SA19

SA18

SA17

SA16

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

+5V

IRQ9

-5V

DRQ2

-12V

0WS

+12V

GND

SMEMW#

SMEMR#

IOW#

IOR#

DACK3#

DRQ3

DACK1#

DRQ1

REF#

CLK

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

DACK2#

T/C

BALE

OSC

GND

C/D CHANNEL

SBHE

LA23

LA22

LA21

LA20

LA19

LA18

LA17

MEMR#

MEMW#

SD08

SD09

SD10

SD11

SD12

SD13

SD14

SD15

GND

MASTER#

+5V

DRQ7

DACK7#

DRQ6

DACK6#

DRQ5

DACK5#

DRQ0

DACK0#

IRQ14

IRQ15

IRQ12

IRQ11

IRQ10

IOCS16#

MECS16#

LPC CON1

CON20B

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

RP7

8.2K

2
3
4
5
6
7
8

CB5
0.1uF

CB6
0.1uF

CB7
0.1uF

4.7K

8.2K

R10

8.2K

R11

8.2K

R12

8.2K

C7
10uF/16V

C8
10uF/16V

C9
10uF/16V

C10
10uF/16V

R13

WINBOND ELECTRONICS CORP.

inbond

W29C040P-90

A18

A17

A16

A15

A14

A13

A12

A11

A10

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC

GND

CE#

OE#

WE#

R14

4.7K

RP8

8.2K

2
3
4
5
6
7
8

R15

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

AEN

IOCHRDY

RSTDRV

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ9

IRQ10
IRQ11
IRQ12

IRQ14

IRQ15

DRQ0

DRQ1

DRQ3

DRQ2

DRQ5

DRQ6

DRQ7

DACK0#

DACK1#

DACK3#

DACK5#

DACK6#

DACK7#

MASTER#

IOCS16#

LA17

LA18

LA19

LA20

LA21

LA22

LA23

SBHE#

MEMR#
MEMW#

SMEMR#

SMEMW#

IOR#

IOW#

SYSCLK

DACK2#

BALE

IOCHRDY

MASTER#

REFRESH#

IOR#

MEMR#

MEMCS16#

IOCS16#

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

LA17

LA18

LA19

LA20

LA21

LA22

LA23

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8

SD9

SD10
SD11
SD12
SD13
SD14
SD15

SMEMR#

SMEMW#

IOCHCK#

OWS#

IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9

IRQ10
IRQ11
IRQ12

IRQ15

DRQ0
DRQ1
DRQ2
DRQ3
DRQ5
DRQ6

IOW#

IRQ14

DRQ7

PCICLK

SERIRQ

LDRQ#

LAD0
LAD1

LAD3

LAD2

PCIRST#

SMDAT
SMCLK

LAD0
LAD1
LAD2
LAD3

SERIRQ

IOCHCK#

OWS#

OSC

LDRQ#

LFRAM#

MEMW#

SA[18..0]

SD[7..0]

MEMR#

MEMW#

ROMCS#

PWRDN#

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 18 - Revision 0.50

626_1.SCH

W83626F FOR LPC TO ISA BRIDGE

Tuesday, November 16, 1999

Title

Size

Document Number

Date:

VCC3
VCC5

VCC5

AVCC3

VCC5

C1
0.1UF

C2
0.1UF

C3
0.1UF

C4
0.1UF

C5
0.1UF

C6
10UF/16V

W83626F

100

101

102

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

DRQ5

DACK5#

DRQ0

DACK0#

VCC5

IRQ14

IRQ15

IRQ12

IRQ11

IRQ10

IOCS16#

MEMCS16#

LFRAM#

PCIRST#

GND

LAD3

LAD2

LAD1

LAD0

VCC3

PCICLK

LDRQ#

SERIRQ

PWRDN#

AVCC3

14.318M

14MOUT1

14MOUT2

24.576M

AGND

SA0

SA1

SA2

SA3

SA4

80PCS#/KBEN#

ROMCS#

GPIO0/IRQ1

GPIO1/KBCS#

GPIO2/MCCS#

SA5

SA6

SA7

SA8

VCC5

SA9

SA10

SA11

SA12

GND

SA13

SA14

SA15

SA16

VCC5

SA17

SA18

SA19

AEN

GND

IOCHRDY

GPIO3/IRQIN

GPIO4/PLED

GPIO5/IRQ8

GPIO6/RTCCS#

GPIO7/IOHCS#

SD0

SD1

SD2

VCC5

SD3

SD4

SD5

SD6

SD7

IOCHCK#

RSTDRV

IRQ9

DRQ2

GND

OWS#

SMEMW#

SMEMR#

IOW#

VCC5

IOR#

DACK3#

DRQ3

DACK1#

DRQ1

REFRESH#

SYSCLK

IRQ7

IRQ6

GND

IRQ5

IRQ4

IRQ3

DACK2#

BALE

SBHE#

LA23
LA22
VCC5
LA21
LA20
LA19
LA18
GND
LA17
MEMR#
MEMW#
SD8
SD9
SD10
SD11
SD12
SD13
VCC5
SD14
SD15
MASTER#/RTCEN#
DRQ7
GND
DACK7#
DRQ6
DACK6#/HEFRAS

inbond

WINBOND ELECTRONICS CORP.

4.7K

DRQ0

DACK0#

IRQ11
IRQ10

LFRAM#

24.576M

OSC
14.318M

SERIRQ
LDRQ#
PCICLK

IOCHRDY

AEN

RSTDRV

IRQ9

DRQ2

DACK2#

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

DRQ1

DACK1#

DACK3#

IOR#

IOW#

PCIRST#

DRQ3

LAD[3..0]

SA[19..0]

SD[7..0]

IOHCS#

PWRDN#

ROMCS#

IRQ1

KBCS#

MCCS#

MEMR#

MEMW#

OWS#

DRQ5

DACK0#

IRQ14
IRQ15
IRQ12

IOCS16#

MEMCS16#

DACK6#

DACK7#

DRQ6

DRQ7

MASTER#

IOCHCK#

FOR AC97 CODEC

LAD[3..0]

SA[19..0]

SD[7..0]

If do not use the GPIO function pin
please pull-down with a resistor.

NOTE1:

NOTE2:
If do not use the clock output function

NOTE3:

setting used

,please connect to GND.(Pin 27,28&29)

For K/B functions power-on

NOTE8 :
For 25.000 MHz clock power-on
setting used .

NOTE9 :
For RTC functions power-on
setting used .

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 19 - Revision 0.50

626_2.SCH

0.3

W83626F FOR LPC TO ISA BRIDGE

Custom

Tuesday, August 24, 1999

Title

Size

Document Number

Rev

Date:

Sheet

VCC3

VCC5

5VCC

VCC3

CB1
0.1uF

CB2
0.1uF

CB3
0.1uF

CB4
0.1uF

RP1

8.2K

2
3
4
5
6
7
8
9

RP2

8.2K

2
3
4
5
6
7
8
9

RP3

8.2K

2
3
4
5
6
7
8
9

RP4

8.2K

2
3
4
5
6
7
8
9

CB5
0.1uF

8.2K

C7
10uF/16V

C8
10uF/16V

C9
10uF/16V

C10
10uF/16V

8.2K

RP5

8.2K

1
3
5
7

2
4
6
8

W29C040P-90

2
3

29
28

25
23
26
27

5
6
7
8

13
14
15
17
18
19
20
21

10
11

A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

VCC

GND

A3
A2
A1

CE#

OE#

WE#

4.7K

RP6

4.7K

2
3
4
5
6
7
8
9

RP7

4.7K

2
3
4
5
6
7
8
9

RP8

8.2K

1
3
5
7

2
4
6
8

RP9

8.2K

2
3
4
5
6
7
8
9

4.7K

RP10

8.2K

2
3
4
5
6
7
8

RP11

8.2K

2
3
4
5
6
7
8

R10

8.2K

inbond

WINBOND ELECTRONICS CORP.

IOCHRDY

IOR#

MEMR#

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9

IRQ10

IRQ11

DRQ0
DRQ1
DRQ2
DRQ3

IOW#

MEMW#

SA[18..0]

SD[7..0]

MEMR#

MEMW#

ROMCS#

IRQ12
IRQ14
IRQ15

MEMCS16#

IOCS16#

IOCHK#

OWS#

SMEMW#

SMEMR#

MASTER#

DRQ5
DRQ6
DRQ7

PWRDN#

LAD0
LAD1
LAD2
LAD3

SERIRQ

LDRQ#

LFRAM#

LAD0
LAD1
LAD2
LAD3

SERIRQ

LDRQ#

LFRAM#

PD[0..7]

STB#

AFD#
INIT#

SLIN#
ERR#

ACK#

BUSY

SLCT

For 8M BIOS
ROM decode

Flash ROM Decoder

ISA I/F PULL HIGH

OR PULL DOWN RESISTORS

PRT PULL-HI RESISTORS

(PLCC)

NOTE4:

For disconnected signals used

NOTE6:

The circuit is for flashable ROM
For BIOS read-only used can connect
OE# and CE# together to ROMCS# and
without MEMR# and MEMW#.

No used signals

R7 for ROMCS# power-on setting used.

NOTE7 :
Reserved for wake_up function.

LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 20 - Revision 0.50

626_3.SCH

0.3

W83626F FOR LPC TO ISA BRIDGE

Custom

Tuesday, August 24, 1999

Title

Size

Document Number

Rev

Date:

Sheet

VCC5

-12V

+12V

VCC5

PD0

PD1

PD2

CS#

PD3

PD4

PD5

SD0
SD1
SD2

PD6

SD3
SD4
SD5

PD7

SD6
SD7

HEFRAS

STB#
AFD#
PD0
ERR#
PD1
INIT#
PD2
SLIN#
PD3

PIRQMDS

PD4

PD5

PD6

PD7

ACK#

BUSY

NDCDA

NSINA

NSOUTA

NDTRA

GND

NDSRA

NRTSA

NCTSA

SLCT

NRIA

IRRXH

STB#

AFD#

PD0

RWC#

PD1

INIT#

INDEX#

PD2

MOA#

PD3

DSB#

SLIN#

DSA#
MOB#
DIR#

ERR#

STEP#
WD#
WE#

ACK#

TRAK0#
WP#
RDATA#

BUSY

HEAD#
DSKCHG#

SLCT

SA[0..10]

SD[0..7]

PD[0..7]

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

HEAD17X2

1N5817/19

W83877F/AF/TF/ATF

66
67
68
69
70
71
72
73

63
64
97
44
37
99
23
39
41

100

96
92

91
94
95
93

87
81
79
84
83
80
89
82
86
85
78
77
74
88
76

34
33
32
31
30

38
35
36

47
48
49
50
42

43
46
45

29
26
24
27
28

22
21
20
19

13
14
16

9
10
11

CS#/A11

A10

D0
D1
D2
D3
D4
D5
D6
D7

MR
AEN
IOCHRDY
IOR#
IOW#
T/C
IRQC/IRQ3
IRQD/IRQ4
IRQF/IRQ6
IRQE/IRQ7
DRQA/DRQ1
DACKA#/DACK1#
DRQB/DRQ2
DACKB#/DACK2#
DRQC/DRQ3
DACKC#/DACK3#

CLKIN

SMI#

IRQA/GIO1
IRQB/GIO0
IRQG/PCICLK
IRQH/SERIRQ
IRRX2
IRTX2
IRQIN
IRRXH/SCI#

RWC#
INDEX#
MOA#
DSB#
DSA#
MOB#
DIR#
STEP#
WD#
WE#
TRAK0#
WP#
RDATA#
HEAD#
DSKCHG#

CTSA#

DSRA#

DCDA#

RIA#

SINA

SOUTA/PENFDC

DTRA#/HEFRAS

RTSA#/PPNPCVS

CTSB#/A12

DSRB#/A13
DCDB#/A14

RIB#/A15

SINB

SOUTB/PIRQMDS

DTRB#

RTSB#/PGOIQSEL

ERR#

ACK#

BUSY

SLCT

SLIN#

INIT#

AFD#

STB#

PD3

PD4
PD5
PD6

VCC

VSS

PD0
PD1
PD2

PD7

R11

24MHz OSC

OUTPUT

CB6

0.1UF

DB25

CN2X5B

2
4
6
8

1
3
5
7
9

HEADER 5

1
2
3
4
5

TC1

10UF/16V

TC2

10UF/16V

TC3

10UF/16V

TC4

10UF/16V

TC5

10UF/16V

C11
0.1UF/16V

C12

0.1UF/6.3V

C13

0.1UF/16V

C14

0.1UF/6.3V

C15

0.1UF/16V

R12

4.7K

CB7
0.1UF

CB8
0.1UF

CB9
0.1UF

CB10
0.1UF

CB11
0.1UF

R13
4.7K

RP12

1
3
5
7

2
4
6
8

RP13

1
3
5
7

2
4
6
8

RP14

1
3
5
7

2
4
6
8

C16

180PF

C17

180PF

C18

180PF

C19

180PF

C20

180PF

C21

180PF

C22

180PF

C23

180PF

C24

180PF

C25

180PF

C26

180PF

C27

180PF

C28

180PF

C29

180PF

C30

180PF

C31

180PF

C32

180PF

MAX232E

12
14
15
16

7
6

20
21

8
5

26
22

13
17

2
3
1
28
9
4
27
16

C1+
C1-
C2+
C2-
T1IN
T2IN
T3IN
T4IN
R1OUT
R2OUT
R3OUT
R4OUT

V+

V-

T1OUT
T2OUT
T3OUT
T4OUT

R1IN
R2IN
R3IN
R4IN

R5OUT

GND

VCC

R5IN

inbond

WINBOND ELECTRONICS CORP.

AEN

DRQ2

IRQ3
IRQ4
IRQ6

DACK2#

IOR#

IOW#

CTSA
DSRA
DCDA
RIA
SINA

SOUTA
DTRA
RTSA

ERR#
ACK#
BUSY
PE
SLCT

SLIN#
INIT#
AFD#
STB#

IRQ7

IOCHRDY

DACK3#

DRQ3

DACK1#

DRQ1

PD[0..7]

SA[0..10]

IRQ5

IRRX

IRTX

SD[0..7]

FIRRX

DRQ0

DACK0#

IOHCS#

PD[0..7]

STB#

AFD#

ERR#

INIT#

SLIN#

ACK#

BUSY

SLCT

IRRX

IRTX

FIRRX

IRQ10

RSTDRV

SOUTA

RTSA

DTRA

DCDA

SINA

DSRA

CTSA

RIA

FDC

PD4
PD5
PD6
PD7

COMA

(UARTA)

IR CONNECTOR

PRT

COM

(SOP)

DRQ0 & DACK0# Set by
CR2B & CR2C

NOTE5

NSOUTA
NRTSA
NDTRA

NDCDA
NSINA
NDSRA
NCTSA
NRIA

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W83626D