Winbond LPC I/O
W83627THF
Date: August 7, 2003 Revision: 0.8
W83627THF
Publication Release Date: August 7, 2003
- 1 -
Revision 0.8
W83627THF Data Sheet Revision History
PAGES DATES VERSION
WEB
VERSION
MAIN CONTENTS
1 N.A.
01/16/2003
0.50
First published preliminary version.
2
P.104
P.117~120
03/25/2003 0.60
SUSLED data correction.
Add Item 7.8.9
3 P.116~122 04/10/2003
0.70
Update Appendix A to demo circuit
4
P.7
P.18
08/07/2003 0.80
Add Block Diagram
Add description for GP26(Pin93)
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83627THF
Publication Release Date: August 7, 2003
- II -
Revision 0.8
Table of Contents-
1.
GENERAL DESCRIPTION ......................................................................................................... 1
2.
FEATURES ................................................................................................................................. 3
3.
BLOCK DIAGRAM ...................................................................................................................... 7
4.
PIN CONFIGURATION ............................................................................................................... 8
5.
PIN DESCRIPTION..................................................................................................................... 9
5.1
LPC Interface ................................................................................................................ 10
5.2
FDC Interface................................................................................................................ 11
5.3
Multi-Mode Parallel Port ............................................................................................... 12
5.4
Serial Port Interface ...................................................................................................... 14
5.5
KBC Interface................................................................................................................ 15
5.6
Hardware Monitor Interface .......................................................................................... 16
5.7
Game Port..................................................................................................................... 17
5.8
General Purpose I/O Port ............................................................................................. 18
5.8.1
General Purpose I/O Port 1 (Power source is Vcc) ........................................................18
5.8.2
General Purpose I/O Port 2 (Power source is Vcc) ........................................................18
5.8.3
General Purpose I/O Port 3, 4 (Power source is VSB) ...................................................19
5.8.4
General Purpose I/O Port 5 (Power source is Vcc) ........................................................20
5.9
Power Pins.................................................................................................................... 20
5.10
GPIO PIN Power Source .............................................................................................. 20
6.
GENERAL PURPOSE I/O......................................................................................................... 21
7.
HARDWARE MONITOR ........................................................................................................... 24
7.1
General Description ...................................................................................................... 24
7.2
Access Interface ........................................................................................................... 24
7.3
Analog Inputs ................................................................................................................ 26
7.3.1
Monitor over 4.096V voltage:..........................................................................................26
7.3.2
CPUVCORE voltage detection method: .........................................................................27
7.3.3
Temperature Measurement Machine..............................................................................28
7.4
FAN Speed Count and FAN Speed Control ................................................................. 29
7.4.1
Fan speed count.............................................................................................................29
7.4.2
Fan speed control...........................................................................................................31
7.5
SmartFan
TM
Control ...................................................................................................... 32
7.5.1
Thermal Cruise mode .....................................................................................................32
7.5.2
Fan Speed Cruise mode.................................................................................................33
7.5.3
Manual Control Mode .....................................................................................................34
W83627THF
Publication Release Date: August 7, 2003
- III -
Revision 0.8
7.6
SMI# Interrupt Mode ..................................................................................................... 34
7.6.1
Voltage SMI# mode: .......................................................................................................34
7.6.2
Fan SMI# mode:.............................................................................................................34
7.6.3
The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes:............35
7.6.4
The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt
has two modes and it is programmed at CR[4Ch] bit 6...................................................36
7.7
OVT# Interrupt Mode .................................................................................................... 37
7.8
Registers and RAM....................................................................................................... 38
7.8.1
Address Port (Port x5h) ..................................................................................................38
7.8.2
Data Port (Port x6h)........................................................................................................38
7.8.3
Configuration Register
Index 40h...............................................................................39
7.8.4
Interrupt Status Register 1
Index 41h .........................................................................39
7.8.5
Interrupt Status Register 2
Index 42h ........................................................................40
7.8.6
SMI# Mask Register 1
Index 43h ...............................................................................41
7.8.7
SMI# Mask Register 2
Index 44h ...............................................................................41
7.8.8
Reserved Register
Index 45h--46h ...........................................................................41
7.8.9
Fan Divisor Register I
Index 47h................................................................................42
7.8.10
Value RAM
Index 20h- 3Fh......................................................................................42
7.8.11
Device ID Register - Index 49h.....................................................................................44
7.8.12
Reserved Register
Index 4Ah ..................................................................................44
7.8.13
Fan Divisor Register II - Index 4Bh...............................................................................44
7.8.14
SMI#/OVT# Control Register- Index 4Ch .....................................................................45
7.8.15
FAN IN/OUT and BEEP Control Register- Index 4Dh ..................................................46
7.8.16
Register 50h ~ 5Fh Bank Select Register - Index 4Eh .................................................47
7.8.17
Winbond Vendor ID Register - Index 4Fh.....................................................................47
7.8.18
Winbond Test Register -- Index 50h - 55h (Bank 0) .....................................................48
7.8.19
BEEP Control Register 1-- Index 56h (Bank 0) ............................................................48
7.8.20
BEEP Control Register 2-- Index 57h (Bank 0) ............................................................49
7.8.21
Chip ID -- Index 58h (Bank 0) .......................................................................................49
7.8.22
Diode Selection Register -- Index 59h (Bank 0).........................................................50
7.8.23
Reserved -- Index 5Ah (Bank 0) ...................................................................................50
7.8.24
Reserved -- Index 5Bh (Bank 0) ...................................................................................50
7.8.25
Reserved -- Index 5Ch (Bank 0) ...................................................................................50
7.8.26
VBAT Monitor Control Register -- Index 5Dh (Bank 0) .................................................51
7.8.27
Reserved Register --5Eh (Bank 0)................................................................................51
7.8.28
Reserved Register --5Fh (Bank 0)................................................................................51
7.8.29
CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) ..
.....................................................................................................................................52
7.8.30
CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1)52
7.8.31
CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) ................53
W83627THF
Publication Release Date: August 7, 2003
- IV -
Revision 0.8
7.8.32
CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) ..53
7.8.33
CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) ...54
7.8.34
CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h
(Bank1) .........................................................................................................................54
7.8.35
CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank
1) ..................................................................................................................................55
7.8.36
AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)...
.....................................................................................................................................55
7.8.37
AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)56
7.8.38
AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2).................56
7.8.39
AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) ..57
7.8.40
AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) ...57
7.8.41
AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h
(Bank 2) ........................................................................................................................58
7.8.42
AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank
2) ..................................................................................................................................58
7.8.43
Interrupt Status Register 3 -- Index 50h (BANK4).........................................................59
7.8.44
SMI# Mask Register 3 -- Index 51h (BANK 4)............................................................59
7.8.45
Reserved Register -- Index 52h (Bank 4) .....................................................................60
7.8.46
BEEP Control Register 3-- Index 53h (Bank 4) ............................................................60
7.8.47
SYSTIN Temperature Sensor Offset Register -- Index 54h (Bank 4) ...........................60
7.8.48
CPUTIN Temperature Sensor Offset Register -- Index 55h (Bank 4) ...........................61
7.8.49
AUXTIN Temperature Sensor Offset Register -- Index 56h (Bank 4) ...........................61
7.8.50
Reserved Register -- Index 57h--58h (Bank4)..............................................................61
7.8.51
Real Time Hardware Status Register I -- Index 59h (Bank 4).......................................62
7.8.52
Real Time Hardware Status Register II -- Index 5Ah (Bank 4) .....................................63
7.8.53
Real Time Hardware Status Register III -- Index 5Bh (Bank 4) ....................................64
7.8.54
Reserved Register -- Index 5Ch (Bank 4).....................................................................64
7.8.55
Reserved Register -- Index 5Dh (Bank 4).....................................................................64
7.8.56
Value RAM 2
Index 50h - 5Ah (BANK 5) ..................................................................64
7.8.57
Winbond Test Register -- Index 50h (Bank 6) ..............................................................65
7.8.58
Reserved Register--Index00h (Bank 0) ........................................................................65
7.8.59
SYSFANOUT Output Value Control Register-- 01h (Bank 0) .......................................65
7.8.60
Reserved Register--Index02h (Bank 0) .......................................................................66
7.8.61
CPUFANOUT Output Value Control Register-- 03h (Bank 0).......................................66
7.8.62
FAN Configuration Register I -- Index 04h (Bank 0) .....................................................66
7.8.63
SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register -- Index 05h
(Bank 0) ........................................................................................................................67
7.8.64
CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -- Index 06h
(Bank 0) ........................................................................................................................68
7.8.65
Tolerance of Target Temperature or Target Speed Register -- Index 07h (Bank 0) ........68
7.8.66
SYSFANOUT Stop Value Register -- Index 08h (Bank 0) ............................................69
PDF 
ZIP