W83637HF

Publication Release Date: June 25, 2003

- I -

Revision 1.3

Revision History

PAGES DATES VERSION

MAIN

CONTENTS

1 N.

A. 03/25/2001 0.50

No Released.
For Winbond Internal use only.

2 08/09/2001

0.60

First

published.

02/18/2002

0.70

Update Chapter 10. (Hardware Monitor Device)

4 08/28/2002 1.0

New

update

09/27/2002

1.1

ADD Secure Digital Function Description

100~101

04/15/2003 1.2

ADD Block Digram
ADD Chapter 4.1 Plug and Play Configuration

7 130~137 06/25/2003

1.3 Add

Chapter 9 DC Specification

Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W83637HF

Publication Release Date: June 25, 2003

- II -

Revision 1.3

Tables of Contents-

GENERAL DESCRIPTION .......................................................................................................... 1

FEATURES .................................................................................................................................. 3

BLOCK DIAGRAM ....................................................................................................................... 7

PIN CONFIGURATION ................................................................................................................ 8

PIN DESCRIPTION...................................................................................................................... 9

5.1 LPC Interface ................................................................................................................. 10

5.2 FDC Interface................................................................................................................. 11

5.3 Multi-Mode Parallel Port................................................................................................. 12

5.4 Serial Port Interface ....................................................................................................... 17

5.5 KBC Interface................................................................................................................. 18

5.6 ACPI Interface................................................................................................................ 19

5.7 Hardware Monitor Interface ........................................................................................... 19

5.8 Game Port & MIDI Port.................................................................................................. 20

5.9 Card Reader Interface ................................................................................................... 21

5.9.1

Smart Card Interface ...................................................................................................21

5.9.2

MS/SD Card Interface .................................................................................................21

5.10

General Purpose I/O Port............................................................................... 22

5.10.1

General Purpose I/O Port 1 (Power source is Vcc) .....................................................22

5.10.2

General Purpose I/O Port 2 (Power source is Vcc) .....................................................22

5.10.3

General Purpose I/O Port 3 (Power source is VSB) ....................................................22

5.11 Power Pins..................................................................................................................... 23

HARDWARE MONITOR ............................................................................................................ 24

6.1 General Description ....................................................................................................... 24

6.2 Access Interface ............................................................................................................ 24

6.2.1

LPC interface...............................................................................................................24

6.3 Analog Inputs ................................................................................................................. 26

6.3.1

Monitor over 4.096V voltage........................................................................................27

6.3.2

CPUVCORE voltage detection method .......................................................................27

6.3.3

Temperature Measurement Machine...........................................................................28

6.4 FAN Speed Count and FAN Speed Control .................................................................. 29

6.4.1

Fan speed count..........................................................................................................29

6.4.2

Fan speed control........................................................................................................31

6.5 Smart Fan Control.......................................................................................................... 32

6.5.1

Thermal Cruise mode ..................................................................................................32

6.5.2

Fan Speed Cruise mode..............................................................................................33

6.5.3

Manual Control Mode ..................................................................................................34

W83637HF

Publication Release Date: June 25, 2003

- III -

Revision 1.3

6.6 SMI# Interrupt Mode ........................................................................................................ 34

6.6.1

Voltage SMI# mode .....................................................................................................34

6.6.2

Fan SMI# mode...........................................................................................................34

6.6.3

The W83637HF temperature sensor 1(SYSTIN) SMI# interrupt has two modes ........35

6.6.4

The W83637HF temperature sensor 2(CPUTIN) and sensor 3(VTIN) SMI# interrupt
has two modes and it is programmed at CR[4Ch] bit 6. ..............................................36

6.7 OVT# Interrupt Mode ................................................................................................... 37

6.8 Registers and RAM ...................................................................................................... 38

SMART CARD READER INTERFACE (SCR)........................................................................... 81

7.1 Features ....................................................................................................................... 81

7.2 Register File ................................................................................................................. 82

7.3 Smart Card ID Number (base address + 2 when BDLAB = 1, fixed at 70h)................ 94

7.4 Functional Description.................................................................................................. 94

7.5 Initialization .................................................................................................................. 94

7.6 Activation...................................................................................................................... 94

7.7 Answer-to-Reset .......................................................................................................... 95

7.8 Data Transfer ............................................................................................................... 95

7.9 Cold Reset and Warm Reset ....................................................................................... 95

7.10 Power States................................................................................................................ 96

7.11 Disabled State.............................................................................................................. 96

7.12 Active State.................................................................................................................. 96

7.13 Idle State...................................................................................................................... 96

7.14 Power Down State ....................................................................................................... 97

CONFIGURATION REGISTER.................................................................................................. 98

8.1 Plug and Play Configuration .......................................................................................... 98

8.1.1

Compatible PnP ..........................................................................................................98

8.1.2

Configuration Sequence ..............................................................................................99

8.2 The PNP ID of the W83637HF Card Reader Device (For BIOS Programming use)... 101

8.3 Chip (Global) Control Register..................................................................................... 101

8.3.1

Logical Device 0 (FDC) .............................................................................................106

8.3.2

Logical Device 1 (Parallel Port) .................................................................................110

8.3.3

Logical Device 2 (UART A)........................................................................................111

8.3.4

Logical Device 3 (UART B)........................................................................................111

8.3.5

Logical Device 5 (KBC) .............................................................................................113

8.3.6

Logical Device 6 (CIR)...............................................................................................114

8.3.7

Logical Device 7 (Game Port and MIDI Port and GPIO Port 1) .................................114

8.3.8

Logical Device 8 (GPIO Port 2 This power of the Port is VCC source)......................115

8.3.9

Logical Device 9 (GPIO Port 3 This power of the Port is standby source (VSB) ) .....117

8.4 Logical Device A (ACPI) .............................................................................................. 118

W83637HF

Publication Release Date: June 25, 2003

- IV -

Revision 1.3

8.5 Logical Device B (Hardware Monitor) .......................................................................... 126

8.6 Logical Device C (Smart Card interface) ..................................................................... 126

8.7 Logical Device D (MS/SD Card Interface) ................................................................... 127

ELECTRICAL CHARACTERISTICS........................................................................................ 129

9.1 Absolute Maximum Ratings ......................................................................................... 129

9.2 DC Characteristics ....................................................................................................... 129

10.

ORDERING INSTRUCTION .................................................................................................... 137

11.

HOW TO READ THE TOP MARKING..................................................................................... 137

12.

PACKAGE DIMENSIONS ........................................................................................................ 138

13.

APPENDIX A:........................................................................................................................... 139

W83637HF

Publication Release Date: June 25, 200302

- 1 -

Revision 1.3

1. GENERAL DESCRIPTION

The W83637HF is the new generation of Winbond's LPC I/O products. It is an evolving product from
Winbond's most popular LPC I/O chip W83627HF � which integrates the disk driver adapter, serial port
(UART), keyboard controller (KBC), SIR, CIR, game port, MIDI port, hardware monitor, ACPI, On Now
Wake-Up � plus additional new features: the Smart Card reader interface and Memory Stick

reader

interface.

The Smart Card application is gaining more and more attention; it provides a very high-grade security
and convenience in Internet transaction, banking, telephony, electronic payments, etc. The W83637HF
supports a smart card reader interface featuring Smart wake-up function. This smart card reader
interface fully meets the ISO7816 and PC/SC (Personal Computer/Smart Card Workgroup) standards.
W83637HF provides a minimum external components and lowest cost solution for smart card
applications.

The W83637HF implements a standard Memory Stick

reader interface. The Memory Stick

has

been a new mainstream media for storing and transferring data. It's ultra-small size and high storage
capacity make it can be used in very wide variety products, including the Audio, Video and PC.

The disk drive adapter functions of W83637HF include a floppy disk drive controller compatible with the
industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range
of functions integrated onto the W83637HF greatly reduces the number of components required for
interfacing with floppy disk drives. The W83637HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M
disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2 Mb/s.

The W83637HF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupts system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud
rates of 230k, 460k, or 921k bps, which support higher speed modems. In addition, the W83637HF
provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting NEC,
RC-5, extended RC-5, and RECS-80 protocols).

The W83637HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two
external floppy disk drives to be connected.

The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95/98

, which makes system resource allocation more efficient than ever.

The W83637HF provides functions that complies with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through PME# or PSOUT#
function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up.
The W83637HF also has auto power management to reduce the power consumption.

The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY

Phoenix MultiKey/42

, or customer code.

W83637HF

Publication Release Date: June 25, 2003

- 2 -

Revision 1.3

The W83637HF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.

The W83637HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide.
Moreover, W83637HF is made to meet the specification of PC2001's requirement in the power
management: ACPI 1.0/1.0b/2.0 and DPM (Device Power Management).

The W83637HF contains a game port and a MIDI port. The game port is designed to support 2
joysticks and can be applied to all standard PC game control devices. They are very important for an
entertainment or consumer computer.

The W83637HF supports hardware status monitoring for personal computers. It can be used to monitor
several critical hardware parameters of the system, including power supply voltages, fan speeds, and
temperatures, which are very important for a high-end computer system to work stably and properly.
Moreover, W83637HF support the Smart Fan control system, including the "Thermal Cruise

" and

"Speed Cruise

" functions. Smart Fan can make system more stable and user friendly.

W83637HF

Publication Release Date: June 25, 2003

- 3 -

Revision 1.3

2. FEATURES

General

� Meet LPC Spec. 1.01
� Support LDRQ#(LPC DMA), SERIRQ (serial IRQ)
� Compliant with Microsoft PC2000/PC2001 Hardware Design Guide
� Support DPM (Device Power Management), ACPI
� Programmable configuration settings
� Single 24 or 48 MHz clock input

FDC

� Compatible with IBM PC AT disk drive systems
� Variable write pre-compensation with track selectable capability
� Support vertical recording format
� DMA enable logic
� 16-byte data FIFOs
� Support floppy disk drives and tape drives
� Detects all overrun and underrun conditions
� Built-in address mark detection circuit to simplify the read electronics
� FDD anti-virus functions with software write protect and FDD write enable signal (write data

signal was forced to be inactive)

� Support up to four 3.5-inch or 5.25-inch floppy disk drives
� Completely compatible with industry standard 82077
� 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
� Support 3-mode FDD, and its Win95/98 driver

UART

� Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
� MIDI compatible
� Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
� Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
� Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (2

-1)

� Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz

W83637HF

Publication Release Date: June 25, 2003

- 4 -

Revision 1.3

Infrared

� Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
� Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
� Support Consumer IR

Parallel Port

� Compatible with IBM parallel port
� Support PS/2 compatible bi-directional parallel port
� Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification
� Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification
� Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A

and B through parallel port

� Enhanced printer port back-drive current protection

Keyboard Controller

� 8042 based with optional F/W from AMIKKEY

-2, Phoenix MultiKey/42

or customer code

with 2K bytes of programmable ROM, and 256 bytes of RAM

� Asynchronous Access to Two Data Registers and One status Register
� Software compatibility with the 8042
� Support PS/2 mouse
� Support port 92
� Support both interrupt and polling modes
� Fast Gate A20 and Hardware Keyboard Reset
� 8 Bit Timer/ Counter
� Support binary and BCD arithmetic
� 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency

Game Port

� Support two separate Joysticks
� Support every Joystick two axis (X, Y) and two button (A, B) controllers

MIDI Port

� The baud rate is 31.25 K baud
� 16-byte input FIFO
� 16-byte output FIFO

W83637HF

Publication Release Date: June 25, 2003

- 5 -

Revision 1.3

General Purpose I/O Ports

� 40 programmable general purpose I/O ports
� General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching

dog timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED
output, RSMRST# signal, PWROK signal, STR (suspend to DRAM) function, VID control
function,

OnNow Functions

� Keyboard Wake-Up by programmable keys
� Mouse Wake-Up by programmable buttons
� CIR Wake-Up by programmable keys
� SMART Card Wake-up by SCPSNT
� On Now Wake-Up from all of the ACPI sleeping states (S1-S5)

Smart Card Reader Interface

� PC/SC T=0, T=1 compliant
� ISO7816 protocol compliant
� With 16-byte send/receive FIFOs
� Programmable baud generator
� Standard drivers for Windows 98 ME

, Windows 2000

Memory Stick

Reader Interface

�

Meet SONY Memory Stick

Specification Version 1.03

Hardware Monitor Functions

� Smart fan control system, support "Thermal Cruise

" and "Speed Cruise

� 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or Pentium

II/III/4

thermal diode output

� 3 positive voltage inputs (typical for +5V, +3.3V, Vcore)
� 2 intrinsic voltage monitoring (typical for Vbat, +5VSB)
� 3 fan speed monitoring inputs
� 3 fan speed control
� Build in Case open detection circuit
� WATCHDOG comparison of all monitored values
� Programmable hysteresis and setting points for all monitored items
� Over temperature indicate output

W83637HF

Publication Release Date: June 25, 2003

- 8 -

Revision 1.3

4. PIN CONFIGURATION

1 2 3 4 5 6 7 8 9

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

PD3

PD2

PD1

PD0

SLIN#

INIT#

ERR#

AFD#

STB#

VCC

CTSA#

DSRA#

HEFRAS/RTSA#

PNPCSV/DTRA#

SINA

PENKBC/SOUTA

VSS

DCDA#

RIA#

MSRWLED/MSWPRO

GA20M

KBRST

VSB

KCLK

KDAT

SUSLED/GP35

DRV

L
E

D/I

I
N/S

I
#

I
N

EX#

SB#

/
F

I
N

SA#

/
F

EP#

AK0

RDA

EAD

CHG

CLK

I
N

VSS

I
C

L
K

LDRQ#

SER

I
R

3
V

L
R

ESET

MCL

MDA

PSO

PSI

RRX

3
4

MRS

#/GP

/
G

3
2

RCT

3
1

SX#

/
G

VBAT

L
#

ASEO

PEN

SB#

/
PEN

DDB

PEN

4
8

DCDB

VSS

/
G

2
6

/
G

2
5

/
G

2
4

/
G

2
2
/S

CC8

/MS

2
1
/
SC

4
/
M

L
K

+3.3

I
N

CORE

I
N

CPUTIN
SYSTIN

OVT#

SCPWCTL#

SCRST#

SCIO

SCPSNT

SCCLK

CPUD-

FANIN2
FANIN1

+5VIN

FANPWM2

FANPWM1

VSS

BEEP

MSI/GP20

MSO/IRQIN0

GPSA2/GP17

GPSB2/GP16

GPY1/GP15

GPY2/P16/GP14

GPX2/P15/GP13

GPX1/P14/GP12

GPSB1/P13/GP11
GPSA1/P12/GP10

1 2 3 4 5 6 7 8 9

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

PD3

PD2

PD1

PD0

SLIN#

INIT#

ERR#

AFD#

STB#

VCC

CTSA#

DSRA#

HEFRAS/RTSA#

PNPCSV/DTRA#

SINA

PENKBC/SOUTA

VSS

DCDA#

RIA#

MSRWLED/MSWPRO

GA20M

KBRST

VSB

KCLK

KDAT

SUSLED/GP35

DRV

L
E

D/I

I
N/S

I
#

I
N

EX#

SB#

/
F

I
N

SA#

/
F

EP#

AK0

RDA

EAD

CHG

CLK

I
N

VSS

I
C

L
K

LDRQ#

SER

I
R

3
V

L
R

ESET

MCL

MDA

PSO

PSI

RRX

3
4

MRS

#/GP

/
G

3
2

RCT

3
1

SX#

/
G

VBAT

L
#

ASEO

PEN

SB#

/
PEN

DDB

PEN

4
8

DCDB

VSS

/
G

2
6

/
G

2
5

/
G

2
4

/
G

2
2
/S

CC8

/MS

2
1
/
SC

4
/
M

L
K

+3.3

I
N

CORE

I
N

MCL

MDA

PSO

PSI

RRX

3
4

MRS

#/GP

/
G

3
2

RCT

3
1

SX#

/
G

VBAT

L
#

ASEO

PEN

SB#

/
PEN

DDB

PEN

4
8

DCDB

VSS

/
G

2
6

/
G

2
5

/
G

2
4

/
G

2
2
/S

CC8

/MS

2
1
/
SC

4
/
M

L
K

+3.3

I
N

CORE

I
N

CPUTIN
SYSTIN

OVT#

SCPWCTL#

SCRST#

SCIO

SCPSNT

SCCLK

CPUD-

FANIN2
FANIN1

+5VIN

FANPWM2

FANPWM1

VSS

BEEP

MSI/GP20

MSO/IRQIN0

GPSA2/GP17

GPSB2/GP16

GPY1/GP15

GPY2/P16/GP14

GPX2/P15/GP13

GPX1/P14/GP12

GPSB1/P13/GP11
GPSA1/P12/GP10

W83637HF

W83637HF

Publication Release Date: June 25, 2003

- 9 -

Revision 1.3

5. PIN DESCRIPTION

PIN DESCRIPTION

I/O12t

TTL level bi-directional pin with 12 mA source-sink capability.

I/O24t

TTL level bi-directional pin with 24 mA source-sink capability.

I/O12ts

TTL level Schmitt-trigger bi-directional pin with 12 mA source-sink capability.

I/O24ts

TTL level Schmitt-trigger bi-directional pin with 24 mA source-sink capability.

I/OD12t

TTL level bi-directional pin and open drain output with 12 mA sink capability.

I/OD24t

TTL level bi-directional pin and open drain output with 24 mA sink capability.

I/OD12ts

TTL level Schmitt-trigger bi-directional pin and open drain output with 12 mA sink
capability.

I/OD24ts

TTL level Schmitt-trigger bi-directional pin and open drain output with 24 mA sink
capability.

I/OD12cs

CMOS level Schmitt-trigger bi-directional pin and open drain output with 12 mA sink
capability.

I/OD16cs

CMOS level Schmitt-trigger bi-directional pin and open drain output with 16 mA sink
capability.

I/OD12csd

CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open
drain output with 12 mA sink capability.

I/OD12csu

CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open
drain output with 12 mA sink capability.

O4t

TTL level output pin with 4 mA source-sink capability.

O12t

TTL level output pin with 12 mA source-sink capability.

O16t

TTL level output pin with 16 mA source-sink capability.

O24t

TTL level output pin with 24 mA source-sink capability.

O24ts

TTL level Schmitt-trigger output pin with 24 mA source-sink capability.

OD12t

TTL level open drain output pin with 12 mA sink capability.

OD24t

TTL level open drain output pin with 24 mA sink capability.

O8c

CMOS level output pin with 8 mA source-sink capability.

INt

TTL level input pin.

INts

TTL level Schmitt-trigger input pin.

INtu

TTL level input pin with internal pull up resistor.

INc

CMOS level input pin.

INcd

CMOS level input pin with internal pull down resistor.

INcsu

CMOS level Schmitt-trigger input pin with internal pull up resistor.

W83637HF

Publication Release Date: June 25, 2003

- 11 -

Revision 1.3

5.2 FDC Interface

SYMBOL PIN I/O

FUNCTION

DRVDEN0 1 OD

24t

Drive Density Select bit 0.

INDEX#

3 IN

csu

This Schmitt-triggered input from the disk drive is active low
when the head is positioned over the beginning of a track marked
by an index hole. This input pin is pulled up internally by a 1 K

resistor. The resistor can be disabled by bit 7 of L0-CRF0
(FIPURDWN).

MOA#

4 OD

24t

Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.

DSB#

FANIN3

5 OD

24t

I/O

24ts

Drive Select B. When set to 0, this pin enables disk drive B.
This is an open drain output.
0V to +5V amplitude fan tachometer input

DSA#

6 OD

24t

Drive Select A. When set to 0, this pin enables disk drive A.
This is an open drain output.

MOB#

FANPWM3

7 OD

24t

Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
Fan speed control. Use the Pulse Width Modulation (PWM)
technical knowledge to control the Fan's RPM.

DIR#

8 OD

24t

Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion

STEP#

9 OD

24t

Step output pulses. This active low open drain output produces a
pulse to move the head to another track.

WD#

10 OD

24t

Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.

WE#

11 OD

24t

Write enable. An open drain output.

TRACK0#

13 IN

csu

Track 0. This Schmitt-triggered input from the disk drive is active
low when the head is positioned over the outermost track. This
input pin is pulled up internally by a 1 K

resistor. The resistor

can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

WP#

14 IN

csu

Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by a 1 K

resistor. The resistor can be

disabled by bit 7 of L0-CRF0 (FIPURDWN).

RDATA#

15 IN

csu

The read data input signal from the FDD. This input pin is pulled
up internally by a 1 K

resistor. The resistor can be disabled by

bit 7 of L0-CRF0 (FIPURDWN).

HEAD# 16

24t

Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1

W83637HF

Publication Release Date: June 25, 2003

- 12 -

Revision 1.3

FDC Interface, continued

SYMBOL PIN I/O

FUNCTION

DSKCHG# 17 IN

csu

Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by a 1 K

resistor. The resistor can be disabled by bit

7 of L0-CRF0 (FIPURDWN).

5.3 Multi-Mode Parallel Port

The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.

SYMBOL PIN I/O

FUNCTION

SLCT

WE2#

31 IN

12t

PRINTER MODE:
An active high input on this pin indicates that the printer is
selected. Refer to the description of the parallel port for definition
of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WE2#
This pin is for Extension FDD B; its function is the same as the
WE# pin of FDC.
EXTENSION 2FDD MODE: WE2#
This pin is for Extension FDD A and B; its function is the same as
the WE# pin of FDC.

PE

WD2#

32 IN

12t

PRINTER MODE:
An active high input on this pin indicates that the printer has
detected the end of the paper. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WD2#
This pin is for Extension FDD B; its function is the same as the
WD# pin of FDC.
EXTENSION 2FDD MODE: WD2#
This pin is for Extension FDD A and B; its function is the same as
the WD# pin of FDC.

BUSY

MOB2#

33 IN

12t

PRINTER MODE:
An active high input indicates that the printer is not ready to
receive data. Refer to the description of the parallel port for
definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: MOB2#
This pin is for Extension FDD B; its function is the same as the
MOB# pin of FDC.
EXTENSION 2FDD MODE: MOB2#
This pin is for Extension FDD A and B; its function is the same as
the MOB# pin of FDC.

W83637HF

Publication Release Date: June 25, 2003

- 13 -

Revision 1.3

Multi-Mode Parallel Port, continued

SYMBOL PIN I/O

FUNCTION

ACK#

DSB2#

34 IN

12t

PRINTER MODE: ACK#
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: DSB2#
This pin is for the Extension FDD B; its functions is the same as
the DSB# pin of FDC.
EXTENSION 2FDD MODE: DSB2#
This pin is for Extension FDD A and B; its function is the same as
the DSB# pin of FDC.

PD7

DSA2#

35 I/O

12ts

12t

PRINTER MODE: PD7
Parallel port data bus bit 7. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: DSA2#
This pin is for Extension FDD A; its function is the same as the
DSA# pin of FDC.

PD6

MOA2#

36 I/O

12ts

12t

PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION. 2FDD MODE: MOA2#
This pin is for Extension FDD A; its function is the same as the
MOA# pin of FDC.

PD5

37 I/O

12ts

PRINTER MODE: PD5
Parallel port data bus bit 5. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.

W83637HF

Publication Release Date: June 25, 2003

- 14 -

Revision 1.3

Multi-Mode Parallel Port, continued

SYMBOL PIN I/O

FUNCTION

PD4

DSKCHG2#

I/O

12ts

PRINTER MODE: PD4
Parallel port data bus bit 4. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSKCHG2#
This pin is for Extension FDD B; the function of this pin is the
same as the DSKCHG# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2#
This pin is for Extension FDD A and B; this function of this pin is
the same as the DSKCHG# pin of FDC. It is pulled high
internally.

PD3

RDATA2#

I/O

12ts

PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: RDATA2#
This pin is for Extension FDD B; its function is the same as the
RDATA# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: RDATA2#
This pin is for Extension FDD A and B; its function is the same as
the RDATA# pin of FDC. It is pulled high internally.

PD2

WP2#

I/O

12ts

PRINTER MODE: PD2
Parallel port data bus bit 2. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WP2#
This pin is for Extension FDD B; its function is the same as the
WP# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: WP2#
This pin is for Extension FDD A and B; its function is the same as
the WP# pin of FDC. It is pulled high internally.

PD1

TRAK02#

I/O

12ts

PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: TRAK02#
This pin is for Extension FDD B; its function is the same as the
TRAK0# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: TRAK02#
This pin is for Extension FDD A and B; its function is the same as
the TRAK0# pin of FDC. It is pulled high internally.

W83637HF

Publication Release Date: June 25, 2003

- 15 -

Revision 1.3

Multi-Mode Parallel Port, continued

SYMBOL PIN I/O

FUNCTION

PD0

INDEX2#

42 I/O

12ts

PRINTER MODE: PD0
Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: INDEX2#
This pin is for Extension FDD B; its function is the same as the
INDEX# pin of FDC. It is pulled high internally.

EXTENSION 2FDD MODE: INDEX2#
This pin is for Extension FDD A and B; its function is the same as
the INDEX# pin of FDC. It is pulled high internally.

SLIN#

STEP2#

43 OD

12t

PRINTER MODE: SLIN#
Output line for detection of printer selection. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: STEP2#
This pin is for Extension FDD B; its function is the same as the
STEP# pin of FDC.
EXTENSION 2FDD MODE: STEP2#
This pin is for Extension FDD A and B; its function is the same as
the STEP# pin of FDC.

INIT#

DIR2#

44 OD

12t

PRINTER MODE: INIT#
Output line for the printer initialization. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP
mode.
EXTENSION FDD MODE: DIR2#
This pin is for Extension FDD B; its function is the same as the
DIR# pin of FDC.
EXTENSION 2FDD MODE: DIR2#
This pin is for Extension FDD A and B; its function is the same as
the DIR# pin of FDC.

W83637HF

Publication Release Date: June 25, 2003

- 16 -

Revision 1.3

Multi-Mode Parallel Port, continued

SYMBOL PIN I/O

FUNCTION

ERR#

HEAD2#

45 IN

12t

PRINTER MODE: ERR#
An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: HEAD2#
This pin is for Extension FDD B; its function is the same as the
HEAD# pin of FDC.
EXTENSION 2FDD MODE: HEAD2#
This pin is for Extension FDD A and B; its function is the same as
the HEAD# pin of FDC.

AFD#

DRVDEN0

46 OD

12t

PRINTER MODE: AFD#
An active low output from this pin causes the printer to auto feed a
line after a line is printed. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DRVDEN0
This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.
EXTENSION 2FDD MODE: DRVDEN0
This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.

STB#

47 OD

12t

PRINTER MODE: STB#
An active low output is used to latch the parallel data into the
printer. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output
EXTENSION 2FDD MODE: This pin is a tri-state output.

W83637HF

Publication Release Date: June 25, 2003

- 17 -

Revision 1.3

5.4 Serial Port Interface

SYMBOL

PIN I/O

FUNCTION

CTSA#
CTSB#

49
78

Clear To Send. It is the modem control input.
The function of these pins can be tested by reading bit 4 of the
handshake status register.

DSRA#
DSRB#

50
79

Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.

RTSA#

HEFRAS

UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for CR26
bit 6 (HEFRAS). A 4.7 k

is recommended if intends to pull up.

(select 4EH as configuration I/O port

s address)

RTSB#

ENGMTO

80 O

UART B Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
Watch Dog Time-Out enable.

DTRA

PNPCVS

UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as PNPCVS, which provides the power-on value for CR24
bit 0 (PNPCVS). A 4.7 k is recommended if intends to pull up.
(clear the default value of FDC, UARTs, PRT, Game port and
MIDI port)

W83637HF

Publication Release Date: June 25, 2003

- 18 -

Revision 1.3

Serial Port Interface, continued

SYMBOL

PIN I/O

FUNCTION

DTRB#

81 O

UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.

SINA
SINB

53
82

Serial Input. It is used to receive serial data through the
communication link.

SOUTA

PENKBC

UART A Serial Output. It is used to transmit serial data out to the
communication link.
During power-on reset, this pin is pulled down internally and is
defined as PENKBC, which provides the power-on value for CR24
bit 2 (PENKBC). A 4.7 k

resistor is recommended if intends to

pull up. (enable KBC)

SOUTB

PEN48

UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as PEN48, which provides the
power-on value for CR24 bit 6 (EN48). A 4.7 k

resistor is

recommended if intends to pull up.

DCDA#
DCDB#

56
84

Data Carrier Detect. An active low signal indicates the modem or
data set has detected a data carrier.

RIA#
RIB#

57
85

Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.

5.5 KBC Interface

SYMBOL

PIN I/O

FUNCTION

GA20M 59

16t

Gate A20 output. This pin is high after system reset. (KBC P21)

KBRST 60

16t

Keyboard reset. This pin is high after system reset. (KBC P20)

KCLK 62

I/OD

16cs

Keyboard

Clock.

KDAT 63

I/OD

16cs

Keyboard

Data.

MCLK 65

I/OD

16cs

PS2 Mouse Clock.

MDAT 66

I/OD

16cs

PS2 Mouse Data.

W83637HF

Publication Release Date: June 25, 2003

- 19 -

Revision 1.3

5.6 ACPI Interface

SYMBOL

PIN I/O

FUNCTION

PSOUT# 67

12t

Panel Switch Output. This signal is used for Wake-Up
system from S5

c o l d

state. This pin is pulse output,

active low.

PSIN 68

c d

Panel Switch Input. This pin is high active with an
internal pull down resistor.

VBAT

pvdf_rc1000_vbat Battery voltage input.

5.7 Hardware Monitor Interface

SYMBOL

PIN I/O

FUNCTION

CASEOPEN#

76 IN

CASE OPEN. An active low input from an external device when
case is opened. This signal can be latched if pin VBAT is
connect to battery, even W83637HF is power off.

VIN2

AIN

0V to 4.096V FSR Analog Inputs.

VIN1

AIN

0V to 4.096V FSR Analog Inputs.

CPUVCORE 100 AIN 0V

4.096V FSR Analog Inputs.

VREF

101

AOUT

Reference Voltage for temperature maturation.

VTIN

102

AIN

Temperature sensor 3 inputs. It is used for temperature
maturation.

CPUTIN

103

AIN

Temperature sensor 2 inputs. It is used for CPU1 temperature
maturation.

SYSTIN 104

AIN

Temperature

sensor 1 input. It is used for system temperature

maturation.

OVT#

SMI#

105 OD

24t

Over temperature Shutdown Output. It indicated the temperature
is over temperature limit.
System Management Interrupt channel input.

FANIN2
FANIN1

112
113

I/O

12ts

0V to +5V amplitude fan tachometer input.

FANPWM1
FANPWM2

116
115

12t

(

12t)

Fan speed control. Use the Pulse Width Modulation (PWM)
technical knowledge to control the Fan's RPM.

BEEP 118

12t

Beep function for hardware monitor. This pin is low after system
reset.

W83637HF

Publication Release Date: June 25, 2003

- 20 -

Revision 1.3

5.8 Game Port & MIDI Port

SYMBOL

PIN I/O

FUNCTION

MSI
GP20

119 INtu

I/OD

12t

MIDI serial data input .(Default)
General purpose I/O port 2 bit 0.

MSO
IRQIN0

120 O

INc

MIDI serial data output. (Default)
Alternate Function input: Interrupt channel input.

GPSA2

GP17

121 Incsu

I/OD

12csu

Active-low, Joystick I switch input 2. This pin has an internal
pull-up resistor. (Default)
General purpose I/O port 1 bit 7.

GPSB2

GP16

122 Incsu

I/OD

12csu

Active-low, Joystick II switch input 2. This pin has an internal
pull-up resistor. (Default)
General purpose I/O port 1 bit 6.

GPY1

GP15

123 I/OD

12csd

I/OD

12cs

Joystick I timer pin. This pin connects to Y positioning variable
resistors for the Joystick. (Default)
General purpose I/O port 1 bit 5.

GPY2
GP14

124 I/OD

12csd

I/OD

12cs

Joystick II timer pin. This pin connects to Y positioning variable
resistors for the Joystick. (Default)
General purpose I/O port 1 bit 4.

P16

Alternate Function Output: KBC P16 I/O port.

GPX2
GP13

125 I/OD

12csd

I/OD

12cs

Joystick II timer pin. This pin connects to X positioning variable
resistors for the Joystick. (Default)
General purpose I/O port 1 bit 3.

P15

Alternate Function Output: KBC P15 I/O port.

GPX1
GP12

P14

126 I/OD

12csd

I/OD

12cs

Joystick I timer pin. This pin connects to X positioning variable
resistors for the Joystick. (Default)
General purpose I/O port 1 bit 2.
Alternate Function Output: KBC P14 I/O port.

GPSB1
GP11
P13

127 Incsu

I/OD

12csu

Active-low, Joystick II switch input 1. (Default)
General purpose I/O port 1 bit 1.
Alternate Function Output: KBC P13 I/O port.

GPSA1
GP10
P12

128 Incsu

I/OD

12csu

Active-low, Joystick I switch input 1. (Default)
General purpose I/O port 1 bit 0.
Alternate Function Output: KBC P12 I/O port.

W83637HF

Publication Release Date: June 25, 2003

- 21 -

Revision 1.3

5.9 Card Reader Interface

5.9.1 Smart Card Interface

SYMBOL

PIN I/O

FUNCTION

SCRWLED
SMI#
IRQIN
GP27

2 OD

24t

I/OD

24t

This pin outputs an oscillating clock signal of various frequencies
depending on traffic of Smart Card interface.
System Management Interrupt channel input.
General purpose I/O port 3 bit 6.

SCPWCTL# 106 O

24t

Smart Card interface power control signal.

SCRST# 107

24t

Smart Card interface reset output

SCIO 108

I/O

24t

Smart Card interface data I/O channel.

SCPSNT 109

Smart Card interface card present detection Schmitt-trigger
input.

SCCLK 110

24t

) Smart Card interface clock output

5.9.2 MS/SD Card Interface

SYMBOL

PIN I/O

FUNCTION

MSLED
SDLED
SDWPRO

58 O

24t

This pin outputs an oscillating clock signal of various frequencies
depending on traffic of secondary Memory Stick interface;
SD Card Write Protect Detect Pin.

MSPWCTL#
SDPWCTL#

75 O

24t

MS Card power control
SD Card power control

MS5
SD5
SCC8
GP22

91 I/O

24ts

I/OD

24ts

MS function
SD Data Line 2(DAT2)
Smart Card C8 PIN.
General purpose I/O port 2 bit 2.

MS3
SD3
SCC4
GP21

92 I/O

24ts

I/OD

24ts

MS function
SD Data Line 0(DAT0)
Smart Card C4 PIN
General purpose I/O port 2 bit 1

MSCLK
SDCLK

24ts

MS card CLK output
SD Card CLK output

MS4
SD4

94 I/O

24ts

function

SD Data Line 1(DAT 1)

MS2
SD2

95 I/O

24ts

function

SD Command Line(CMD)

MS1
SD1

96 I/O

24ts

function

SD Data Line 3(CD/DAT3)

W83637HF

Publication Release Date: June 25, 2003

- 22 -

Revision 1.3

5.10 General Purpose I/O Port

5.10.1 General Purpose I/O Port 1 (Power source is Vcc)
see 1.8 Game Port

5.10.2 General Purpose I/O Port 2 (Power source is Vcc)

SYMBOL

PIN I/O

FUNCTION

IRTX
GP26

87 O

12t

I/OD

12t

General purpose I/O port 2 bit 6.
Alternate Function Output: Infrared Transmitter Output. (Default)

IRRX
GP25

88 IN

I/OD

12ts

General purpose I/O port 2 bit 5.
Alternate Function Input: Infrared Receiver input. (Default)

WDTO
GP24

89 O

12t

I/OD

12t

General purpose I/O port 2 bit 4.
Watch dog timer output. (Default)

PLED
GP23

90 O

24t

I/OD

24t

General purpose I/O port 2 bit 3.
Power LED output, this signal is low after system reset. (Default)

GP22 91

I/OD

24t

General purpose I/O port 2 bit 2.

GP21 92

I/OD

24t

General purpose I/O port 2 bit 1.

5.10.3 General Purpose I/O Port 3 (Power source is VSB)

SYMBOL PIN I/O

FUNCTION

SUSLED

GP35

64 O

24t

I/OD

24t

Suspend LED output, it can program to flash when suspend
state. This function can work without VCC. (Default)
General purpose I/O port 3 bit 5

CIRRX

SDDET
GP34

69 In

I/OD

12ts

Consumer IR receiving input. This pin can Wake-Up system
from S5

(Default)

SD Card External Card Detect.
General purpose I/O port 3 bit 4

RSMRST#

GP33

70 OD

12t

I/OD

12t

This pin generates the RSMRST signal while the VSB come in.
(Default)
General purpose I/O port 3 bit 3

PWROK

GP32

71 OD

12t

I/OD

12t

This pin generates the PWROK signal while the VCC come in.
(Default)
General purpose I/O port 3 bit 2.

PWRCTL#

GP31

72 O

12t

I/OD

12t

This pin generates the PWRCTL# signal while the power failure.
(Default)
General purpose I/O port 3 bit 1.

SLP_SX#
GP30

73 IN

I/OD

12ts

Chip Set sleep state input.
General purpose I/O port 3 bit 0.

W83637HF

Publication Release Date: June 25, 2003

- 24 -

Revision 1.3

6. HARDWARE MONITOR

6.1 General Description

The W83637HF can be used to monitor several critical hardware parameters of the system, including
power supply voltages, fan speeds, and temperatures, which are very important for a high-end
computer system to work stable and properly. W83637HF provides LPC interface to access hardware.

An 8-bit analog-to-digital converter (ADC) was built inside W83637HF. The W83637HF can
simultaneously monitor 5 analog voltage inputs(addition monitor 3.3V & 5V VDD power), 3 fan
tachometer inputs, 3 remote temperature, one case-open detection signal. The remote temperature
sensing can be performed by thermistors, or 2N3904 NPN-type transistors, or directly from Intel

Deschutes CPU thermal diode output. Also the W83637HF provides: 3 PWM (pulse width modulation)
outputs for the fan speed control; beep tone output for warning; SMI#(through serial IRQ or OVT pin),
OVT# signals for system protection events.

Through the application software or BIOS, the users can read all the monitored parameters of system
from time to time. And a pop-up warning can be also activated when the monitored item was out of the
proper/preset range. The application software could be Winbond's Hardware Doctor

, or Intel

LDCM

(LanDesk Client Management), or other management application software. Also the users can set up
the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one
programmable and maskable interrupts. An optional beep tone could be used as warning signal when
the monitored parameters is out of the preset range.

6.2 Access Interface

The W83637HF provides two interface for microprocessor to read/write hardware monitor internal
registers.

6.2.1 LPC

interface

The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the
port 5h and 6h. The other higher bits of these ports is set by W83637HF itself. The general decoded
address is set to port 295h and port 296h. These two ports are described as following:
Port 295h: Index port.
Port 296h: Data port.
The register structure is showed as the Figure 6.1

W83637HF

Publication Release Date: June 25, 2003

- 25 -

Revision 1.3

Configuration Register

40h

Interrupt Status Registers

41h, 42h

SMI# Mask Registers

43h-44h

Fan Divisor Register I

47h

Serial Bus Address

48h

Monitor Value Registers

20h~3Fh

Device ID

49h

Temperature 2, 3 Serial

Bus Address

4Ah

4Bh

SMI#/OVT# Control Register

4Ch

Fan IN/OUT and BEEP/GPO#

Control Register

4Dh

Bank Select for 50h~5Fh

Registers.

4Eh

Winbond Vendor ID

4Fh

BANK 0

BEEP Control Registers

56h~57h

BANK 0

Chip ID Register

58h

BANK 0

Temperature Sensor Type

Configuration &

Fan Divisor Bit2 Registers

59h,5Dh

Data

Port 6h

Port 5h

Index

LPC

Bus

Smart Fan Configuration

Registers

00h-1Fh

BANK 4

Interrupt Status & SMI

Mask Registers

50h~51h

BANK 4

Beep Control Registers

53h

BANK 4

Temperature Offset

Registers

54h~56h

BANK 4

Read Time Status

Registers

59h~5Bh

BANK 5

59h~5Bh

Monitor Value Registers

Fan Divisor Register I

BANK 0

Winbond Test Registers

50h~55h

BANK 1

CPUTIN Temperature

Control/Staus Registers

50h~56h

BANK 2

VTIN Temperature

Control/Staus Registers

50h~56h

Figure 6.1: LPC interface access diagram

W83637HF

Publication Release Date: June 25, 2003

- 27 -

Revision 1.3

6.3.1 Monitor over 4.096V voltage
The +12V input voltage can be expressed as following equation.

VIN

�

The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input
voltage V1 is 12V. The node voltage of VIN1 can be subject to less than 4.096V for the maximun input
range of the 8-bit ADC.

The -12V input voltage can be expressed as following equation.

)

(

�

whereV

VIN

The value of R3 and R4 can be selected to 56K Ohms and 232K Ohms, respectively, when the input
voltage V2 is -12V. The node voltage of VIN2 can be subject to less than 4.096V for the maximun input
range of the 8-bit ADC.
The Pin 114 is connected to the power supply VCC with +5V. There are two functions in this pin with
5V. The first function is to supply internal analog power in the W83637HF and the second function is
that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The
W83637HF internal two serial resistors are 34K ohms and 51K ohms so that input voltage to ADC is
3V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as
follows.

VCC

�

where VCC is set to 5V.

The Pin 61 is connected to 5VSB voltage. W83637HF monitors this voltage and the internal two serial
resistors are 34K

and 51K so that input voltage to ADC is 3V which less than 4.096V of ADC

maximum input voltage.

6.3.2 CPUVCORE voltage detection method

W83637HF provides two detection methods for CPUVCORE(pin100).
(1). VRM8 method:
The LSB of this mode is 16mV. This means that the detected voltage equals to the reading of
this voltage register multiplies 16mV. The formula is as the following:

Detected Voltage =

016

ading

(2). VRM9 method:
The LSB of this mode is 4.88mV which is especially designed the low voltage CPU. The
formula is as the following:

Detected Voltage =

00488

ading

+ 0.7 V

W83637HF

Publication Release Date: June 25, 2003

- 28 -

Revision 1.3

6.3.3 Temperature Measurement Machine
The temperature data format is 8-bit two's-complement for sensor SYSTIN and 9-bit two's-complement
for sensor CPUTIN and VTIN. The 8-bit temperature data can be obtained by reading the CR[27h]. The
9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1/Bank2 CR[50h] and the
LSB from the Bank1/Bank2 CR[51h] bit 7. The format of the temperature data is show in Table 1.

Temperature

8-Bit Digital Output

9-Bit Digital Output

8-Bit Binary

8-Bit Hex

9-Bit Binary

9-Bit Hex

+125�C

0111,1101 7Dh 0,1111,1010 0FAh

+25�C

0001,1001 19h 0,0011,0010 032h

+1�C

0000,0001 01h 0,0000,0010 002h

+0.5�C

- -

0,0000,0001

001h

+0�C

0000,0000 00h 0,0000,0000 000h

-0.5�C

- -

1,1111,1111

1FFh

-1�C

1111,1111 FFh 1,1111,1110 1FFh

-25�C

1110,0111 E7h 1,1100,1110 1CEh

-55�C

1100,1001 C9h 1,1001,0010 192h

Table 1

6.3.3.1 Monitor temperature from thermistor:

The W83637HF can connect three thermistors to measure three different envirment temperature. The
specification of thermistor should be considered to (1)

value is 3435K, (2) resistor value is 10K ohms

at 25

�C. In the Figure 6.2, the themistor is connected by a serial resistor with 10K Ohms, then connect

to VREF (Pin 101).

6.3.3.2 Monitor temperature from Pentium II

/Pentium III

thermal diode or bipolar

transistor2N3904

The W83637HF can alternate the thermistor to Pentium II

/Pentium III

thermal diode interface or

transistor 2N3904 and the circuit connection is shown as Figure 6.3. The pin of Pentium II

/Pentium

III

D- is connected to pin 111(CPUD-) and the pin D+ is connected to temperature sensor pin in the

W83637HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current
and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor
2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the
2N3904 should be tied together to act as a thermal diode.

W83637HF

Publication Release Date: June 25, 2003

- 29 -

Revision 1.3

2N3904

R=30K,1%

C=3300pF

Bipolar Transistor
Temperature Sensor

Pentium II/III

CPU

D+

D-

Therminal

Diode

C=3300pF

R=30K,1%

VREF

SYSTIN

CPUTIN

W83637HF

CPUD-

Figure 6.3

6.4 FAN Speed Count and FAN Speed Control

6.4.1 Fan speed count
Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals
should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from
the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the
voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure
6.4.

Determine the fan counter according to:

Count

RPM Divisor

�

135 10

In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan
speed can be evaluated by the following equation.

RPM

Count

Divisor

�

1 35 10

The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are
three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed
table is an example for the relation of divisor, PRM, and count.

W83637HF

Publication Release Date: June 25, 2003

- 30 -

Revision 1.3

Divisor Nominal

PRM

Time per

Revolution

Counts

70% RPM

Time for 70%

1 8800

6.82

153

6160 9.84

2 (default)

4400 13.64

ms 153

3080 19.48

4 2200

27.27

153

1540 38.96

8 1100

54.54

153

770 77.92

16 550

109.08

153

385 155.84

32 275

218.16

153

192 311.68

64 137

436.32

153

96 623.36

128 68

872.64

153

48 1246.72

Table 2

FAN

Connector

FAN Out

+12V

GND

Pull-up resister

4.7K Ohms

+5V

+12V

Fan Input

Pin 111-112

W83637HF

FAN

Connector

FAN Out

+12V

GND

Pull-up resister

4.7K Ohms

+12V

Fan Input

Pin 111-112

W83637HF

14K~39K

10K

Fan with Tach Pull-Up to +12V, or Totem-Pole

Output and Register Attenuator

Fan with Tach Pull-Up to +5V

FAN

Connector

FAN Out

+12V

GND

Pull-up resister

> 1K

+12V

Fan Input

Pin 111-112

W83637HF

FAN

Connector

FAN Out

+12V

GND

Pull-up resister < 1K
or totem-pole output

+12V

Fan Input

Pin 111-112

W83637HF

> 1K

Fan with Tach Pull-Up to +12V, or Totem-Pole

Output and Zener Clamp

Fan with Tach Pull-Up to +12V and Zener Clamp

3.9V Zener

diode

Figure 6.4

W83637HF

Publication Release Date: June 25, 2003

- 32 -

Revision 1.3

6.5 Smart Fan Control

Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan
Speed Cruise mode.

6.5.1 Thermal Cruise mode
There are maximum 3 pairs of Temperature/FanPWM control at this mode: SYSTIN with FANPWM1,
CPUTIN with FANPWM2, VTIN with FANPWM3. At this mode, W83637HF provides the Smart Fan
system which can control the fan speed automatically depend on current temperature to keep it with in
a specific range. At first a wanted temperature and interval must be set (ex. 55

�C �3 �C) by BIOS, as

long as the real temperature remains below the setting value, the fan will be off. Once the temperature
exceeds the setting high limit temperature (58

�C), the fan will be turned on with a specific speed set by

BIOS (ex: 80% duty cycle) and automatically controlled its PWM duty cycle with the temperature
varying. Three conditions may occur:

(1) If the temperature still exceeds the high limit (ex: 58

�C), PWM duty cycle will increase slowly. If the

fan has been operating in its fully speed but the temperature still exceeds the high limit(ex: 58

�C), a

warning message will be issued to protect the system.

(2) If the temperature goes below the high limit (ex: 58

�C), but above the low limit (ex: 52�C), the fan

speed will be fixed at the current speed because the temperature is in the target area(ex: 52

�C ~

�C).

(3) If the temperature goes below the low limit (ex: 52

�C), PWM duty cycle will decrease slowly to 0

until the temperature exceeds the low limit.
Figure 6.6 and 6.7 give the illustration for Thermal Cruise Mode.

55`C

58`C

52`C

PWM

Duty

Cycle

100

Fan Start = 20%

Target Temperature

Tolerance

Figure 6.6

W83637HF

Publication Release Date: June 25, 2003

- 33 -

Revision 1.3

55`C

58`C

52`C

PWM
Duty
Cycle

100

Fan Start = 20%

Fan Stop = 10%

Fan Start = 20%

Target Temperature

Tolerance

Figure 6.7

One more protection is provided that duty cycle will not be decreased to 0 in the above (3) situation in
order to keep the fans running with a minimum speed. By setting CR[12h] bit3-5 to 1, FAN PWM duty
cycle will be decreased to the "Stop Duty Cycle" which are defined at CR[08h],CR[09h] and CR[17h].

6.5.2 Fan Speed Cruise mode
There are 3 pairs of FanSpeed/FanPWM control at this mode: FANIN1 with FANPWM1, FANIN2 with
FANPWM2, FANIN3 with FANPWM3.At this mode, W83637HF provides the Smart Fan system which
can control the fan speed automatically depend on current fan spesed to keep it with in a specific
range. A wanted fan speed count and interval must be set (ex. 160

�10) by BIOS. As long as the fan

speed count is the specific range, PWM duty will keep the current value. If current fan speed count is
higher than the high limit (ex. 160+10), PWM duty will be increased to keep the count less than the
high limit. Otherwise, if current fan speed is less than the low limit(ex. 160-10), PWM duty will be
decreased to keep the count higher than the low limit. See Figure 6.8 example.

160

170

150

PWM

Duty

Cycle

100

Count

Figure 6.8

W83637HF

Publication Release Date: June 25, 2003

- 34 -

Revision 1.3

6.5.3 Manual Control Mode
Smart Fan control system can be disabled and the fan speed control algorithem can be progrmmed by
BIOS or application software. The programming method is just as section 6.4.2.

6.6 SMI# Interrupt Mode

The SMI#/OVT# pin (pin105) is a multi-function pin. The function is selected at Configuration Register
CR[28h] bit 6.

6.6.1 Voltage SMI# mode
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below

low limit will causes an interrupt if the previous interrupt has been reset by reading all the
interrupt Status Register. (Figure 6.9)

6.6.2 Fan SMI# mode

SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding
and then going below the limit, will causes an interrupt if the previous interrupt has been reset by
reading all the interrupt Status Register. (Figure 6.10)

*Interrupt Reset when Interrupt Status Registers are read

SMI#

High limit

Low limit

SMI#

Fan Count limit

Figure 6.9

Figure 6.10

W83637HF

Publication Release Date: June 25, 2003

- 35 -

Revision 1.3

6.6.3 The W83637HF temperature sensor 1(SYSTIN) SMI# interrupt has two modes

(1) Comparator Interrupt Mode

Setting the T

HYST

(Temperature Hysteresis) limit to 127�C will set temperature sensor 1 SMI# to

the Comparator Interrupt Mode. Temperature exceeds T

(Over Temperature) Limit causes an

interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an
interrupt event has occurred by exceeding T

, then reset, if the temperature remains above the

, the interrupt will occur again when the next conversion has completed. If an interrupt event

has occurred by exceeding T

and not reset, the interrupts will not occur again. The interrupts will

continue to occur in this manner until the temperature goes below T

. (Figure 6.11)

Setting the T

HYST

lower than T

will set temperature sensor 1 SMI# to the Interrupt Mode. The following

are two kinds of interrupt modes, which are selected by Index 4Ch bit5:

(2) Two-Times Interrupt Mode

Temperature exceeding T

causes an interrupt and then temperature going below T

HYST

will also

cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status
Register. Once an interrupt event has occurred by exceeding T

, then reset, if the temperature

remains above the T

HYST

, the interrupt will not occur. (Figure 6.12)

(3) One-Time Interrupt Mode

Temperature exceeding T

causes an interrupt and then temperature going below T

HYST

will not

cause an interrupt. Once an interrupt event has occurred by exceeding T

, then going below

HYST,

an interrupt will not occur again until the temperature exceeding T

. (Figure .6.13)

HYST

*Interrupt Reset when Interrupt Status Registers are read

HYST

SMI#

127'C

Figure 6.11

Figure 6.12

W83637HF

Publication Release Date: June 25, 2003

- 36 -

Revision 1.3

*Interrupt Reset when Interrupt Status Registers are read

HYST

SMI#

Figure 6.13

6.6.4 The W83637HF temperature sensor 2(CPUTIN) and sensor 3(VTIN) SMI#

interrupt has two modes and it is programmed at CR[4Ch] bit 6.

(1) Comparator Interrupt Mode

Temperature exceeding T

causes an interrupt and this interrupt will be reset by reading all the

Interrupt Status Register. Once an interrupt event has occurred by exceeding T

, then reset, if the

temperature remains above the T

HYST

, the interrupt will occur again when the next conversion has

completed. If an interrupt event has occurred by exceeding T

and not reset, the interrupts will not

occur again. The interrupts will continue to occur in this manner until the temperature goes below
T

HYST

. (Figure 6.14)

(2) Two-Times Interrupt Mode

Temperature exceeding T

causes an interrupt and then temperature going below T

HYST

will also

cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status
Register. Once an interrupt event has occurred by exceeding T

, then reset, if the temperature

remains above the T

HYST

, the interrupt will not occur. (Figure 6.15)

HYST

*Interrupt Reset when Interrupt Status Registers are read

HYST

SMI#

Figure

6.14

Figure

6.15

W83637HF

Publication Release Date: June 25, 2003

- 37 -

Revision 1.3

6.7 OVT# Interrupt Mode

The SMI#/OVT# pin (pin105) is a multi-function pin. The function is selected at Configuration
Register CR[28h] bit 6. The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1
Index52h bit1and Bank2 Index52h bit1.

(1) Comparator Mode

Temperature exceeding T

causes the OVT# output activated until the temperature is less than

HYST

. (Figure 6.16)

(2) Interrupt Mode

Temperature exceeding T

causes the OVT# output activated indefinitely until reset by reading

temperature sensor registers. Temperature exceeding T

, then OVT# reset, and then temperature

going below T

HYST

will also cause the OVT# activated indefinitely until reset by reading

temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding T

, then

reset, if the temperature remains above T

HYST

, the OVT# will not be activated again.(Figure 6.16)

HYST

*Interrupt Reset when Temperature sensor registers are
read

OVT#

(Comparator Mode; default)

(Interrupt Mode)

Figure 6.16

W83637HF

Publication Release Date: June 25, 2003

- 45 -

Revision 1.3

Value RAM

Index 20h- 3Fh, continued

Address A6-A0

Description

36h Reserved
37h Reserved
38h Reserved
39h

SYSTIN temperature sensor High Limit

3Ah

SYSTIN temperature sensor Hysteresis Limit

3Bh

FAN1 Fan Count Limit
Note: It is the number of counts of the internal
clock for the Low Limit of the fan speed.

3Ch

FAN2 Fan Count Limit
Note: It is the number of counts of the internal
clock for the Low Limit of the fan speed.

3Dh

FAN3 Fan Count Limit
Note: It is the number of counts of the internal
clock for the Low Limit of the fan speed.

3E- 3Fh

Reserved

Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means
interrupts will never be generated except the case when voltages go below the low limits.

Device ID Register - Index 49h
Register Location:

49h

Power on Default Value

03h

Attribute:

bit<7:1> Read Only; bit<0> Read/Write

Size:

bits

7 6 5 4 3 2 1 0

DID<6:0>

VID[4]

Bit 7-1: Read Only - Device ID<6:0>
Bit 0 : CPU Vcore ID [4]. The VID value is written by BIOS if the VID value can be detected. After the

VID value is written, Software/AP can use this information to identify the Vcore voltage of the
CPU.

W83637HF

Publication Release Date: June 25, 2003

- 48 -

Revision 1.3

FAN IN/OUT and BEEP Control Register- Index 4Dh
Register Location:

4Dh

Power on Default Value

15h

Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

FANINC1

FANOPV1

FANINC2

FANOPV2

FANINC3

FANOPV3

Reserved

Bit 7~6: Reserved.
Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, pin5 (DSB#/FANIN3) generates a logic high

signal. Write 0, pin 5 generates a logic low signal. This bit is default 0. This bit is only valid when
pin5 is set to FANIN3 function.

Bit 4: FAN 3 Input Control. Set to 1, pin 5(DSB#/FANIN3) acts as FAN tachmeter input, which is default

value. Set to 0, this pin 5 acts as FAN control signal and the output value of FAN control is set
by this register bit 5. This bit is only valid when pin5 is set to FANIN3 function.

Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 115 always generate logic high

signal. Write 0, pin 115 always generates logic low signal. This bit default 0.

Bit 2: FAN 2 Input Control. Set to 1, pin 112 acts as FAN clock input, which is default value. Set to 0,

this pin 112 acts as FAN control signal and the output value of FAN control is set by this register
bit 3.

Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 116 always generate logic high

signal. Write 0, pin 116 always generates logic low signal. This bit default 0.

Bit 0: FAN 1 Input Control. Set to 1, pin 113 acts as FAN clock input, which is default value. Set to 0,

this pin 113 acts as FAN control signal and the output value of FAN control is set by this register
bit 1.

W83637HF

Publication Release Date: June 25, 2003

- 50 -

Revision 1.3

BEEP Control Register 1-- Index 56h (Bank 0)
Register Location:

56h

Power on Default Value

00h

Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

EN_VCORE_BP

EN_VIN1_BP

EN_+3.3VIN_BP

EN_+5VIN_BP

EN_SYSTIN_BP

EN_CPUTIN_BP

EN_FAN1_BP

EN_FAN2_BP

Bit 7: BEEP output control for FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Bit 6: BEEP output control for FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Bit 5: BEEP output control for temperature CPUTIN if the monitor value exceed the limit value. Write 1,

enable BEEP output. Write 0, disable BEEP output, which is default value.

Bit 4: BEEP output control for temperature SYSTIN if the monitor value exceed the limit value. Write 1,

enable BEEP output. Write 0, disable BEEP output, which is default value.

Bit 3: BEEP output control for +5VIN if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Bit 2: BEEP output control for +3.3VIN if the monitor value exceed the limit value. Write 1, enable

BEEP output. Write 0, disable BEEP output, which is default value.

Bit 1: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Bit 0: BEEP output control for CPUVCORE if the monitor value exceed the limit value. Write 1, enable

BEEP output. Write 0, disable BEEP output, which is default value.

W83637HF

Publication Release Date: June 25, 2003

- 51 -

Revision 1.3

BEEP Control Register 2-- Index 57h (Bank 0)
Register Location:

57h

Power on Default Value 80h
Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

EN_VIN2_BP

Reserved

EN_FAN3_BP

EN_CASO_BP

EN_VTIN_BP

Reserved

EN_GBP

Bit 7: Global BEEP Control. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP
output.
Bit 6: Reserved.
Bit 5: BEEP output control for temperature VTIN if the monitor value exceed the limit value. Write 1,

enable BEEP output. Write 0, disable BEEP output, which is default value.

Bit 4: BEEP output control for case open if the monitor value exceed the limit value. Write 1, enable

BEEP output. Write 0, disable BEEP output, which is default value.

Bit 3: BEEP output control for FAN 3 if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Bit 2-1: Reserved.
Bit 0: BEEP output control for VTIN2 if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Chip ID -- Index 58h (Bank 0)
Register Location:

58h

Power on Default Value

80h

Attribute: Read

Only

Size:

bits

7 6 5 4 3 2 1 0

CHIPID

Bit 7: Winbond Chip ID number. Read this register will return 80h.

W83637HF

Publication Release Date: June 25, 2003

- 53 -

Revision 1.3

VBAT Monitor Control Register -- Index 5Dh (Bank 0)
Register Location:

5Dh

Power on Default Value

00h

Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

EN_VBAT_MNT

DIODES1

DIODES2

DIODES3

Reserved

FANDIV1_B2

FANDIV2_B2

FANDIV3_B2

Bit 7: Fan3 divisor Bit2.
Bit 6: Fan2 divisor Bit2.
Bit 5: Fan1 divisor Bit2.
Bit 4: Reserved.
Bit 3: Sensor type selection of VTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor.
Bit 2: Sensor type selection of CPUTIN. Set to 1, select diode sensor. Set to 0, select thermistor

sensor.

Bit 1: Sensor type selection of SYSTIN. Set to 1, select diode sensor. Set to 0, select thermistor

sensor.

Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this

bit from 0 to 1, the monitored value will be updated to the VBAT reading value register after one
monitor cycle time.

Fan divisor table:

Bit 2

Bit 1

Bit 0

Fan Divisor Bit 2

Bit 1

Bit 0

Fan Divisor

0 0 0

1 0 0 16

0 0 1

1 0 1 32

0 1 0

1 1 0 64

0 1 1

1 1 1 128

W83637HF

Publication Release Date: June 25, 2003

- 61 -

Revision 1.3

Interrupt Status Register 3 -- Index 50h (BANK4)
Register Location:

50h

Power on Default Value

00h

Attribute: Read

Only

Size:

bits

7 6 5 4 3 2 1 0

5VSB

VBAT

TAR3

Reserved

Bit 7-3: Reserved.
Bit 2: A one indicates that the VTIN temperature has been over the target temperature for 3 minutes

with full fan speed at thermal cruise mode of SmartFan

Bit 1: A one indicates a High or Low limit of VBAT has been exceeded.
Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded.

SMI# Mask Register 3 -- Index 51h (BANK 4)
Register Location:

51h

Power on Default Value

00h

Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

5VSB

VBAT

Reserved

TAR3

Reserved

Bit 7-5: Reserved.

Bit 4: A one disables the corresponding interrupt status bit for

SMI

interrupt.

Bit 2-3: Reserved.

Bit 1: A one disables the corresponding interrupt status bit for

SMI

interrupt.

Bit 0: A one disables the corresponding interrupt status bit for

SMI

interrupt.

W83637HF

Publication Release Date: June 25, 2003

- 62 -

Revision 1.3

Reserved Register -- Index 52h (Bank 4)

BEEP Control Register 3-- Index 53h (Bank 4)
Register Location:

53h

Power on Default Value

00h

Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

EN_5VSB_BP

EN_VBAT_BP

Reserved

EN_USER_BP

Reserved

Bit 7-6: Reserved.
Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is

inactive. (Default 0)

Bit 4-2: Reserved.
Bit 1: BEEP output control for VBAT if the monitor value exceed the limit value. Write 1, enable BEEP

output. Write 0, disable BEEP output, which is default value.

Bit 0: BEEP output control for 5VSB if the monitor value exceed the limit value. Write 1, enable
BEEP output. Write 0, disable BEEP output, which is default value.

SYSTIN Temperature Sensor Offset Register -- Index 54h (Bank 4)
Register Location:

54h

Power on Default Value

00h

Attribute: Read/Write
Size:

bits

7 6 5 4 3 2 1 0

OFFSET<7:0>

Bit 7-0: SYSTIN temperature offset value. The value in this register will be added to the monitored

value so that the reading value will be the sum of the monitored value and the offset value.

W83637HF

Publication Release Date: June 25, 2003

- 64 -

Revision 1.3

Real Time Hardware Status Register I -- Index 59h (Bank 4)
Register Location:

59h

Power on Default Value

00h

Attribute: Read

Only

Size:

bits

7 6 5 4 3 2 1 0

VCORE_STS

VIN1_STS

+3.3VIN_STS

+5VIN_STS

SYSTIN_STS

CPUTIN_STS

FAN1_STS

FAN2_STS

Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter

is in the limit range.

Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter

is in the limit range.

Bit 5: CPUTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit

value. Set 0, the temperature is in under the hysteresis value.

Bit 4: SYSTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit

value. Set 0, the temperature is in under the hysteresis value.

Bit 3: +5VIN Voltage Status. Set 1, the voltage of +5VIN is over the limit value. Set 0, the voltage of

+5VIN is in the limit range.

Bit 2: +3.3VIN Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of

+3.3VIN is in the limit range.

Bit 1: VIN1 Voltage Status. Set 1, the voltage of VIN1 is over the limit value. Set 0, the voltage of VIN1

is in the limit range.

Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE is over the limit value. Set 0, the voltage of

VCORE is in the limit range.

W83637HF

Publication Release Date: June 25, 2003

- 65 -

Revision 1.3

Real Time Hardware Status Register II -- Index 5Ah (Bank 4)
Register Location:

5Ah

Power on Default Value

00h

Attribute: Read

Only

Size:

bits

7 6 5 4 3 2 1 0

VIN2_STS

Reserved

FAN3_STS

CASE_STS

VTIN_STS

TAR1_STS

TAR2_STS

Bit 7: Smart Fan 2 warning status. Set 1, the CPUTIN temperature has been over the target

temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan

. Set 0, the

temperature does not reach the warning range yet.

Bit 6: Smart Fan 1 warning status. Set 1, the SYSTIN temperature has been over the target

temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan

. Set 0, the

temperature does not reach the warning range yet.

Bit 5: VTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit

value. Set 0, the temperature is in under the hysteresis value.

Bit 4: Case Open Status. Set 1, the case open is detected and latched. Set 0, the case is not latched

open.

Bit 3: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter

is in the limit range.

Bit 2-1: Reserved.

Bit 0: Vin2 Voltage Status. Set 1, the voltage of VIN2 is over the limit value. Set 0, the voltage of VIN2

is in the limit range.

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Revision 1.3

12h

Power on Default Value

00h

Attribute: Read/Write

Size:

bits

7 6 5 4 3 2 1 0

FAN3_OB
FAN3_Mode

FAN3_Mode

FAN3_MIN_Duty
FAN2_MIN_Duty

FAN1_MIN_Duty
Reserved

Reserved

Bit7-6: Reserved
Bit 5: Set 1, FANPWM1 duty cycle will decrease to and keep the value set in Index 08h when
temperature goes below target range. This is to maintain the fan speed in a minimum value.

Set 0, FANPWM1 duty cycle will decrease to 0 when temperature goes below target range.
Bit 4: Set 1, FANPWM2 duty cycle will decrease to and keep the value set in Index 09h when

temperature goes below target range. This is to maintain the fan speed in a minimum value.

Set 0, FANPWM2 duty cycle will decrease to 0 when temperature goes below target range.
Bit 3: Set 1, FANPWM3 duty cycle will decrease to and keep the value set in Index 17h when

temperature goes below target range. This is to maintain the fan speed in a minimum value.

Set 0, FANPWM3 duty cycle will decrease to 0 when temperature goes below target range.

Bit2-1: FANPWM3 mode control.

Set 00, FANPWM3 is as Manual Mode. (Default).
Set 01, FANPWM3 is as Thermal Cruise Mode.
Set 10, FANPWM3 is as Fan Speed Cruise Mode.
Set 11, reserved and no function.

Bit 0: FANPWM3 output mode selection. Set to 0, FANPWM3 pin is as output pin so that it can drive
a logical high or low signal. Set to 1, FANPWM3 pin is as open-drain pin which can only drive a logical
low signal.

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Revision 1.3

FANPWM3 Stop Time Register -- Index 17h (Bank 0)
Register Location:

17h

Power on Default Value

3Ch

Attribute: Read/Write

Size:

bits

7 6 5 4 3 2 1 0

FANPWM3 Stop Time

When at Thermal Cruise mode, this register determines the time of which FANPWM3 duty is from stop
duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default time is 6 seconds.

VRM & OVT Configuration Register -- Index 18h (Bank 0)
Register Location:

18h

Power on Default Value

43h

Attribute: Read/Write

Size:

bits

7 6 5 4 3 2 1 0

VCORE_AD_SEL
Reserved

Reserved

Reserved
OVT1_Mode

Reserved
DIS_OVT1

Reserved

Bit 7: Reserved.
Bit 6: Set to 1, disable temperature sensor SYSTIN over-temperature (OVT) output. Set to 0, enable

the SYSTIN OVT output.

Bit 5: Reserved.
Bit 4: SYSTIN OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1,

interrupt mode will be selected.

Bit 3-1: Reserved.
Bit 0: CPUVCORE pin voltage detection method selection. Set to 1, VRM9 formula is selected. Set to

0, VRM8 formula is selected. This bit default value is 1.

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Revision 1.3

Reserved -- Index 19h (Bank 0)

User Defined Register -- Index 1A- 1Bh (Bank 0)
Register Location:

1A-1Bh

Power on Default Value

FFh

Attribute: Read/Write

Size:

bits

7 6 5 4 3 2 1 0

User-defined
User-defined

User-defined

User-defined
User-defined

User-defined

Bit 7-0: User can write any value into these bits and read.

Reserved -- Index 1Ch-1Fh (Bank 0)

7. SMART CARD READER INTERFACE (SCR)

7.1 Features

Winbond's implementation of Smart Card Reader interface is based on ISO/IEC 7816-3 standard and
fully compliant with PC/SC Specifications 1.0. Except for pins specified in ISO/IEC 7816-3,
W83637HF's SCI also includes SCPSNT (Smart Card Present) monitoring status of card
insertion/extraction, SCLED (Smart Card traffic LED display) which is active high when host is
accessing information to/from card, and two general-purpose I/O pins SCC4 and SCC8 (only available
in W83637HF) for users to design application-specific functions.

Register file (control and status registers) of Winbond's Smart Card interface is designed in an UART-
like structure so that users with previous UART experience should have no trouble to implement
Winbond's SCI applications.

Power consumption is minimized by sophisticated device's operation scheme.

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Revision 1.3

7.2 Register File

Complete register file table

Bit Number

Register

file Abbr.

7 6 5 4 3 2 1 0

Base + 0

BDLAB = 0

Receiver Buffer

only)

RBR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Base + 0

BDLAB = 0

Transmitter Buffer

only)

TBR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Interrupt Enable

SCC8 SCC4

SCC8_IO

(note)

SCC4_IO

(note)

ESCPTI

(note)

ESCSRI

(note)

ETBREI

(note)

ERDRI

(note)

Base + 1

BDLAB = 0

default

IER

x x 0 0 0 0 0 0

Base + 2

BDLAB = 0

Interrupt Status

only)

ISR

FIFO

enabled

FIFO

enabled

SCPSNT

SCPTI

(note)

INTS2

(note)

INTS1

(note)

INTS0

(note)

Interrupt

pending

Smart Card FIFO

control Register

(Write only)

RxTL1

(note)

RxTL0

(note)

Reserved Reserved Reserved

TxFRST

(note)

RxFRST

(note)

Enable

FIFO

Base + 2

BDLAB = 0

default

SCFR

0 0 x x x 0 0 0

Smart Card

Control

BDLAB

(note)

Reserved Reserved

EPE

(note)

PBE

(note)

Reserved Reserved SC_SEL

Base + 3

default

SCCR

0 x x 0 0 x x 0

Clock Base

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Base + 4

default

CBR

0 0 0 0 1 1 0 0

Base + 5

Smart Card

Status

only)

SCSR

RxFEI

(note)

TSRE
(note)

TBRE
(note)

SBD

(note)

NSER

(note)

PBER

(note)

OER

(note)

RDR

(note)

Guard Time

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Base + 6

default

GTR

0 0 0 0 0 0 0 1

Extended Control

Cold

reset

Reserved

SCKFS1

(note)

SCKFS0

(note)

CLKSTPL

(note)

CLKSTP

(note)

SCIODIR

(note)

Warm

reset

Base + 7

default

ECR

0 x 0 1 0 0 1 0

Baud rate divisor

Latch Lower byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Base + 0

BDLAB = 1

default

BLL

0 0 0 1 1 1 1 1

Baud rate divisor

Latch Higher byte

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Base + 1

BDLAB = 1

default

BLH

0 0 0 0 0 0 0 0

Base + 2

BDLAB = 1

Smart Card ID
number (Read

only)

0 1 1 1 0 0 0 0

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Revision 1.3

Note:

Abbreviation explanation (in alphabetical order) �

BDLAB � Baud rate divisor latch access bit.

CLKSTP � Stop Smart Card interface's clock SCCLK.

CLKSTPL � Set SCCLK level when CLKSTP is "1".

EPE � Even parity enable.

ERDRI � Enable RBR (Receiver Buffer Register) data ready interrupt.

ESCPTI - Enable SCPSNT interrupt.

ESCSRI - Enable interrupts of SCSR (read only Smart Card Status Register at base address + 5)
events.
ETBREI � Enable TBR (write only Transmitter Buffer Register at base address + 0) empty interrupt.
INTS2 ~ INTS0 � Interrupt status bits. Refer to description of ISR (read only Interrupt Status Register
at base address + 2) for details.
NSER � No stop bit error.
OER � Overrun error.

PBE � Parity bit enable.

PBER � Parity bit error.

RDR � Receiver data ready status.

RxFEI � Receiver FIFO error indication.

RxFRST � Receiver FIFO reset.

RxTL1 ~ RxTL0 � Receiver threshold level setting bits. Refer to description of SCFR (write only

Smart Card FIFO control register at base address + 2) for details.

SBD � Silent byte detected.

SCIODIR � SCIO direction bit (0/1 mean output/input respectively).

SCKFS1 ~ SCKFS0 � Smart Card interface clock frequency selection bits. Refer to description of

ECR (Extended Control Register at base address + 7) for details.

SCPTI � SCPSNT toggle interrupt status.

SC_SEL � Smart Card socket selection.

TBRE � TBR (write only Transmitter Buffer Register at base address + 0) empty status.

TSRE � TSR (Transmitter shift register) empty status.

TxFRST � Transmitter FIFO reset.

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Revision 1.3

Interrupt Enable Register (IER at base address + 1 when BDLAB = 0)

This register includes four control bits to enable interrupt events. The other four bits are allocated for
control of general-purpose I/O pins which are usually connected to C4 and C8 pads of a smart card for
application specific function.

ERDRI
ETBREI
ESCSRI
ESCPTI
SCC4_IO
SCC8_IO
SCC4
SCC8

7 6 5 4 3 2 1 0

Bit 7: SCC8 means Smart Card C8 pad. When SCC8_IO (bit 5) is set to "0" for output mode, this bit

controls the voltage level of SCC8 pin which is high when SCC8 is set to "1" and low for setting
of "0". Its value reflects what could be observed on SCC8 pin when SCC8_IO is set to "1" for
input mode with the same convention as in output mode.

Bit 6: SCC4 means Smart Card C4 pad. When SCC4_IO (bit 4) is set to "0" for output mode, this bit

controls the voltage level of SCC4 pin which is high when SCC4 is set to "1" and low for setting
of "0". Its value reflects what is observed on SCC4 pin when SCC4_IO is set to "1" for input
mode with the same convention as in output mode.

Bit 5: SCC8_IO means input/output direction control for SCC8 pin.

= 0

SCC8 is in output mode.

= 1

SCC8 is in input mode.

Bit 4: SCC4_IO means input/output direction control for SCC4 pin.

= 0

SCC4 is in output mode.

= 1

SCC4 is in input mode.

Bit 3: ESCPTI means SCPSNT toggle interrupt enable bit. A rising/falling edge of SCPSNT signal

triggers an interrupt if this bit is set to "1".

= 0

SCPSNT toggle interrupt is disabled.

= 1

SCPSNT toggle interrupt is enabled.

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Revision 1.3

Bit 2: ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error,

no stop bit error, parity bit error or overrun error. Any SCSR-related event as described above
will trigger an interrupt if this bit is set to "1".

= 0

SCSR-related event interrupt is disabled.

= 1

SCSR-related event interrupt is enabled.

Bit 1: ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An

interrupt is issued when TBR is empty and this bit is set to "1". It is used in output mode
(SDIODIR = 0) to request host's attention to transfer data byte to card.

= 0

TBR empty interrupt is disabled.

= 1

TBR empty interrupt is enabled.

Bit 0: ERDRI means interrupt enable bit for receiver data ready status. The active FIFO threshold level

for this kind of interrupt when FIFO is enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of
SCFR at base address + 2. Refer to description of SCFR for details). An interrupt is issued if a
data byte is ready for host to read when FIFO is disabled or incoming data from card reaches
active FIFO threshold level when FIFO is enabled.

= 0

Receiver data ready interrupt is disabled.

= 1

Receiver data ready interrupt is enabled.

Interrupt Status Register (ISR at base address + 2 when BDLAB = 0, read only)

This register contains mainly interrupt status including transmission-related interrupts and SCPSNT
toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART
implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR
(write only Smart Card FIFO Register at base address + 2 when BDLAB = 0) and SCPSNT line status.

Interrupt pending
INTS0
INTS1
INTS2
SCPTI
SCPSNT
FIFO enabled
FIFO enabled

7 6 5 4 3 2 1 0

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Revision 1.3

Bit 7, 6: FIFO enabled status bits reflect what is set in bit 0 of SCFR (write only Smart Card FIFO

Bit 5: SCPSNT line status. User may poll this bit to see SCPSNT pin's voltage level.

Bit 4: SCPTI means SCPSNT toggle interrupt status. A rising/falling edge of SCPSNT signal triggers

an interrupt and set this status bit if ESCPTI (IER bit 3) is set to "1" to enable SCPSNT toggle
interrupt.

= 0

No SCPSNT toggle interrupt.

= 1

SCPSNT toggle interrupt occurs.

Bit 3 ~ 1: INTS2 ~ INTS0 mean interrupt status bit 2 ~ 0. The combination indicates which kind of

transmission-related interrupt has occurred. Refer to the following table for details.

ISR bit

Interrupt set and function

3 2 1 0 Priority

Interrupt

type

Interrupt source

Clear interrupt condition

0 0 0 1

interrupt

pending

0 1 1 0

first

Data receiving status

1. OER = 1
2. PBER = 1
3. NSER = 1
4. SBD = 1

Read SCSR

0 1 0 0 second RBR

data

ready

1. RBR data ready
2. FIFO interrupt active

level reached

1. Read RBR
2. Read RBR until FIFO

is under active level

1 1 0 0 second FIFO data time out

Data present in Rx
FIFO for 4-character
period of time since last
access of Rx FIFO.

Read RBR

0 0 1 0

third TBR empty

TBR empty

1. Write data to TBR
2. Read ISR (if priority is

third)

Bit 0: Interrupt pending status bit. This bit is a logical "1" if there is no interrupt pending. If one of the

interrupt sources occurs, this bit will be set to a logical "0".

= 0

Interrupt pending.

= 1

No interrupt occurs.

W83637HF

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Revision 1.3

Smart Card FIFO control Register (SCFR at base address + 2 when BDLAB = 0, write only)

This register controls FIFO function of Smart Card interface.

Enable FIFO
RxFRST
TxFRST
Reserved
Reserved
Reserved
RxTL0
RxTL1

7 6 5 4 3 2 1 0

Bit 7, 6: RxTL1 and RxTL0 mean receiver FIFO active threshold level control bits. These two bits are

used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active
level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an
interrupt is activated to notify host to read data from FIFO. Default to be 00b.

RxTL1

RxTL0

Rx FIFO Interrupt Active Level (Bytes)

0 0

0 1

1 0

1 1

Bit 5 ~ 3: Reserved.

Bit 2: TxFRST means transmitter FIFO reset control bit. Setting this bit to a logical "1" resets the

transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1".
Default is "0".

Bit 1: RxFRST means receiver FIFO reset control bit. Setting this bit to a logical "1" resets the

receiver FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1".
Default is "0".

Bit 0: This bit enables FIFO of Smart Card interface. It should be set to a logical "1" before other bits

of SCFR are programmed. Default is "0".

W83637HF

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Revision 1.3

Smart Card Control Register (SCCR at base address + 3)
In contrast to its UART counterpart, Smart Card

Control Register only controls parity bit setting

because data length is fixed at 8-bit long for Smart Card interface protocol.

Reserved
Reserved
Reserved
PBE
EPE
Reserved
Reserved
BDLAB

7 6 5 4 3 2 1 0

Bit 7: BDLAB means baud rate divisor latch access bit. When this bit is set to a logical "1", users may

access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of
baudrate generator during a read/write operation. A special Smart Card ID can also be read at
base address + 2 when BDLAB is "1". When this bit is set to "0", accesses to base address +
0, 1 or 2 refer to RBR/TBR, IER or ISR/SCFR respectively.

Bit 6 ~ 5: Reserved.

Bit 4: EPE means even parity enable. This bit is only available when bit 3 of SCCR is programmed to

"1". It prescribes number of logical 1s in a data word including parity bit. When this bit is set
to "1", even parity is required for transmission and reception. Odd parity is demanded when
this bit is set to "0".

Bit 3: PBE means parity bit enable. When this bit is set, a parity bit is inserted between last data bit

and stop bit for transmission integrity check.

Bit 2 ~ 0: Reserved.

W83637HF

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Revision 1.3

Clock Base Register (CBR at base address + 4, default 0Ch)
This register combining with BLH and BLL (baud rate latches) determine internal sampling clock
frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh which mean
SCCLK clock frequency is 372 (12 x 31) times of internal sampling clock frequency. The default
values of CBR, BLH and BLL are corresponding to default values of transmission factors F and D
specified in ISO/IEC 7816-3. The value of 0Ch of CBR means there're 12 sampling clock pulses to
detect a 1-etu (elementary time unit) data bit on SCIO signal. It is recommended that user sets CBR
to be around 16 to maintain better data integrity and transmission stability.

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

7 6 5 4 3 2 1 0

Bit 7 ~ 0: Clock base value. It specifies number of internal sampling clock pulses for a data bit.

Default to be 0Ch.

Smart Card Status Register (SCSR at base address + 5)
This 8-bit register provides information about status of data transfer during communication.

RDR
OER
PBER
NSER
SBD
TBRE
TSRE
RxFEI

7 6 5 4 3 2 1 0

Bit 7: RxFEI means receiver FIFO error indication. This bit is set to "1" when there is at least one

parity bit error, no stop bit error or silent byte detected error in receiver FIFO. It is cleared by
reading from SCSR if there is no remaining error left in receiver FIFO.

Bit 6: TSRE means transmitter shift register empty. This bit is set to "1" when transmitter shift register

is empty.

Bit 5: TBRE means transmitter buffer register empty. In non-FIFO mode, this bit will be set to a logical

1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt
is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1"
when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or
FIFO.

W83637HF

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Revision 1.3

Bit 4: SBD means silent byte detected. This bit is set to "1" to indicate that received data byte are

kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In
FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads
SCSR, it clears this bit to "0".

Bit 3: NSER means no stop bit error. This bit is set to "1" to indicate that received data has no stop

bit. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host
reads SCSR, it clears this bit to "0".

Bit 2: PBER means parity bit error. This bit is set to "1" to indicate that parity bit of received data is

wrong. In FIFO mode, it indicates the same condition for the data on top of the FIFO. When
host reads SCSR, it clears this bit to "0".

Bit 1: OER means overrun error. This bit is set to "1" to indicate previously received data is

overwritten by the next received data before it is read by host. In FIFO mode, it indicates the
same condition instead of FIFO full. When host reads SCSR, it clears this bit to "0".

Bit 0: RDR means receiver data ready. This bit is set to "1" to indicate received data is ready to be

read by host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is cleared to "0".

Guard Time Register (GTR at base address + 6, default 01h)

This register specifies number of stop bits appended in the end of data byte.

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

7 6 5 4 3 2 1 0

Bit 7 ~ 0: Guard time values. Default to be 01h.

W83637HF

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Revision 1.3

Extended Control Register (ECR at base address + 7, default 12h)
This register contains reset control bits, clock frequency selection bits, clock stop control bits and SCIO
direction control bit.

Warm reset
SCIODIR
CLKSTP
CLKSTPL
SCKFS0
SCKFS1
Reserved
Cold reset

7 6 5 4 3 2 1 0

Bit 7: Cold reset. Setting "1" to this bit turns off power to Smart Card interface by pulling up SCPWR#.

SCCLK is stopped, SCRST# kept low, SCIO in input mode and SCLED is inactive. ECR's
SCIODIR, SCKFS1 and SCKFS0 control bits and control bits in CBR, GTR, BLH and BLL are
cleared to default values. User must write a "0" to this bit to recover to normal state.

Bit 6: Reserved.

Bit 5, 4: SCKFS1 and SCKFS0 means SCCLK frequency selection bit 1 and 0. They selects working

clock frequency as following table. Default values are 01h.

SCKFS1, SCKFS0

SCCLK frequency

00 1.5

MHz

01 3.0

MHz

10 6.0

MHz

11 12

MHz

Bit 3: CLKSTP means clock stop control bit. Setting "1" to this bit stops SCCLK at a voltage level

specified by CLKSTPL (bit 2 of ECR).

Bit 2: CLKSTPL means clock stop voltage level.

= 0

SCCLK stops at low if CLKSTP is also set to "1".

= 1

SCCLK stops at high if CLKSTP is also set to "1".

Bit 1: SDIODIR means SDIO direction.

= 0

SDIO is in output mode.

= 1

SDIO is in input mode.

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Revision 1.3

Bit 0: Warm reset. Setting "1" to this bit pulls down SCRST#. SCCLK is stopped, SCIO in input

mode and SCLED is inactive. ECR's SCIODIR, SCKFS1 and SCKFS0 control bits and control
bits in CBR, GTR, BLH and BLL are cleared to default values. User must write a "0" to this bit
to recover to normal state. This bit is similar to cold reset except SCPWR# stays active low.

Baud rate divisor Latch Lower byte (BLL at base address + 0 when BDLAB = 1, default 1Fh)
This register combining with BLH and CBR determine internal sampling clock frequency. Refer to
section 2.2.8 for example.

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

7 6 5 4 3 2 1 0

Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh.

Baud rate divisor Latch Higher byte (BLH at base address + 1 when BDLAB = 1, default 00h)

This register combining with BLL and CBR determine internal sampling clock frequency. Refer to
section 2.2.8 for example.

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

7 6 5 4 3 2 1 0

Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h.

W83637HF

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Revision 1.3

7.3 Smart Card ID Number (base address + 2 when BDLAB = 1, fixed at 70h)

This register contains a specific value of 70h for driver to identify Smart Card interface.

7.4 Functional Description

The following description uses abbreviations to refer to control/status registers and their contents of
Smart Card interface as seen in section 2.2. Also, PnP resources of Smart Card interface are
assumed to have been programmed and allocated appropriately by system BIOS.

7.5 Initialization

User needs to program control registers so that ATR (Answer To Reset) data streams can be properly
decoded after card insertion. Initialization settings include the following steps where sequential order
is irrelevant.

1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default

transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3.

2. GTR is programmed with 01h for one stop bit.
3. Set SCFR bit 1 to "1" to enable FIFO.
4. PBE needs to be "1" for parity bit enable but EPE is optional.
5. Set SDIODIR to "1" to put SDIO in reception mode.
6. Set SCKFS1 and SCKFS0 to "01" to select 3 MHz for SCCLK.

Most default values of above control bits are designed as specified in initialization step but it is
recommended that user performs all the initialization sequence to avoid any ambiguity.
The relationship between transmission factors and settings of BLH, BLL and CBR is best described in
the following example.

etu

�

(f means SCCLK frequency)

Therefore,

(

)

CBR

BLL

BLH

372

�

7.6 Activation

Card insertion pulls up SCPSNT (assuming SCPSNT is active high with CRF0 bit 0 SCPSNT_POL = 0)
and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after
a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually
applied.

SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and
pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles
to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3).

W83637HF

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Revision 1.3

To meet another timing requirement, tc of ISO/IEC 7816-3, a counter based on SCCLK is implemented
to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR (Answer To
Reset) is detected after 65536 clock cycles from the rising edge of SCRST#.

7.7 Answer-to-Reset

Answer-to-Reset (ATR) is the data streams sent by the card to the interface as an answer to a reset on
SCRST# signal. Refer to ISO/IEC 7816-3 for detailed description of ATR.

There're two kind of cards specified in ISO/IEC 7816-3, inverse convention card and direct convention
card. Although these two conventions treat logical meanings (0 or 1) of voltage levels (low or high)
differently, Winbond's implementation of Smart Card interface decodes a high voltage level data bit as
"1" and low voltage level data bit "0" nevertheless and resorts to software to interpret incoming data.
Software driver needs to interpret initial character of ATR first to determine which convention is for
inserted card and chooses a conversion procedure for it. Subsequent incoming data bytes must be
passed through a conversion procedure before actually transfers these data bytes to host. Similar
conversion procedure must be applied to outgoing data byte before writing to TBR too.

For example, the raw data byte for initial character of inverse-convention ATR would be 03h.
Software driver therefore needs a conversion procedure to reverse bit-significance and polarity to
process subsequent raw data bytes. On the other hand, initial character of direct-convention ATR is
3Bh which needs no conversion procedure to process data byte.

7.8 Data Transfer

Software driver might need to configure control registers again based on information contained in ATR
before process subsequent data transfer. The following guidelines are provided for programming
reference.

1. EPE should be set to "1" for direct-convention card and otherwise for inverse-convention card.
2. BLH, BLL and CBR should be set to comply with Fi and Di.
3. GTR is used for various stop bit requirement of different transmission protocols.
4. SCIODIR controls direction of data transfer.
5. Use interrupt resources to control communication sequence.
6. Monitor SCSR for transmission integrity.

7.9 Cold Reset and Warm Reset

Cold reset is achieved by writing a "1" to bit 7 of ECR. It deactivates SCPWR# to high.
Consequentially, SCRST# is pulled down and SCCLK is stopped. User must write a "0" to ECR bit 7
to resume Smart Card interface to a normal activation state as described in section 2.3.2 assuming
card is still present.

Writing a "1" to ECR bit 0 triggers a warm reset. This is a self-cleared reset operation unlike cold
reset which needs explicit cancellation. Its effect is similar to cold reset except SCPWR# is kept
activated and therefore power supply to card stays on.

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7.10 Power States

W83637HF employs a sophisticated algorithm to partition Smart Card interface's internal circuits to
achieve optimal power utilization. However, users must pay extra care in the design of application
circuits following guidelines stated below to prevent potential signal conflict and unnecessary power
consumption.

There're four power states: disabled state, active state, idle state and power down state. Disabled
state is the default state when power is first applied to the IC. Active state is entered by setting a "1" to
enable bits at bit 0 of CR30 in logical device 0 (refer to Configuration Register section for details). Idle
state means that I/O pins of deselected socket output a predetermined voltage level to disable power
to socket and to prevent leakage from floating connections while Smart Card interface core circuits
might still be servicing other selected socket. SCPWD (Smart Card Power Down, bit 7 of CR22 global
control register) controls whether in active state (SCPWD = 0) or in power down state (SCPWD = 1).

7.11 Disabled State

Smart Card interface is in disabled state initially. Clock is stopped in this state and therefore it is the
least power-consuming state. To prevent current leakage from floating connections, it is designed to
output a predetermined voltage level on all the I/O pins of Smart Card interface as follows:
SCPWR# outputs high to disable power supply to socket;
SCRST#, SCCLK, SCIO, SCC4, SCC8 and SCLED output low;
SCPSNT is tri-stated.

These I/O conditions also apply to both socket A and socket B in power down state (SCPWD = 1) or
deselected socket in idle state. Designers of application circuits must take extra care so that no
contention occurs when Smart Card interface is in those power-saving states. Please refer to
Winbond's recommended application circuit for example.

7.12 Active State

Active state is when Smart Card interface is actually performing all its functions: configuration of control
and interrupt registers, detection of card insertion/extraction, reception of ATR (Answer To Reset)
packet and communication of information between host and card. Refer to section 2.3 for detailed
function description.
Smart Card interface enters active state by setting a "1" to bit 0 of CR30 in logical device 0. This is
the most power-consuming state and actual power consumption is dependent on traffic of interface.

7.13 Idle State

W83637HF supports up to two Smart Card sockets. Only one socket could be active at a time and the
other deselected socket is considered to be in idle state. Selection of active socket is controlled
through socket selection bits which are bits 0 at base address + 3. I/O pins of deselected socket also
output a predetermined voltage level as described in section 2.4.1. Power consumption in this state is
similar to active state because one of the two sockets is selected and core circuit is still functioning.
There is no idle state for W83637HF because only one Smart Card socket is supported and it is always
selected.

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8. CONFIGURATION REGISTER

8.1 Plug and Play Configuration

The W83637HF uses Compatible PNP protocol to access configuration registers for setting up different
types of configurations. In W83637HF, there are eleven Logical Devices (from Logical Device 0 to
Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to
eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2),
UART2 (logical device 3), KBC (logical device 5), CIR (Consumer IR, logical device 6), GPIO1 (logical
device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), ACPI ((logical device A), and hardware
monitor (logical device B). Each Logical Device has its own configuration registers (above CR30).
Host can access those registers by writing an appropriate logical device number into logical device
select register at CR7.

8.1.1 Compatible

PnP

8.1.1.1 Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration
registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the
Extended Function mode as follows:

HEFRAS

Address and Value

Write 87h to the location 2Eh twice

Write 87h to the location 4Eh twice

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After Power-on reset, the value on RTSA# (pin 43) is latched by HEFRAS of CR26. In Compatible
PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port
address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended
Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register)
to identify which configuration register is to be accessed. The designer can then access the desired
configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh).

After programming of the configuration register is finished, an additional value (AAh) should be written
to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration
registers against accidental accesses.

The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.

8.1.1.2 Extended Functions Enable Registers (EFERs)

After a power-on reset, the W83637HF enters the default operating mode. Before the W83637HF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh
or 4Eh (as described in previous section).

8.1.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)

After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as
described in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address
2Fh or 4Fh (as described in section 9.2.1) on PC/AT systems.

8.1.2 Configuration

Sequence

To program W83637HF configuration registers, the following configuration sequence must be followed:
(1). Enter the extended function mode
(2). Configure the configuration registers
(3). Exit the extended function mode

8.1.2.1 Enter the extended function mode

To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to
Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh).

8.1.2.2 Configuration the configuration registers

The chip selects the logical device and activates the desired logical devices through Extended
Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the
same address as EFER, and EFDR is located at address (EFIR+1).

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First, write the Logical Device Number (i.e., 0x07) to the EFIR and then write the number of the desired
logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required.
Secondly, write the address of the desired configuration register within the logical device to the EFIR
and then write (or read) the desired configuration register through EFDR.

8.1.2.3 Exit the extended function mode

To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the
extended function mode, it is in the normal running mode and is ready to enter the configuration mode.

8.1.2.4 Software programming example

The following example is written in Intel 8086 assembly language. It assumes that the EFER is located
at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can
be directly replaced by 4Eh and 2Fh replaced by 4Fh.

;-----------------------------------------------------------------------------------

; Enter the extended function mode ,interruptible double-write |

;-----------------------------------------------------------------------------------

MOV DX,2EH

MOV AL,87H

OUT DX,AL

;-----------------------------------------------------------------------------

; Configuration logical device 1, configuration register CRF0 |

;-----------------------------------------------------------------------------

MOV DX,2EH

MOV AL,07H

OUT

DX,AL

; point to Logical Device Number Reg.

MOV DX,2FH

MOV AL,01H

OUT

DX,AL

; select logical device 1

;

MOV DX,2EH

MOV AL,F0H

OUT

DX,AL

; select CRF0

MOV DX,2FH

MOV AL,3CH

OUT

DX,AL

; update CRF0 with value 3CH

;------------------------------------------

; Exit extended function mode |

;------------------------------------------

MOV DX,2EH

MOV AL,AAH

OUT DX,AL

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CR23 (Default 0x00)

Bit 7 - 1

: Reserved.

Bit 0

: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power
down mode immediately.

CR24 (Default 0b1s000s0s)

Bit 7

: EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification

Bit

6 :CLKSEL

= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 83).

Bit 5 - 3 : Reserved

Bit 2

: ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-
on setting pin is SOUTA (pin 54).

Bit 1

: Reserved

Bit 0

: PNPCSV
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.

When trying to make a change to this bit, new value of PNPCVS must be complementary to the old
one to make an effective change. For example, the user must set PNPCVS to 0 first and then
reset it to 1 to reset these PnP registers if the present value of PNPCVS is 1. The corresponding
power-on setting pin is NDTRA (pin 52).

CR25 (Default 0x00)

Bit 7 - 6 : Reserved

Bit 5

: URBTRI

Bit 4

: URATRI

Bit 3

: PRTTRI

Bit 2 - 1 : Reserved

Bit 0

: FDCTRI.

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CR26 (Default 0b0s000000)

Bit 7

: SEL4FDD
= 0 Select two FDD mode.
= 1 Select four FDD mode.

Bit 6

: HEFRAS

These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is NRTSA (pin 51).
HEFRAS Address and Value
= 0 Write 87h to the location 2E twice.
= 1 Write 87h to the location 4Etwice.

Bit 5

: LOCKREG
= 0 Enable R/W Configuration Registers
= 1 Disable R/W Configuration Registers.

Bit 4

:Reserve

Bit 3

: DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is
effective on selecting IRQ

= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is

not effective on selecting IRQ

Bit 2

: DSPRLGRQ
= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective
on selecting IRQ

= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not

effective on selecting IRQ

Bit 1

: DSUALGRQ
= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on
selecting IRQ

= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ

Bit 0

: DSUBLGRQ

= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on

selecting IRQ

= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on

selecting IRQ

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Revision 1.3

CR28 (Default 0x00)

Bit 7

: PIN5S and PIN7S
= 0 pin5 and pin 7 is selected FDC(DSB and MOS) function
= 1 pin5 and pin 7 is selected FAN3(FANIN3 and FANPWM3) function

Bit 6

: PIN105S
= 0 pin105 is selected HM(OVT#) function
= 1 pin105 is selected HM(SMI#) function

Bit 5

: PIN91S and PIN92S
= Reserved
= 1 Select by CR2B Bit 7 & 6 for SCC4 & SCC8 or GPIO 21 & 22.

Bit 4

: PIN93S
= 0 pin 93 (MSCLK) is setting 8 fingers.
= 1 pin 93 (MSCLK) is setting 6 fingers.

Bit 3

: PIN91S, PIN92S, PIN94S, PIN95S and PIN96S
= 0 pin 91, 92, 94, 95 and 96 are setting 8 fingers.
= 1 pin 91, 92, 94, 95 and 96 are setting 6 fingers.

Bit 2 - 0 : PRTMODS2 - PRTMODS0

= 0xx Parallel Port Mode
= 100 Reserved
= 101 External FDC Mode
= 110 Reserved
= 111 External two FDC Mode

CR29 (GPIO3 multiplexed pin selection register. VBAT powered. Default 0x00)

Bit 7

: PIN64S
= 0 SUSLED (SUSLED control bits are in CRF3 of Logical Device 9)
= 1 GP35

Bit 6

: PIN69S
= 0 CIRRX#
= 1 GP34

Bit 5

: PIN70S
= 0 RSMRST#
= 1 GP33

Bit 4

: PIN71S
= 0 PWROK
= 1 GP32

Bit 3

: PIN72S
= 0 PWRCTL#

= 1 GP31

Bit 2

: PIN 73S
= 0 SLP_SX#
= 1 GP30

Bit 1

: Reserved

Bit 0

: Reserved

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Revision 1.3

CR2B(GPIO multiplexed pin selection register 2. VCC powered. Default 0XC0), continued

Bit 3

: PIN88S
= 0 IRRX
= 1 GP25

Bit 2

: PIN87S
= 0 IRTX
= 1 GP26

Bit 1-0 :PIN 2S

= 00 SCLED.
= 01 SMI#.
= 10 IRQIN1 (select IRQ resource through CRF4 Bit 7-4 of Logical Device8) SMI#
= 11 Reserved.

CR2C (Default 0x00)

Bit 7-1 : Reserved
Bit 0 : MS/SD Multi-Function Pin Select(Pin 58,75,91-96)

= 0 Memory Stick
= 1 Secure Digital
CR2E (Default 0x00)

Test Modes: Reserved for Winbond.

CR2F (Default 0x00)

Test Modes: Reserved for Winbond.

8.3.1 Logical Device 0 (FDC)

CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)

These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.

CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit 3 - 0 : These bits select IRQ resource for FDC.

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Revision 1.3

CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise)

Bit 7 - 3 : Reserved.

Bit 2 - 0 : These bits select DRQ resource for FDC.

= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04 - 0x07 No DMA active

CRF0 (Default 0x0E)
FDD Mode Register

Bit 7

: FIPURDWN

This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.

= 0 The internal pull-up resistors of FDC are turned on.(Default)
= 1 The internal pull-up resistors of FDC are turned off.

Bit 6

: INTVERTZ

This bit determines the polarity of all FDD interface signals.

= 0 FDD interface signals are active low.
= 1 FDD interface signals are active high.

Bit 5

: DRV2EN (PS2 mode only)

When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.

Bit 4

: Swap Drive 0, 1 Mode
= 0 No Swap (Default)
= 1 Drive and Motor select 0 and 1 are swapped.

Bit 3 - 2 :Interface Mode

= 11 AT Mode (Default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30

Bit 1

: FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)

Bit 0

: Floppy Mode
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-mode FDD

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Revision 1.3

CRF1 (Default 0x00)

Bit 7 - 6 : Boot Floppy

= 00 FDD A
= 01 FDD B
= 10 FDD C
= 11 FDD D

Bit 5, 4 : Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7,

Bit 3 - 2 : Density Select

= 00 Normal (Default)
= 01 Normal
= 10 1 ( Forced to logic 1)
= 11 0 ( Forced to logic 0)

Bit 1

: DISFDDWR
= 0 Enable FDD write.
= 1 Disable FDD write(forces pins WE, WD stay high).

Bit 0

: SWWP
= 0 Normal, use WP to determine whether the FDD is write protected or not.
= 1 FDD is always write-protected.

CRF2 (Default 0xFF)

Bit 7 - 6 : FDD D Drive Type

Bit 5 - 4 : FDD C Drive Type

Bit 3 - 2 : FDD B Drive Type

Bit 1 - 0 : FDD A Drive Type

CRF4 (Default 0x00)
FDD0 Selection:

Bit 7

: Reserved.

Bit 6

: Pre-comp. Disable.
= 1 Disable FDC Pre-compensation.
= 0 Enable FDC Pre-compensation.

Bit 5

: Reserved.

Bit 4 - 3 : DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A).

= 00 Select Regular drives and 2.88 format
= 01

3-mode drive

= 10 2 Meg Tape
= 11 Reserved

Bit 2

: Reserved.

Bit 1:0

: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B).

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Revision 1.3

8.3.2 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)

These two registers select Parallel Port I/O base address.
[0x100:0xFFC] on 4 byte boundary (EPP not supported) or

[0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address

is on 8 byte boundary).

CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit [3:0] : These bits select IRQ resource for Parallel Port.

CR74 (Default 0x04)

Bit 7 - 3 : Reserved.

Bit 2 - 0 : These bits select DRQ resource for Parallel Port.

0x00 = DMA0
0x01 = DMA1
0x02 = DMA2
0x03 = DMA3
0x04 - 0x07= No DMA active

CRF0 (Default 0x3F)

Bit 7

: Reserved.

Bit 6 - 3 : ECP FIFO Threshold.

Bit 2 - 0 : Parallel Port Mode (CR28 PRTMODS2 = 0)

= 100 Printer Mode (Default)
= 000 Standard and Bi-direction (SPP) mode
= 001 EPP - 1.9 and SPP mode
= 101 EPP - 1.7 and SPP mode
= 010 ECP mode
= 011 ECP and EPP - 1.9 mode
= 111 ECP and EPP - 1.7 mode.

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8.3.3 Logical Device 2 (UART A)

CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)

These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.

CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit 3 - 0 : These bits select IRQ resource for Serial Port 1.

CRF0 (Default 0x00)

Bit 7 - 2 : Reserved.

Bit 1 - 0 : SUACLKB1, SUACLKB0

= 00 UART A clock source is 1.8462 Mhz (24MHz/13)
= 01 UART A clock source is 2 Mhz (24MHz/12)
= 10 UART A clock source is 24 Mhz (24MHz/1)
= 11 UART A clock source is 14.769 Mhz (24 MHz/1.625)

8.3.4 Logical Device 3 (UART B)

CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)

These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.

CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit [3:0] : These bits select IRQ resource for Serial Port 2.

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Revision 1.3

CRF0 (Default 0x00)

Bit 7 - 4 : Reserved.

Bit 3

: RXW4C
= 0

No reception delay when SIR is changed from TX mode to RX mode.

= 1

Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX
mode to RX mode.

Bit 2

: TXW4C
= 0

No transmission delay when SIR is changed from RX mode to TX mode.

= 1

Transmission delays 4 characters-time (40 bit-time) when SIR is changed from
RX mode to TX mode.

Bit 1 - 0 : SUBCLKB1, SUBCLKB0

= 00 UART B clock source is 1.8462 MHz (24MHz/13)
= 01 UART B clock source is 2 MHz (24MHz/12)
= 10 UART B clock source is 24 MHz (24MHz/1)
= 11 UART B clock source is 14.769 MHz (24 MHz/1.625)

CRF1 (Default 0x00)

Bit 7

: Reserved.

Bit 6

: IRLOCSEL. IR I/O pins' location select.
= 0

Through SINB/SOUTB.

= 1

Through IRRX/IRTX.

Bit 5

: IRMODE2. IR function mode selection bit 2.

Bit 4

: IRMODE1. IR function mode selection bit 1.

Bit 3

: IRMODE0. IR function mode selection bit 0.

IR MODE

IR FUNCTION

IRTX

IRRX

00X Disable tri-state

High

010* IrDA

Active pulse 1.6

�S

Demodulation into
SINB/IRRX

011*

IrDA

Active pulse 3/16 bit time

Demodulation into
SINB/IRRX

100

ASK-IR

Inverting IRTX/SOUTB pin

routed to SINB/IRRX

101 ASK-IR

Inverting IRTX/SOUTB & 500 KHZ
clock

routed to SINB/IRRX

110 ASK-IR Inverting

IRTX/SOUTB

Demodulation into
SINB/IRRX

111* ASK-IR

Inverting IRTX/SOUTB & 500 KHZ
clock

Demodulation into
SINB/IRRX

Note: The notation is normal mode in the IR function.

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Revision 1.3

Bit 2

: HDUPLX. IR half/full duplex function select.
= 0

The IR function is Full Duplex.

= 1

The IR function is Half Duplex.

Bit 1

: TX2INV
= 0

The SOUTB pin of UART B function or IRTX pin of IR function in normal
condition.

= 1

Inverse the SOUTB pin of UART B function or IRTX pin of IR function.

Bit 0

: RX2INV.
= 0

The SINB pin of UART B function or IRRX pin of IR function in normal condition.

= 1

Inverse the SINB pin of UART B function or IRRX pin of IR function

8.3.5 Logical Device 5 (KBC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x00, 0x60 if PNPCSV = 0 during POR, default 0x00 otherwise)

These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary.

CR62, CR 63 (Default 0x00, 0x64 if PNPCSV = 0 during POR, default 0x00 otherwise)

These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary.

CR70 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit [3:0] : These bits select IRQ resource for KINT (keyboard).

CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit [3:0] : These bits select IRQ resource for MINT (PS2 Mouse)

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Revision 1.3

CRF0 (Default 0x80)

Bit 7 - 6 : KBC clock rate selection

= 00 Select 6 MHz as KBC clock input.
= 01 Select 8 MHz as KBC clock input.
= 10 Select 12 MHz as KBC clock input.
= 11 Select 16 MHz as KBC clock input.
(W83637HF-AW can support these 4 kinds of clock input)

Bit 5 - 3 : Reserved.

Bit 2

= 0 Port 92 disable.
= 1 Port 92 enable.

Bit 1

= 0 Gate20 software control.
= 1 Gate20 hardware speed up.

Bit 0

= 0 KBRST software control.
= 1 KBRST hardware speed up.

8.3.6 Logical Device 6 (CIR)
CR30 (Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x00, 0x00)

These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary.

CR70 (Default 0x00)

Bit 7 - 4 : Reserved.

Bit [3:0] : These bits select IRQ resource for CIR.

8.3.7 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1)

CR30 (Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activate Game Port and MIDI Port.
= 0 Game Port and MIDI Port is inactive.

CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)

These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary.

W83637HF

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Revision 1.3

CR62, CR 63 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise)

These two registers select the MIDI Port base address [0x100:0xFFF] on 2 byte boundary.

CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise)

Bit 7 - 4 : Reserved.

Bit [3:0] : These bits select IRQ resource for MIDI Port.

CRF0 (GP10-GP17 I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.

CRF1 (GP10-GP17 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.

CRF2 (GP10-GP17 inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.

8.3.8 Logical Device 8 (GPIO Port 2 This power of the Port is VCC source)
CR30 (GP20-GP27 Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activate GPIO2.
= 0 GPIO2 is inactive.

CRF0 (GP20-GP27 I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.

CRF1 (GP20-GP27 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.

CRF2 (GP20-GP27 inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.

W83637HF

Publication Release Date: June 25, 2003

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Revision 1.3

CRF3 (Default 0x00)

Bit 7 - 4 : These bits select IRQ resource for IRQIN1.

Bit 3 - 0 : These bits select IRQ resource for IRQIN0.

CRF4 (Reserved)

CRF5 (PLED mode register. Default 0x00)

Bit 7-6 : select PLED mode

= 00 Power LED pin is tri-stated.
= 01 Power LED pin is driven low.
= 10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle
= 11 Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle.

Bit 5-4 : Reserved

Bit 3

: select WDTO count mode.
= 0 Second
= 1 Minute

Bit 2

: Enable the rising edge of keyboard Reset(P20) to force Time-out event.
= 0 Disable
= 1 Enable

Bit 1-0 : Reserved

CRF6 (Default 0x00)

Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load
the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set, any Mouse
Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded non-zero value to
Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog
Counter instead of Watch Dog Timer Time-out value.

Bit 7 - 0 = 0x00 Time-out Disable

= 0x01 Time-out occurs after 1 second/minute
= 0x02 Time-out occurs after 2 second/minutes
= 0x03 Time-out occurs after 3 second/minutes
................................................
= 0xFF Time-out occurs after 255 second/minutes

W83637HF

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Revision 1.3

CRF7 (Default 0x00)

Bit 7

: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt

Bit 6

: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt

Bit 5

: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.

Bit 4

: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred
= 0 Watch Dog Timer counting

Bit 3 -0 : These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.

8.3.9 Logical Device 9 (GPIO Port 3 This power of the Port is standby source (VSB) )

CR30 (Default 0x00)

Bit 7 - 1 : Reserved

Bit 0

= 1 Activate GPIO3.
= 0 GPIO3 is inactive.

CRF0 (GP30-GP35 I/O selection register. Default 0xFF Bit 7-6: Reserve)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.

CRF1 (GP30-GP35 data register. Default 0x00 Bit 7-6: Reserve)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.

CRF2 (GP30-GP35 inversion register. Default 0x00 Bit 7-6: Reserve)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.

CRF3 (SUSLED mode register. Default 0x00)

Bit 7-6 : select Suspend LED mode

= 00 Suspend LED pin is drove low.
= 01 Suspend LED pin is tri-stated.
= 10 Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle.
= 11 Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle.

This mode selection bit 7-6 keep its settings until battery power loss.

Bit 5 - 0 : Reserved.

W83637HF

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Revision 1.3

8.4 Logical Device A (ACPI)

(The CR30, 70, F0~F9 are VCC power source; CR E0~E7 are VRTC power source)

CR30 (Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR70 (Default 0x00)

Bit 7 - 4 : Reserved.

Bit 3 - 0 : These bits select IRQ resources for

PME

CRE0 (Default 0x00)

Bit 7

: DIS-PANSW_IN. Disable panel switch input to turn system power supply on.
= 0

PANSW_IN is wire-ANDed and connected to PANSW_OUT.

= 1

PANSW_IN is blocked and can not affect PANSW_OUT.

Bit 6

: ENKBWAKEUP. Enable Keyboard to wake-up system via PANSW_OUT.
= 0

Disable Keyboard wake-up function.

= 1

Enable Keyboard wake-up function.

Bit 5

: ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT.
= 0

Disable Mouse wake-up function.

= 1

Enable Mouse wake-up function.

Bit 4

: MSRKEY. This bit combining with MSXKEY (bit 1 of CRE0 of logical device A) and
ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up
event can trigger an active low pulse on PSOUT#. Their combination is described in the
following table.

ENMDAT_UP MSRKEY

MSXKEY

Wake up event

Any button click or any movement

one click of left/right button

one click of left button

one click of right button

two times click of left button

two times click of right button

Bit

3 : ENCIRWAKEUP. Enable CIR to wake-up system via PSOUT#.

= 0 Disable CIR wake-up function.
= 1 Enable CIR wake-up function.

Bit

2 : KB/MS Swap. Enable Keyboard/Mouse port-swap.

= 0

Keyboard/Mouse ports are not swapped.

= 1

Keyboard/Mouse ports are swapped.

W83637HF

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Revision 1.3

Bit

1 : MSXKEY. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and

ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up
event can trigger an active low pulse on PSOUT#. Their combination is described in the
following table.

ENMDAT_UP MSRKEY

MSXKEY

Wake up event

Any button click or any movement

One click of left/right button

One click of left button

One click of right button

Two times click of left button

Two times click of right button

Bit

0 : KBXKEY. Enable any character received from Keyboard to wake-up the system

= 0 Only predetermined specific key combination can wake up the system.
= 1

Any character received from Keyboard can wake up the system.

CRE1 (Default 0x00) Keyboard Wake-Up Index Register

This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register
is to be read/written via CRE2. The first set of wake up key combination is in the range of 0x00 - 0x0E,
the second set 0x30 � 0x3E, and the third set 0x40 � 0x4E. Incoming key combination can be read
through 0x10 � 0x1E. The range of CIR wake-up index register is in 0x20 - 0x2F.

CRE2 Keyboard Wake-Up Data Register

This register holds the value of wake-up key register indicated by CRE1. This register can be
read/written.

CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register

Bit 7-5 : Reserved.

Bit 4

: PWRLOSS_STS: This bit is set when power loss occurs.

Bit 3

: CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared

by reading this register.

Bit 2

: PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by

reading this register.

Bit 1

: Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is

cleared by reading this register.

Bit 0

: Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit

is cleared by reading this register.

W83637HF

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Revision 1.3

CRE4 (Default 0x00)

Bit 7

: Power loss control bit 2.
0 = Disable ACPI resume
1 = Enable ACPI resume

Bit 6-5 : Power loss control bit <1:0>

00 = System always turn off when come back from power loss state.
01 = System always turn on when come back from power loss state.
10 = System turn on/off when come back from power loss state depend on the state

before power loss.

11 = Reserved.

Bit 4

: Suspend clock source select
0 = Use internal clock source.
1 = Use external suspend clock source(32.768KHz).

Bit 3

: Keyboard wake-up type select for wake-up the system from S1/S2.
0 = Password or Hot keys programmed in the registers.
1 = Any key.

Bit 2

: Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This

bit is cleared when wake-up event occurs.

0 = Disable.
1 = Enable.

Bit 1 - 0 : Reserved.

CRE5 (Default 0x00)

Bit 7

: Reserved.

Bit 6 - 0 : Compared Code Length. When the compared codes are storied in the data register,

these data length should be written to this register.

CRE6 (Default 0x00)

Bit 7

: ENMDAT_UP. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and
MSXKEY (bit 1 of CRE0 of logical device A) define what kind of mouse wake-up event
can trigger an active low pulse on PSOUT#. Their combination is described in the
following table.

ENMDAT_UP MSRKEY

MSXKEY

Wake up event

Any button click or any movement

One click of left/right button

One click of left button

One click of right button

Two times click of left button

Two times click of right button

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Revision 1.3

CRE6 (Default 0x00), continued
Bit6 : EN_SCUP. Enable SCPSNT# of Smart Card interface to wake up system through

PSOUT#.
0 = Disable.
1 = Enable.

Bit 5 - 0 : CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz

divided by ( CIR Baud Rate Divisor + 1).

CRE7 (Default 0x00)

Bit 7

: ENKD3. Enable the third set of keyboard wake-up key combinations. Its values are
accessed through keyboard wake-up index register (CRE1 of logical device A) and
keyboard wake-up data register (CRE2 of logical device A) at index from 40h to 4eh.
= 0

Disable wake-up function of the third set of key combinations.

= 1

Enable wake-up function of the third set of key combinations.

Bit 6

: ENKD2. Enable the second set of keyboard wake-up key combinations. Its values
are accessed through keyboard wake-up index register (CRE1 of logical device A) and
keyboard wake-up data register (CRE2 of logical device A) at index from 30h to 3eh.
= 0

Disable wake-up function of the second set of key combinations.

= 1

Enable wake-up function of the second set of key combinations.

Bit 5

: ENWIN98KEY. Enable WIN98 keyboard dedicated key to wake up system through
PANSW_OUT if keyboard wake up function is enabled.
0 = Disable WIN98 keyboard wake up.
1 = Enable WIN98 keyboard wake up.

Bit 4

: EN_ONPSOUT. Enable to issue a 0.5 s long PSOUT# pulse when system returns
from power loss state and is supposed to be on as described in CRE4 bit 6, 5 of logical
device A.

0 = Disable this function.
1 = Enable this function.

Bit 3

: SELWDTORST: Select whether Watch Dog timer function is reset by LRESET_L signal
or PWROK signal.
0 = Watch Dog timer function is reset by LRESET_L signal.
1 = Watch Dog timer function is reset by PWROK signal.

Bit 2

: Reset CIR Power-On function. After using CIR power-on, the software should write
logical 1 to restart CIR power-on function.

Bit 1

: Invert RX Data.
= 1 Inverting RX Data.
= 0 Not inverting RX Data.

Bit 0

: Enable Demodulation.
= 1 Enable received signal to demodulate.
= 0 Disable received signal to demodulate.

W83637HF

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Revision 1.3

CRF0 (Default 0x00)

Bit 7

: CHIPPME. Chip level auto power management enable.
= 0

Disable the auto power management functions

= 1

Enable the auto power management functions.

Bit 6

: CIRPME. Consumer IR port auto power management enable.
= 0

Disable the auto power management functions

= 1

Enable the auto power management functions.

Bit 5

: MIDIPME. MIDI port auto power management enable.
= 0

Disable the auto power management functions

= 1

Enable the auto power management functions.

Bit 4

: Reserved. Return zero when read.

Bit 3

: PRTPME. Printer port auto power management enable.
= 0

Disable the auto power management functions.

= 1

Enable the auto power management functions.

Bit 2

: FDCPME. FDC auto power management enable.
= 0

Disable the auto power management functions.

= 1

Enable the auto power management functions.

Bit 1

: URAPME. UART A auto power management enable.
= 0

Disable the auto power management functions.

= 1

enable the auto power management functions.

Bit 0

: URBPME. UART B auto power management enable.
= 0

Disable the auto power management functions.

= 1

Enable the auto power management functions.

CRF1 (Default 0x00)

Bit 7

: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will transition the
system to the working state. This bit is only set by hardware and is cleared by writing a 1
to this bit position or by the sleeping/working state machine automatically when the global
standby timer expires.
= 0 The chip is in the sleeping state.
= 1 The chip is in the working state.

Bit 6 - 5 : Devices' trap status.

Bit 4

: Reserved. Return zero when read.

Bit 3 - 0 : Devices' trap status.

W83637HF

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Revision 1.3

CRF3 (Default 0x00)

Bit 7 - 0 : Device's IRQ status.

These bits indicate the IRQ status of the individual device respectively. The device's
IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has
no effect.

Bit 7

: MSIRQSTS. MS IRQ status.

Bit 6

: Reserved

Bit 5

: MOUIRQSTS. MOUSE IRQ status.

Bit 4

: KBCIRQSTS. KBC IRQ status.

Bit 3

: PRTIRQSTS. printer port IRQ status.

Bit 2

: FDCIRQSTS. FDC IRQ status.

Bit 1

: URAIRQSTS. UART A IRQ status.

Bit 0

: URBIRQSTS. UART B IRQ status.

CRF4 (Default 0x00)

Bit 7

: Reserved. Return zero when read.

Bit 6 - 0 : These bits indicate the IRQ status of the individual GPIO function or logical device

respectively. The status bit is set by their source function or device and is cleared by
writing a1. Writing a 0 has no effect.

Bit 6

: SCIRQSTS. SC IRQ status.

Bit 5

: HMIRQSTS. Hardware monitor IRQ status.

Bit 4

: WDTIRQSTS. Watch dog timer IRQ status.

Bit 3

: CIRIRQSTS. Consumer IR IRQ status.

Bit 1

: IRQIN1STS. IRQIN1 status.

Bit 0

: IRQIN0STS. IRQIN0 status.

W83637HF

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Revision 1.3

CRF6 (Default 0x00)

Bit 7 - 0 : Enable bits of the

SMI

PME

generation due to the device's IRQ.

These bits enable the generation of an

SMI

PME

interrupt due to any IRQ of the

devices.

SMI

PME

logic output = (MOUIRQEN and MOUIRQSTS) or (KBCIRQEN and

KBCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS)
or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or
(HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or
(IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or
(IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS)

Bit 7

: MSIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to MS's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to MS's IRQ.

Bit

6 Reserved

Bit 5

: MOUIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to MOUSE's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to MOUSE's IRQ.

Bit 4

: KBCIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to KBC's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to KBC's IRQ.

Bit 3

: PRTIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to printer port's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to printer port's IRQ.

Bit 2

: FDCIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to FDC's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to FDC's IRQ.

Bit 1

: URAIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to UART A's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to UART A's IRQ.

Bit 0

: URBIRQEN.
= 0

disable the generation of an

SMI

PME

interrupt due to UART B's IRQ.

= 1

enable the generation of an

SMI

PME

interrupt due to UART B's IRQ.

W83637HF

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Revision 1.3

CRF7 (Default 0x00)

Bit 7

: Reserved. Return zero when read

Bit 6 - 0 : Enable bits of the

SMI

PME

generation due to the GPIO IRQ function or device's IRQ.

Bit 6

: SCIRQEN.

= 0

Disable the generation of an

SMI

PME

interrupt due to SC's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to SC's IRQ.

Bit 5

: HMIRQEN.

= 0

Disable the generation of an

SMI

PME

interrupt due to hardware monitor's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to hardware monitor's IRQ.

Bit 4

: WDTIRQEN.

= 0

Disable the generation of an

SMI

PME

interrupt due to watch dog timer's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to watch dog timer's IRQ.

Bit 3

: CIRIRQEN.

= 0

Disable the generation of an

SMI

PME

interrupt due to CIR's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to CIR's IRQ

Bit 2

: MIDIIRQEN.

= 0

Disable the generation of an

SMI

PME

interrupt due to MIDI's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to MIDI's IRQ.

Bit 1

: IRQIN1EN.

= 0

Disable the generation of an

SMI

PME

interrupt due to IRQIN1's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to IRQIN1's IRQ.

Bit 0

: IRQIN0EN.

= 0

Disable the generation of an

SMI

PME

interrupt due to IRQIN0's IRQ.

= 1

Enable the generation of an

SMI

PME

interrupt due to IRQIN0's IRQ.

W83637HF

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Revision 1.3

CRF9 (Default 0x00)

Bit 7 - 3 : Reserved. Return zero when read.

Bit

2 : PME_EN: Select the power management events to be either an

PME

SMI

interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1.

= 0 The power management events will generate an

SMI

event

= 1 The power management events will generate an

PME

event.

Bit 1

: FSLEEP: This bit selects the fast expiry time of individual devices.
= 0 1 second.
= 1 8 milli-seconds

Bit

0 : SMIPME_OE: This is the

SMI

and

PME

output enable bit.

= 0 Neither

SMI

nor

PME

will be generated. Only the IRQ status bit is set.

= 1 An

SMI

PME

event will be generated.

CRFE, FF (Default 0x00)
Reserved for Winbond test.

8.5 Logical Device B (Hardware Monitor)

CR30 (Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

= 1 Activates the logical device.
= 0 Logical device is inactive.

CR60, CR 61 (Default 0x00, 0x00)

These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary.

CR70 (Default 0x00)

Bit 7 - 4 : Reserved.

Bit 3 - 0 : These bits select IRQ channel for Hardware Monitor.

8.6 Logical Device C (Smart Card interface)

CR30 (Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

: Logical device active bit.
= 0 Logical device is inactive.
= 1 Activates the logical device.

CR60, CR61 (Default 0x00, 0x00)

These two registers select Smart Card interface base address [0x100:0xFFF] on 8-byte boundary.

W83637HF

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Revision 1.3

CR70 (Default 0x00)

Bit 7 - 4 : Reserved.

Bit 3 - 0 : These bits select IRQ channel for Smart Card interface.

CRF0 (Default 0x00)

Bit 7 - 1 : Reserved.

Bit 0

SCPSNT_POL (Smart Card Present Polarity). SCPSNT polarity bit.
= 0

SCPSNT is active high.

= 1

SCPSNT is active low.

8.7 Logical Device D (MS/SD Card Interface)

CR30 (Default 0x00)

Bit 7 - 3 : Reserved.

Bit 2

: SD Card Interface Active Bit
= 0 SD card interface is inactive.
= 1 SD card interface is active.

Bit 1

: MS Card Interface Active Bit
= 0 MS card interface is inactive.
= 1 MS card interface is active.

Bit 0

: MS/SD card interface active bit.
= 0 Both MS & SD card interface is inactive.
= 1 Both MS & SD card interface is active.

CR60, CR61 (Default 0x00, 0x00)

These two registers select MS/SD Card interface base address [0x100:0xFFF] on 8-byte boundary.

CR70 (Default 0x00)

Bit 7 - 4 : Reserved.

Bit 3 - 0 : These bits select IRQ channel for MS/SD Card interface.

CR74 (Default 0x04)

Bit 7 - 3 : Reserved.

Bit 2 - 0 : These Bits Select DMA Channel for MS/SD Card Port.

0x00 = DMA0
0x01 = DMA1
0x02 = DMA2
0x03 = DMA3
0x04 - 0x07 = No DMA active

W83637HF

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Revision 1.3

9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings

PARAMETER RATING

UNIT

Power Supply Voltage (5V)

-0.5 to 7.0

Input Voltage

-0.5 to V

+0.5 V

RTC Battery Voltage V

BAT

2.2 to 4.0

Operating Temperature

0 to +70

�C

Storage Temperature

-55 to +150

�C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

9.2 DC Characteristics

= 0

�

C to 70

�

C, V

= 5V

�

10%, V

= 0V)

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

RTC Battery Quiescent
Current

BAT

2.4 uA

BAT

= 2.5 V

ACPI Stand-by Power
Supply Quiescent Current

BAT

2.0

= 5.0 V, All ACPI pins

are not connected.

I/O

- TTL level bi-directional pin with 8mA source-sink capability

Input Low Voltage

0.8 V

Input High Voltage

2.0

Output Low Voltage

0.4 V

= 8 mA

Output High Voltage

2.4

V I

= - 8 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

I/O

12t

- TTL level bi-directional pin with 12mA source-sink capability

Input Low Voltage

0.8 V

Input High Voltage

2.0

Output Low Voltage

0.4 V

= 12 mA

Output High Voltage

2.4

V I

= -12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

W83637HF

Publication Release Date: June 25, 2003

- 130 -

Revision 1.3

DC Characteristics, continued

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

I/O

24t

- TTL level bi-directional pin with 24mA source-sink capability

Input Low Voltage

0.8 V

Input High Voltage

2.0

Output Low Voltage

0.4 V

= 24 mA

Output High Voltage

2.4

V I

= -24 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

I/O

12tp3

� 3.3V TTL level bi-directional pin with 12mA source-sink capability

Input Low Voltage

0.8 V

Input High Voltage

2.0

Output Low Voltage

0.4 V

= 12 mA

Output High Voltage

2.4

V I

= -12 mA

Input High Leakage

LIH

+10

�A

= 3.3V

Input Low Leakage

LIL

-10

�A

= 0V

I/O

12ts

- TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability

Input Low Threshold
Voltage

0.5 0.8 1.1 V

Input High Threshold
Voltage

1.6 2.0 2.4 V

Hystersis V

0.5 1.2

V V

=5V

Output Low Voltage

0.4 V

= 12 mA

Output High Voltage

2.4

V I

= -12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

I/O

24ts

- TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability

Input Low Threshold
Voltage

0.5 0.8 1.1 V

Input High Threshold
Voltage

1.6 2.0 2.4 V

Hystersis V

0.5 1.2

V V

= 5V

Output Low Voltage

0.4 V

= 24 mA

Output High Voltage

2.4

V I

= -24 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

W83637HF

Publication Release Date: June 25, 2003

- 131 -

Revision 1.3

DC Characteristics, continued

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

I/O

24tsp3

� 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability

Input Low Threshold
Voltage

0.5 0.8 1.1 V

Input High Threshold
Voltage

1.6 2.0 2.4 V

Hystersis V

0.5 1.2

V V

= 3.3V

Output Low Voltage

0.4 V

= 24 mA

Output High Voltage

2.4

V I

= -24 mA

Input High Leakage

LIH

+10

�A

= 3.3V

Input Low Leakage

LIL

-10

�A

= 0V

I/OD

12t

- TTL level bi-directional pin and open-drain output with 12mA sink capability

Input Low Voltage

0.8 V

Input High Voltage

2.0

Output Low Voltage

0.4 V

= 12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

I/OD

24t

- TTL level bi-directional pin and open-drain output with 24mA sink capability

Input Low Voltage

0.8 V

Input High Voltage

2.0

Output Low Voltage

0.4 V

= 24 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

I/OD

12ts

- TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink

capability

Input Low Threshold
Voltage

0.5 0.8 1.1 V

Input High Threshold
Voltage

1.6 2.0 2.4 V

Hystersis V

0.5 1.2

V V

= 5V

Output Low Voltage

0.4 V

= 12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

W83637HF

Publication Release Date: June 25, 2003

- 132 -

Revision 1.3

DC Characteristics, continued

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

I/OD

24ts

- TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink

capability

Input Low Threshold
Voltage

0.5 0.8 1.1 V

Input High Threshold
Voltage

1.6 2.0 2.4 V

Hystersis V

0.5 1.2

V V

= 5V

Output Low Voltage

0.4 V

= 24 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0V

I/OD

12cs

- CMOS level Schmitt-trigger bi-directional pin and open drain output with 12mA

sink capability

Input Low Threshold
Voltage

1.3

1.5 1.7 V

= 5 V

Input High Threshold
Voltage

3.2 3.5

3.8 V

= 5 V

Hystersis V

1.5 2

V V

= 5 V

Output Low Voltage

0.4 V

= 12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

I/OD

16cs

- CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA

sink capability

Input Low Threshold
Voltage

1.3

1.5 1.7 V

= 5 V

Input High Threshold
Voltage

3.2 3.5

3.8 V

= 5 V

Hystersis V

1.5 2

V V

= 5 V

Output Low Voltage

0.4 V

= 16 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

W83637HF

Publication Release Date: June 25, 2003

- 133 -

Revision 1.3

DC Characteristics, continued

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

I/OD

12csd

- CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and

open drain output with 12mA sink capability

Input Low Threshold
Voltage

1.3 1.5 1.7 V

= 5 V

Input High Threshold
Voltage

3.2 3.5

3.8 V V

= 5 V

Hystersis V

1.5 2

V V

= 5 V

Output Low Voltage

0.4 V

= 12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

I/OD

12csu

- CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and

open drain output with 12mA sink capability

Input Low Threshold
Voltage

1.3 1.5 1.7 V

= 5 V

Input High Threshold
Voltage

3.2 3.5

3.8 V V

= 5 V

Hystersis V

1.5 2

V V

= 5 V

Output Low Voltage

0.4 V

= 12 mA

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

- Output pin with 4mA source-sink capability

Output Low Voltage

0.4 V

= 4 mA

Output High Voltage

2.4

V I

= -4 mA

- Output pin with 8mA source-sink capability

Output Low Voltage

0.4 V

= 8 mA

Output High Voltage

2.4

V I

= -8 mA

- Output pin with 12mA source-sink capability

Output Low Voltage

0.4 V

= 12 mA

Output High Voltage

2.4

V I

= -12 mA

- Output pin with 16mA source-sink capability

Output Low Voltage

0.4 V

= 16 mA

Output High Voltage

2.4

V I

= -16 mA

W83637HF

Publication Release Date: June 25, 2003

- 134 -

Revision 1.3

DC Characteristics, continued

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

- Output pin with 24mA source-sink capability

Output Low Voltage

0.4 V

= 24 mA

Output High Voltage

2.4

V I

= -24 mA

12p3

- 3.3V output pin with 12mA source-sink capability

Output Low Voltage

0.4 V

= 12 mA

24p3

- 3.3V output pin with 24mA source-sink capability

Output Low Voltage

0.4 V

= 24 mA

- Open drain output pin with 12mA sink capability

Output Low Voltage

0.4 V

= 12 mA

- Open drain output pin with 24mA sink capability

Output Low Voltage

0.4 V

= 24 mA

12p3

- 3.3V open drain output pin with 12mA sink capability

Output Low Voltage

0.4 V

= 12 mA

- TTL level input pin

Input Low Voltage

0.8 V

Input High Voltage

2.0

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

tp3

- 3.3V TTL level input pin

Input Low Voltage

0.8 V

Input High Voltage

2.0

Input High Leakage

LIH

+10

�A

= 3.3V

Input Low Leakage

LIL

-10

�A

= 0 V

- TTL level input pin with internal pull down resistor

Input Low Voltage

0.8 V

Input High Voltage

2.0

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

W83637HF

Publication Release Date: June 25, 2003

- 135 -

Revision 1.3

DC Characteristics, continued

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT CONDITIONS

- TTL level input pin with internal pull up resistor

Input Low Voltage

0.8 V

Input High Voltage

2.0

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

- TTL level Schmitt-trigger input pin

Input Low Threshold
Voltage

0.5 0.8 1.1 V

= 5 V

Input High Threshold
Voltage

1.6 2.0 2.4 V V

= 5 V

Hystersis V

0.5 1.2

V V

= 5 V

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

tsp3

- 3.3 V TTL level Schmitt-trigger input pin

Input Low Threshold
Voltage

0.5 0.8 1.1 V

= 3.3 V

Input High Threshold
Voltage

1.6 2.0 2.4 V V

= 3.3 V

Hystersis V

0.5 1.2

V V

= 3.3 V

Input High Leakage

LIH

+10

�A

= 3.3 V

Input Low Leakage

LIL

-10

�A

= 0 V

- CMOS level input pin

Input Low Voltage

1.5 V

Input High Voltage

3.5

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

- CMOS level input pin with internal pull down resistor

Input Low Voltage

1.5 V

Input High Voltage

3.5

Input High Leakage

LIH

+10

�A

= 5V

Input Low Leakage

LIL

-10

�A

= 0 V

W83637HF

Publication Release Date: June 25, 2003

- 138 -

Revision 1.3

12. PACKAGE DIMENSIONS

(128-pin QFP)

Detail F

102

1.Dimension D & E do not include interlead

flash.

2.Dimension b does not include dambar

protrusion/intrusion

3.Controlling dimension : Millimeter
4.General appearance spec. should be based

on final visual inspection spec.

Note:

Seating Plane

See Detail F

128

103

5. PCB layout please use the "mm".

Symbol

b
c
D

e
H

y
0

A
A

0.08

1.60

0.95

17.40

0.80

17.20

0.65

17.00

14.10

0.20

0.30

2.87

14.00

2.72

0.50

13.90

0.10

2.57

0.25

Min

Nom

Max

Dimension in mm

0.20

0.15

19.90

20.00

20.10

23.00

23.20

23.40

0.35

0.45

0.003

0.063

0.037

0.685

0.031

0.677

0.025

0.669

0.020

0.555

0.008

0.012

0.113

0.551

0.107

0.547

0.004

0.101

0.010

Max

Nom

Min

Dimension in inch

0.006

0.008

0.783

0.787

0.791

0.905

0.913

0.921

0.014

0.018

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

W83637HF

Publication Release Date: June 25, 2003

- 139 -

Revision 1.3

13. APPENDIX A:

MOA#

MS4

MS1

KBRST

PD4

.1UF

MIDI PORT

CASEOPEN#

LAD[0..3]

BEEP

PD6

LAD3

GA20M

RDATA#

RIA#

INDEX#

RTSA#

WDTO

OVT#

.1UF

Printer

MSCLK

PD3

PANSWOUT#

CPUVCORE

IRTX

PS2 Mouse.

DIR#

JP1

HEADER

|637HFD6.SCH

OSC

VCC

O/P

GND

SCRWLED

RSMRST#

SCCLK

DSRB#

STEP#

PD5

SCRST#

COMB & IR

|637HFD4.SCH

Use 627HF remove
parts R2,R4

Use 637HF remove
parts R1,R3

ACK#

INIT#

LDRQ#

IO5V

GPY2

SOUTB

GPSB1

FANPWM2

WD#

DSKCHG#

CPUTIN

|637HFD5.SCH

CPUD-

MS I/F

LPC INTERFACE

IO3V

GPY1

PD0

MOB#

IO5V

DTRB#

To Power supply for turn ON VCC.

DSRA#

Keyboard &

IO3V

LRESET#

CPUD-

WE#

HEAD#

|LINK

BUSY

MS3

IO5V

SUSLED

SINA

SERIRQ

GPSA2

MSPWCTL#

AVCC

MDAT

PD2

|637HFD2.SCH

COMA

RTSB#

IRRX

For Wake Up Function

MCLK

FANPWM1

SLP_SX#

STB#

ERR#

MS2

VIN2

AFD#

LFRAME#

VIN1

WINBOND ELECTRONICS CORP.

SLCT

PD1

.1UF

MS5

R10

PCICLK

Smart

Card

PSIN

MOB#

PWRCTL#

GPX2

W83637HF(W83627HF)

2 3

5 6

7 8

9 10

12 13

14 15

16 17

18 19

21 22

23 24

25 26

28 29

30 31

32 33

35 36

37 38

100

101

102

103
104

105
106

107
108
109

110
111

112
113

114
115

116
117
118

119
120

121
122

123
124
125

126
127

128

DRV

CRWL

I
R

I
N/

I
#

(DRV

/
I
R

I
N1

)

EX#

SB#/F

SB#)

SA#

B#/F

(
M

OB#)

EP#

WD# WE

AK0#

RDA

EAD

CHG

I
N

VSS

DRQ

SER

LAD

CC3

ESET

SLC

PD3

PD2

PD1

PD0

SLIN#

INIT#

ERR#

AFD#

STB#

VCC

CTSA#

DSRA#

HEFRAS/RTSA#

PNPCSV/DTRA#

SINA

PENKBC/SOUTA

VSS

DCDA#

RIA#

(KBLOCK#)MSRWLED/MSWPRO

GA20M

KBRST

VSB

KCLK

KDAT

SUSLED/GP35

MCL

MDA

PSOU

PSIN

RRX

/
G

GP33

K/GP32

L#/

GP31

SLP_SX#/GP30

VBAT

I
N)MS

CTL

/
S

CTL

ASEOPEN

SB#

(
R

SB#)

SB#/PEN

(
D

B#)

B#/PEN

SIN

SOU

B/PEN

DCDB

VSS

/GP2

I
RRX

/
G

WDT

/
G

PLED

/GP23

/
S

CC8

/
M

/
S

CC4

/
M

ND)MS

(-5

I
N

)MS

(-1

I
N

)MS

I
N

)MS

CC)V

I
N2

VIN

(
V

EB)

VIN

)
CP

I
N3

I
N

CPUTIN(VTIN2)
SYSTIN(VTIN1)
OVT#

SCPWCTL#(VID4)
SCRST#(VID3)

SCIO(VID2)
SCPSNT(VID1)

SCCLK(VID0)
CPUD-(FANIO3)
FANIN2

FANIN1
+5VIN

FANPWM2
FANPWM1

VSS
BEEP
MSI/GP20

MSO/IRQIN0
GPSA2/GP17

GPSB2/GP16
GPY1/GP15

GPY2/P16/GP14
GPX2/P15/GP13

GPX1/P14/GP12
GPSB1/P13/GP11
GPSA1/P12/GP10

DCDB#

SCPSNT

FANIN2

H/W MONITOR

MSRWLED

SLIN#

SCPWCTL#

LAD1

637HFD1.SCH

0.3

W83637HF CIRCUIT (LPC I/O)

Winbond Electronic Corp.

13, 2002

Title

Size

Document Number

Rev

Date:

Sheet

KDAT

LAD[0..3]

PWROK

VREF

0.1UF

PD[0..7]

VTIN

CTSA#

CIRRX

DCDA#

DTRA#

PME#

GPSB2

DSA#

TRAK0#

Indicated the VCC is OK.

DSB#

WP#

PLED

FANIN1

AVCC

IO5V

RWC#

SCIO

DSB#

.1UF

IOBAT

SINB

IO5V

GPX1

GPSA1

AVCC

RIB#

MSI

10K

SYSTIN

GAME PORT

KCLK

SCRWLED

JP2

HEADER 17X2

IOVSB

PD7

LAD0

SOUTA

MSO

|637HFD3.SCH

IO5V

LAD2

CTSB#

W83637HF

Publication Release Date: June 25, 2003

- 140 -

Revision 1.3

IO5V

MSO

BATTERY CIRCUIT

C12

47P

MSI

IOBAT

C10

0.1U

637HFD2.SCH

0.3

GAME & MIDI & KBC

WINBOND ELECTRONICS CORP.

13, 2002

Title

Size

Document Number

Rev

Date:

Sheet

R28

C15

0.01U

GPSB2

GAME & MIDI PORT CIRCUIT

IO5V

KDAT

R24 2.2K

C21

0.01U

MDAT

IO5V

OnNow or Wake_up function power

GPX1

FUSE

IO5V

C20

0.01U

JP3

KB/MS

IO5V

GPY2

C17

0.01U

BT1

BATTERY

R27

C13

0.1U

C16

0.01U

VWAKE

HEADER 6

3
4

VWAKE CIRCUIT

KCLK

R25 2.2K

R12
4.7K

R11
4.7K

R19

2.2K

R26 2.2K

R14
4.7K

IO5V

GPSA2

10U

GPSA1

R13
4.7K

R29

R30

R15

HEADER 6

3
4

C22

0.01U

GPX2

IOVSB

R17

2.2K

47P

R18

2.2K

1N4148

GPY1

C19

0.01U

JP4

HEAD3

IO5V

KEYBOARD

R16

100K

47P

VWAKE

PS2 MOUSE

R22 2.2K

1N4148

WINBOND ELECTRONICS CORP.

R23 2.2K

MCLK

JP5:1-2 Clear CMOS

R21 2.2K

C14

0.01U

IO5V

C11

47P

PRT

1N4148

GPSB1

2-3 Enable ONNOW functions

R20

2.2K

C18

0.01U

W83637HF

Publication Release Date: June 25, 2003

- 141 -

Revision 1.3

SOUTA

MSPWCTL#

NDTRB

IO_5V

RIB#

NDCDA

NDSRB

COM PORT

1)MS1, MS2, MS3,MS4,MS5 ARE STAND
FOR MEMORY STICK MEMORY PIN
DEFINITION

NRIA

MS2

NRIB

RTSA#

SINA

IO+12V

MS5

IO3V

R34

4.7

SOUTA

NRTSA

DCDA#

R33

CONNECTOR DB9

C24

OPEN

VWAKE

W83778

VCC

DA1

DA2

DA3

RY1

RY2

RY3

RY4

RY5

GND

+12V

DY1

DY2

DY3

RA1

RA2

RA3

RA4

RA9

-12V

C26

10UF

SCCLK

CTSA#

RIA#

NSINA

NSINB

637HFD3.SCH

0.3

UART + CARD READER

WINBOND ELECTRONICS CORP.

13, 2002

Title

Size

Document Number

Rev

Date:

Sheet

NCTSA

RTSB#

NCTSA

NDCDA

CN2X5

WINBOND CARD READER

IO5V

NRIB

CTSB#

SCRST#

GND

NCTSB

MS1

W83778

VCC

DA1

DA2

DA3

RY1

RY2

RY3

RY4

RY5

GND

+12V

DY1

DY2

DY3

RA1

RA2

RA3

RA4

RA9

-12V

IO5V

GND

NDTRB

MS4

R31

4.7K

1) U5 is a 2.54mm, 2* 5

connector

SINB

NSOUTA

DCDA#

IRTX

3) JP6 is a 2.00 mm, 1* 10

connector

IO-12V

NRTSB

C25

OPEN

CTSA#

MSRWLED

NDCDB

NDSRA

NRTSB

NOTE:

SCRWLED

NDTRA

NSOUTA

NDCDB

DTRB#

SCIO

SINA

DSRB#

NDSRA

NSOUTB

R32

DTRA#

NCTSB

IO-12V

NRIA

IO5V

MS3

COMA

NSINA

NDTRA

NSINB

NRTSA

COMB

RIA#

(UARTA)

IRRX

JP6

MEM STICK

SOUTB

DSRA#

NSOUTB

MSCLK

JP5

HEADER 5X2

(UARTB)

DSRA#

IR/CIR CONNECTOR

C23

10UF

CIRRX

SCPWCTL#

WINBOND ELECTRONICS CORP.

DTRA#

(SOP20)

IO+12V

2)The trade marks and intellectual property rights
of Memory Stick belong to SONY Corporation.
Information check:http:www.memorystick.org

DCDB#

SCPSNT

SC_CON

VCC

PWR

SCIO

CLK

GND

RST

RWLED

PSNT

(SOP20)

RTSA#

NOTE:

NDSRB

W83637HF

Publication Release Date: June 25, 2003

- 144 -

Revision 1.3

SUSLED

SW DIP-5

1
2

4
5

10
9

7
6

RP12

4.7K

DTRA#

PENKBC

CLK 24M

IO3V

JP9

HEADER 2

RTSA#

637HFD6.SCH

0.3

GPIO + PWR SETTING

WINBOND Electronics Corp.

13, 2002

Title

Size

Document Number

Rev

Date:

Sheet

ONLY FOR 637HF

SOUTA

DTRB#

PEN48

CLK 48M

R?(8P4RA1

4.7K

ONLY FOR 637HF

SOUTB

IO5V

POWER ON SETTING PIN

IO5V

RSMRST#

SUSLED

SUSPEND LED CIRCUIT

I/O CONFIGURATION ADDRESS

WINBOND ELECTRONICS CORP.

RP9

4.7K

SOUTB

HEFRAS

LFRAME#

I/O PORT BASE DEFAULT VALUE

LAD[0..3]

PNPCSV

POWER LED CIRCUIT

SOUTA

RP8

4.7K

PIN18 INPUT CLK VALUE

Q6
2N3904

PENKBC

IOVSB

GP42

R65

10K

SOUTB

Signal Pullhigh

PEN48

IO5V

2N3904

PSIN

SERIRQ

SOUTA

LED

PENFDDB#

IOVSB

C47

0.1U

IO3V

LDRQ#

RP10

4.7K

R60 150

DTRA#

PENMS#

PANEL SWITCH

PANSWOUT#

DTRB#

R59 4.7K

PLED

RTSB#

IO5V

DTRA#

R62 150

IOVSB

POWER ON SETTING PIN

DEFAULT

R63

4.7K

RTSB#

RP11

4.7K

FDDB

R64

10K

IO3VSB

R61 4.7K

STREN

ALL 0

PWRCTL#

FAN3

HEFRAS

KBC ENABLE

RTSA#

IOVSB

PNPCSV

KBC DISABLE

PME#

Электронный компонент: W83637HF