W83877F
WINBOND I/O
Publication Release Date: January 1996
- 1 -
Revision A2
GENERAL DESCRIPTION
One of Winbond's popular series of I/O chips, the W83877F integrates a disk drive adapter, serial
port (UART), parallel port, IDE bus interface, and game port decoder onto a single chip. The
W83877F is an enhanced version of the W83777F, with additional powerful features such as
configurable plug-and-play registers for the whole chip and infrared support in one of the serial ports.
The disk drive adapter functions of the W83877F include a floppy disk drive controller compatible
with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic,
data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The
wide range of functions integrated onto the W83877F greatly reduces the number of components
required for interfacing with floppy disk drives. The W83877F supports four 360K, 720K, 1.2M, 1.44M,
or 2.88M disk drives and data transfer rates of 250 Kb/S, 300 Kb/S, 500 Kb/S, and 1 Mb/S.
The W83877F provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system.
The W83877F supports one PC-compatible printer port. Additional bidirectional I/O capability is
available by hardware control or software programming. The parallel port also supports the Enhanced
Parallel Port (EPP) and Extended Capabilities Port (ECP).
The W83877F supports two embedded hard disk drive (AT bus) interfaces and a game port with
decoded read/write output. The chip's Extension FDD Mode and Extension 2FDD Mode allow one or
two external floppy disk drives to be connected to the computer through the printer interface pins in
notebook computer applications.
The Extension Adapter Mode of the W83877F allows pocket devices to be installed through the
printer interface pins in notebook computer applications according to a protocol set by Winbond, but
with upgraded performance. The JOYSTICK mode allows a joystick to be connected to a parallel port
with a signal switching cable.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Moreover, the configurable PnP registers are compatible with the plug-and-play feature in
Windows 95
TM
, which makes system resource allocation more efficient than ever.
W83877F
- 2 -
FEATURES
FDC:
Compatible with IBM PC AT disk drive systems
Variable write pre-compensation with track selectable capability
DMA enable logic
Non-burst mode DMA option
Supports floppy disk drives and tape drives
Detects all overrun and underrun conditions
Data rate and drive control registers
Built-in address mark detection circuit to simplify the read electronics
IBM PC system address decoder
Supports up to two embedded hard disk drives (IDE AT BUS)
Single 24 MHz crystal input
FDD anti-virus functions with software write protect and FDD write enable signal, write data signal
force inactive
Supports up to four 3.5-inch or 5.25-inch floppy disk drives
Completely compatible with industry standard 82077
360K/720K/1.2M/1.44M/2.88M format
250K, 300K, 500K, 1M bps data transfer rate
Supports vertical recording format
16-byte data FIFOs
UART:
Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
MIDI compatible
Fully programmable serial-interface characteristics:
-
5, 6, 7 or 8-bit characters
-
Even, odd or no parity bit generation/detection
-
1, 1.5 or 2 stop bits generation
Internal diagnostic capabilities:
-
Loop-back controls for communications link fault isolation
-
Break, parity, overrun, framing error simulation
Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (2
16
-1)
Parallel Port:
W83877F
Publication Release Date: January 1996
- 3 -
Revision A2
Compatible with IBM parallel port
Supports parallel port with bidirectional lines
Supports Enhanced Parallel Port (EPP)
-
Compatible with IEEE 1284 specification
Supports Extended Capabilities Port (ECP)
-
Compatible with IEEE 1284 specification
Extension FDD mode supports disk drive B through parallel port
Extension Adapter Mode supports pocket devices through parallel port
Extension 2FDD mode supports disk drives A and B through parallel port
JOYSTICK mode supports joystick through parallel port
Others:
Programmable configuration settings
Immediate or automatic power-down mode for power management
All hardware power-on settings have internal pull-up or pull-down resistors as default value
Packaged in 100-pin QFP
Configurable Plug and Play registers
Infrared communication port
W83877F
- 4 -
PIN CONFIGURATION
/
M
O
B
/
M
O
A
/
T
R
A
K
0
N
W
P
/
D
S
K
C
H
G
A
1
0
/
R
D
A
T
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
G
N
D
/
I
O
W
/
I
O
R
A
E
N
A
9
A
8
A
7
A
6
A
5
V
D
D
A
4
A
3
A
2
A
1
A
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RIB
DCDB
DSRB
CTSB
DTRB
RTSB
IRQ_C
SOUTB
SINB
GMRD
GND
GMWR
SOUTA
IRQ_D
RTSA
DTRA
CTSA
DSRA
DCDA
RIA
/
R
E
S
I
D
E
/
C
S
P
D
C
I
N
D
R
Q
|
C
I
O
C
H
R
D
Y
M
R
X
T
A
L
1
X
T
A
L
2
P
D
0
P
D
1
P
D
2
P
D
3
P
D
4
V
D
D
P
D
5
P
D
6
P
D
7
/
D
A
C
K
|
C
/
S
T
B
/
A
F
D
/
I
N
I
T
/
S
L
I
N
I
R
Q
|
E
B
U
S
Y
G
N
D
/
A
C
K
P
E
S
L
C
T
/
E
R
R
S
I
N
A
INDEX
STEP
DSA
DSB
WE
WD
RWC
HEAD
DIR
GND
IDBEN
IRQ_B
IRQIN
CS0
CS1
IRQ_A
TC
DACK_B
IRQ_F
DRQ_B
W83877F
Publication Release Date: January 1996
- 5 -
Revision A2
1.0 PIN DESCRIPTION
Note: Refer to section 9.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bidirectional pin with 8 mA source-sink capability
I/O12t - TTL level bidirectional pin with 12 mA source-sink capability
I/O24t - TTL level bidirectional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt
- TTL level input pin
INc
- CMOS level input pin
INcs - CMOS level schmitt-triggered input pin
1.1 Host Interface
SYMBOL
PIN
I/O
FUNCTION
D0
-
D7
66-73
I/O
24t
System data bus bits 0-7
A0
-
A9
51-55
57-61
IN
c
System address bus bits 0-9
A10
75
IN
c
In ECP Mode, this pin is the A10 address input.
IOCHRDY
5
OD
24
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR
6
IN
cs
Master Reset. Active high. MR is low during normal operations.
CS
2
IN
t
Active low chip select signal
AEN
62
IN
c
System address bus enable
IOR
63
IN
cs
CPU I/O read signal
IOW
64
IN
cs
CPU I/O write signal
DRQ_B
100
OUT
12t
DMA request signal B
DACK_B
98
IN
c
DMA Acknowledge signal B
DRQ_C
4
OUT
12t
DMA request signal C
DACK_ C
18
IN
c
DMA Acknowledge signal C
TC
97
IN
c
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
IRQIN
93
IN
c
Interrupt request input
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