W83977ATF

WINBOND I/O

Publication Release Date: April 1998

-1-

Preliminary Revision 0.52

GENERAL DESCRIPTION

The W83977ATF is an

evolving product

from Winbond

s most popular I/O chip W83877F --- which

integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug-
and-play registers for the whole chip --- plus additional powerful features:

ACPI, 8042 keyboard

controller with PS/2 mouse support,

general purpose I/O ports, full 16-bit address decoding,

OnNow keyboard wake-up, OnNow mouse wake-up, and OnNow CIR wake-up.

In addition, the

W83977ATF provides IR functions:

IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps) and TV remote

IR (

Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols).

The disk drive adapter functions of W83977ATF include a floppy disk drive controller compatible with
the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data
rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide
range of functions integrated onto the W83977ATF greatly reduces the number of components
required for interfacing with floppy disk drives. The W83977ATF supports four 360K, 720K, 1.2M,
1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2
Mb/s.

The W83977ATF provides two high-speed serial communication ports (UARTs), one of which
supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete modem control capability, and a processor interrupt
system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and

also

advanced speed

with

baud rates

230k, 460k, or 921k bps which support higher speed modems. The W83977ATF

provides independent

3rd UART(32-byte FIFO) dedicated for the IR function.

The W83977ATF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP)
and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer
port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one
or two external floppy disk drives to be connected.

The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95

, which makes system resource allocation more efficient than ever.

The W83977ATF provides functions that comply with

ACPI (Advanced Configuration and Power

Interface), which includes support of legacy and ACPI power management through SMI or

SCI

function pins. The W83977ATF also has auto power management to reduce power consumption.

The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEY

Phoenix MultiKey/42

, or customer code.

The W83977ATF provides a set of flexible I/O control functions to the system designer through a set
of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.

The W83977ATF is made to fully comply with

Microsoft PC97 Hardware Design Guide. IRQs,

DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover

W83977ATF is made to meet the specification of PC97

s requirement in the power management:

ACPI and DPM (Device Power Management).

Another benifit

is that W83977ATF has the same pin assignment as W83977AF, W83977F,

W83977TF

. This makes the design very flexible.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-2-

Revision 0.52

FEATURES

General

Plug & Play 1.0A

compatible

Support 13 IRQs, 4 DMA channels, full 16-bit address decoding

Capable of ISA Bus IRQ Sharing

Compliant with

Microsoft PC97 Hardware Design Guide

Support

DPM (Device Power Management), ACPI

Report ACPI status interrupt by

SCI

signal issued from any of the 13 IQRs pins or GPIO xx

Programmable configuration settings

Single 24/48 Mhz clock input

FDC

Compatible with IBM PC AT disk drive systems

Variable write pre-compensation with track selectable capability

Support vertical recording format

DMA enable logic

16-byte data FIFOs

Support floppy disk drives and tape drives

Detects all overrun and underrun conditions

Built-in address mark detection circuit to simplify the read electronics

FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)

Support up to four 3.5-inch or 5.25-inch floppy disk drives

Completely compatible with industry standard 82077

360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate

Support

3-mode FDD, and its Win95 driver

UART

Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs

MIDI compatible

Fully programmable serial-interface characteristics:

--- 5, 6, 7 or 8-bit characters

--- Even, odd or no parity bit generation/detection

--- 1, 1.5 or 2 stop bits generation

Internal diagnostic capabilities:

--- Loop-back controls for communications link fault isolation

--- Break, parity, overrun, framing error simulation

Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (2

-1)

Maximum baud rate up to

921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-3 -

Revision 0.52

Infrared

Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps

Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps

Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol

--- Single DMA channel for transmitter or receiver

--- 3rd UART with 32-byte FIFO is supported in both TX/RX transmission

--- 8-byte status FIFO is supported to store received frame status (such as overrun CRC error,

etc.)

Support auto-config SIR and FIR

Parallel Port

Compatible with IBM parallel port

Support PS/2 compatible bi-directional parallel port

Support Enhanced Parallel Port (EPP)

Compatible with IEEE 1284 specification

Support Extended Capabilities Port (ECP)

Compatible with IEEE 1284 specification

Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and
B through parallel port

Enhanced printer port back-drive current protection

Keyboard Controller

8042 based with optional F/W from AMIKKEY

-2, Phoenix MultiKey/42

or customer code

with 2K bytes of programmable ROM, and 256 bytes of RAM

Asynchronous Access to Two Data Registers and One status Register

Software compatibility with the 8042 and PC87911 microcontrollers

Support PS/2 mouse

Support port 92

Support both interrupt and polling modes

Fast Gate A20 and Hardware Keyboard Reset

8 Bit Timer/ Counter

Support binary and BCD arithmetic

6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency

General Purpose I/O Ports

programmable general purpose I/O ports;

dedicate,

optional

General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog
timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control
I/O pins

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-5 -

Revision 0.52

PIN CONFIGURATION

1 2 3 4 5 6 7 8 9

S 5

64
63

62
61
60
59
58

56
55

54
53

52
51
50
49
48

47
46
45

44
43
42

VBAT

XTAL1

VSS
XTAL2

MDATA
KDATA
KBLOCK/GP13

KBRST/GP12
GA20/GP11
VCC
DCDB
SOUTB/PEN48
SINB

DTRB

RTSB
DSRB
CTSB

DCDA

SOUTA/PENKBC

SINA
DTRA/PNPCSV
RTSA/HEFRAS

DSRA
CTSA

CIRRX/GP24
IRRXH/IRSL0

40
39

103

104
105
106

107
108

109
110
111
112
113
114

115

116
117

118
119
120

121
122
123
124
125

126

127
128

IRQ14/GP14

IRQ15/GP15

IOR

IOW

AEN

IOCHRDY

D1
D2

VCC

DACK0/GP16

VSS

SCI/DRQ0/GP17

DACK1

DRQ1

DACK2

DRQ2

DACK3

DRQ3

N T

S
W

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-6-

Revision 0.52

1.0 PIN DESCRIPTION

Note: Please refer to Section 12.2 DC CHARACTERISTICS for details.

I/O

- TTL level bi-directional pin with 6 mA source-sink capability

I/O

- TTL level bi-directional pin with 8 mA source-sink capability

I/O

- CMOS level bi-directional pin with 8 mA source-sink capability

I/O

12t

- TTL level bi-directional pin with 12 mA source-sink capability

I/O

- CMOS level bi-directional pin with 12 mA source-sink capability

I/O

16u

- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor

I/OD

16u

- CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor

I/O

24t

- TTL level bi-directional pin with 24 mA source-sink capability

OUT

- TTL level output pin with 8 mA source-sink capability

OUT

12t

- TTL level output pin with 12 mA source-sink capability

- Open-drain output pin with 12 mA sink capability

- Open-drain output pin with 24 mA sink capability

- TTL level input pin

- CMOS level input pin

- CMOS level input pin with internal pull-up resitor

- CMOS level Schmitt-triggered input pin

- TTL level Schmitt-triggered input pin

tsu

- TTL level Schmitt-triggered input pin with internal pull-up resistor

1.1 Host Interface

SYMBOL

PIN

I/O

FUNCTION

A10

74-84

System address bus bits 0-10.

A11-A14

86-89

System address bus bits 11-14.

A15

System address bus bit 15.

109-

114

I/O

12t

System data bus bits 0-5.

116-

117

I/O

12t

System data bus bits 6-7.

IOR

105

CPU I/O read signal.

IOW

106

CPU I/O write signal.

AEN

107

System address bus enable.

IOCHRDY

108

In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.

118

Master Reset; Active high; MR is low during normal operations.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-7 -

Revision 0.52

1.1 Host Interface, continued

SYMBOL

PIN

I/O

FUNCTION

DACK0

119

tsu

DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,
default)

GP16
(WDTO)

I/O

12t

General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)

Alternate function from GP16: Watch dog timer output.

P15

I/O

12t

KBC P15 I/O port. (CR2C bit 5_4 = 10)

DRQ0

121

OUT

12t

DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)

GP17
(PLEDO)

I/O

12t

General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)

Alternate Function from GP17: Power LED output.

P14

I/O

12t

KBC P14 I/O port. (CR2C bit 7_6 = 10)

SCI

System Control Interrupt.(CR2C bit 7_6 = 11)

In the ACPI power management mode,

SCI

is driven low by the

power management events.

DACK1

122

DMA Channel 1 Acknowledge signal .

DRQ1

123

OUT

12t

DMA Channel 1 request signal.

DACK2

124

DMA Channel 2 Acknowledge signal.

DRQ2

125

OUT

12t

DMA Channel 2 request signal.

DACK3

126

DMA Channel 3 Acknowledge signal.

DRQ3

127

OUT

12t

DMA Channel 3 request signal.

128

Terminal Count. When active, this pin indicates termination of a
DMA transfer.

IRQ1

OUT

12t

Interrupt request 1. (Logical device 9, CRF1 bit 2 = 0)

IRQ1

I/O

12t

General purpose I/O port 3 bit 0.

(Logical device 9, CRF1 bit 2 = 1)

IRQ3

OUT

12t

Interrupt request 3. (Logical device 9, CRF1 bit 2 = 0)

GP31

I/O

12t

General purpose I/O port 3 bit 1.

(Logical device 9, CRF1 bit 2 = 1)

IRQ4

OUT

12t

Interrupt request 4. (Logical device 9, CRF1 bit 2 = 0)

GP32

I/O

12t

General purpose I/O port 3 bit 2.

(Logical device 9, CRF1 bit 2 = 1)

IRQ5

OUT

12t

Interrupt request 5. (Logical device 9, CRF1 bit 2 = 0)

GP33

I/O

12t

General purpose I/O port 3 bit 3.

(Logical device 9, CRF1 bit 2 = 1)

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-8-

Revision 0.52

1.1 Host Interface, continued

SYMBOL

PIN

I/O

FUNCTION

IRQ6

OUT

12t

Interrupt request 6. (Logical device 9, CRF1 bit 2 = 0)

GP34

I/O

12t

General purpose I/O port 3 bit 4.

(Logical device 9, CRF1 bit 2 = 1)

IRQ7

OUT

12t

Interrupt request 7. (Logical device 9, CRF1 bit 2 = 0)

GP35

I/O

12t

General purpose I/O port 3 bit 5.

(Logical device 9, CRF1 bit 2 = 1)

IRQ8

OUT

12t

Interrupt request 8. (Logical device 9, CRF1 bit 2 = 0)

GP36

I/O

12t

General purpose I/O port 3 bit 6.

(Logical device 9, CRF1 bit 2 = 1)

IRQ9

OUT

12t

Interrupt request 9. (Logical device 9, CRF1 bit 2 = 0)

GP37

I/O

12t

General purpose I/O port 3 bit 7.

(Logical device 9, CRF1 bit 2 = 1)

IRQ10

100

OUT

12t

Interrupt request 10. (Logical device 9, CRF1 bit 2 = 0)

SERIRQ

I/O

12t

Serial IRQ input/output. (Logical device 9, CRF1 bit 2 = 1)

IRQ11

101

OUT

12t

Interrupt request 11. (Logical device 9, CRF1 bit 2 = 0)

PCICLK

PCI clock input. (Logical device 9, CRF1 bit 2 = 1)

IRQ12

102

OUT

12t

Interrupt request 12. (Logical device 9, CRF1 bit 2 = 0)

GP26

I/O

12t

General purpose I/O port 2 bit 6.

(Logical device 9, CRF1 bit 2 = 1)

IRQ14

103

OUT

12t

Interrupt request 14. (CR2C bit 1_0 = 00, default)

GP14

I/O

12t

General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)

( GPACS )

Alternate Function 1 from GP14: General purpose address
decode output.

(P17)

Alternate Function 2 from GP14: KBC P17 I/O port.

PLEDO

OUT

12t

Power LED output. (CR2C bit 1_0 = 10)

IRQ15

104

OUT

12t

Interrupt request 15.(CR2C bit 3_2 = 00, default)

GP15

( GPAWE )

I/O

12t

General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)

Alternate Function 1 from GP15: General purpose address write
enable output.

(P12)

Alternate Function 2 from GP15: KBC P12 I/O port.

WDT

OUT

12t

Watch-Dog timer output. (CR2C bit 3_2 = 10)

CLKIN

24 or 48 MHz clock input, selectable through CR24 bit 6.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-9 -

Revision 0.52

1.2 General Purpose I/O Port

SYMBOL

PIN

I/O

FUNCTION

GP20

I/O

12t

General purpose I/O port 2 bit 0.

(KBRST)

Alternate Function from GP20: Keyboard reset. (KBC P20)

SMI

System Management Interrupt. (CR2B bit 4_3 = 00, default)

In the legacy power management mode, SMI

is driven

low by

the power managenment events.

GP21

I/O

12t

General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01)

(P13)

Alternate Function from GP21: KBC P13 I/O port.

P16

I/O

12t

KBC P16 I/O port. (CR2B bit 4_3 = 10)

PANSWOUT

GP22

I/O

12t

Panel Switch output. (CR2B bit 5 = 0, default)

General purpose I/O port 2 bit 2. (CR2B bit 5 = 1)

(P14)

Alternate Function from GP22: KBC P14 I/O port.

PANSWIN

GP23

12t

I/O

12t

Panel Switch input. (CR2B bit 7_6 = 00, default)

General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01)

(P15)

Alternate Function from GP23: KBC P15 I/O port.

GP24

I/O

12t

General purpose I/O port 2 bit 4.

(CR2A bit 5_4 = 01)

(P16)

Alternate Function from GP24: KBC P16 I/O port.

P13

I/O

12t

KBC P13 I/O port. (CR2A bit 5_4 = 10)

CIRRX

Consumer IR receiving input. (CR2A bit 5_4 = 00)

GP25

I/O

General purpose I/O port 2 bit 5. (CR2A bit 3_2 = 10)

(GA20)

Alternate Function from GP25: GATE A20. (KBC P21)

IRRXH

FIR receiving input. (CR2A bit 3_2 = 00)

IRSL0

OUT

12t

IR module select 0. (CR2A bit 3_2 = 01)

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-10-

Revision 0.52

1.3 Serial Port Interface

SYMBOL

PIN

I/O

FUNCTION

CTSA

CTSB

Clear To Send. This is the modem control input.

The function of these pins can be tested by reading bit 4 of the
handshake status register.

DSRA

DSRB

Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.

RTSA

I/O

UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.

HEFRAS

During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for
CR26 bit 6 (HEFRAS). A 4.7 k

is recommended if intends to

pull up. (select 370H as configuration I/O port

s address)

RTSB

I/O

UART B Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.

DTRA

PNPCSV

I/O

UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.

During power-on reset, this pin is pulled down internally and is

defined as PNPCSV , which provides the power-on value for

CR24 bit 0 ( PNPCSV ). A 4.7 k

is recommended if intends to

pull up. (clear the default value of FDC, UARTs, and PRT)

DTRB

I/O

UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.

SINA
SINB

45, 52

Serial Input. It is used to receive serial data through the
communication link.

SOUTA

I/O

UART A Serial Output. It is used to transmit serial data out to the
communication link.

PENKBC

During power-on reset, this pin is pulled down internally and is
defined as PENKBC, which provides the power-on value for
CR24 bit 2 (ENKBC). A 4.7 k

resistor is recommended if

intends to pull up. (enable KBC)

SOUTB

PEN48

I/O

UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as

PEN48

, which provides the

power-on value for CR24 bit 6 (

EN48

). A 4.7 k

resistor is

recommended if intends to pull up.

DCDA
DCDB

Data Carrier Detect. An active low signal indicates the modem
or data set has detected a data carrier.

RIA

RIB

Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-11 -

Revision 0.52

1.4 Infrared Interface

SYMBOL

PIN

I/O

FUNCTION

IRRX

Infrared Receiver input.

IRTX

OUT

12t

Infrared Transmitter Output.

1.5 Multi-Mode Parallel Port

The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.

SYMBOL

PIN

I/O

FUNCTION

SLCT

PRINTER MODE: SLCT

An active high input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to the
description of the parallel port for definition of this pin in ECP
and EPP mode.

EXTENSION FDD MODE:

WE2

This pin is for Extension FDD B; its function is the same as the

pin of FDC.

EXTENSION 2FDD MODE: WE2

This pin is for Extension FDD A and B; its function is the same
as the WE pin of FDC.

PRINTER MODE: PE

An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.

EXTENSION FDD MODE: WD2

This pin is for Extension FDD B; its function is the same as the

WD pin of FDC.

EXTENSION 2FDD MODE: WD2

This pin is for Extension FDD A and B; its function is the same
as the WD pin of FDC.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-12-

Revision 0.52

1.5 Multi-Mode Parallel Port, continued

SYMBOL

PIN

I/O

FUNCTION

BUSY

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to the
description of the parallel port for definition of this pin in ECP
and EPP mode.

EXTENSION FDD MODE: MOB2

This pin is for Extension FDD B; its function is the same as the
MOB pin of FDC.

EXTENSION 2FDD MODE: MOB2

This pin is for Extension FDD A and B; its function is the same
as the MOB pin of FDC.

ACK

PRINTER MODE: ACK

An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is
pulled high internally. Refer to the description of the parallel port
for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: DSB2

This pin is for the Extension FDD B; its functions is the same as
the DSB pin of FDC.

EXTENSION 2FDD MODE: DSB2

This pin is for Extension FDD A and B; its function is the same
as the DSB pin of FDC.

ERR

PRINTER MODE: ERR

An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.

EXTENSION FDD MODE: HEAD2

This pin is for Extension FDD B; its function is the same as the
HEADpin of FDC.

EXTENSION 2FDD MODE: HEAD2

This pin is for Extension FDD A and B; its function is the same
as the HEAD pin of FDC.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-13 -

Revision 0.52

1.5 Multi-Mode Parallel Port, continued

SYMBOL

PIN

I/O

FUNCTION

SLIN

PRINTER MODE: SLIN

Output line for detection of printer selection. This pin is pulled
high internally. Refer to the description of the parallel port for
the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: STEP2

This pin is for Extension FDD B; its function is the same as the

STEP pin of FDC.

EXTENSION 2FDD MODE: STEP2

This pin is for Extension FDD A and B; its function is the same
as the STEP pin of FDC.

INIT

PRINTER MODE: INIT

Output line for the printer initialization. This pin is pulled high
internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: DIR2

This pin is for Extension FDD B; its function is the same as the
DIR pin of FDC.

EXTENSION 2FDD MODE: DIR2

This pin is for Extension FDD A and B; its function is the same
as the DIR pin of FDC.

AFD

PRINTER MODE: AFD

An active low output from this pin causes the printer to auto feed
a line after a line is printed. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.

EXTENSION FDD MODE: DRVDEN0

This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.

EXTENSION 2FDD MODE: DRVDEN0

This pin is for Extension FDD A and B; its function is the same
as the DRVDEN0 pin of FDC.

STB

PRINTER MODE: STB
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to the description
of the parallel port for the definition of this pin in ECP and EPP
mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION 2FDD MODE: This pin is a tri-state output.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-14-

Revision 0.52

1.5 Multi-Mode Parallel Port, continued

SYMBOL

PIN

I/O

FUNCTION

PD0

I/O

24t

PRINTER MODE: PD0

Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: INDEX2

This pin is for Extension FDD B; its function is the same as the
INDEX pin of FDC. It is pulled high internally.

EXTENSION 2FDD MODE: INDEX2

This pin is for Extension FDD A and B; its function is the same
as the INDEX pin of FDC. It is pulled high internally.

PD1

I/O

24t

PRINTER MODE: PD1

Parallel port data bus bit 1. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: TRAK02

This pin is for Extension FDD B; its function is the same as the

TRAK0 pin of FDC. It is pulled high internally.

EXTENSION. 2FDD MODE: TRAK02

This pin is for Extension FDD A and B; its function is the same
as the TRAK0 pin of FDC. It is pulled high internally.

PD2

I/O

24t

PRINTER MODE: PD2

Parallel port data bus bit 2. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: WP2

This pin is for Extension FDD B; its function is the same as the

pin of FDC. It is pulled high internally.

EXTENSION. 2FDD MODE: WP2

This pin is for Extension FDD A and B; its function is the same
as the WP pin of FDC. It is pulled high internally.

PD3

I/O

24t

PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: RDATA2
This pin is for Extension FDD B; its function is the same as the
RDATA pin of FDC. It is pulled high internally.

EXTENSION 2FDD MODE: RDATA2
This pin is for Extension FDD A and B; its function is the same
as the RDATA pin of FDC. It is pulled high internally.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-15 -

Revision 0.52

1.5 Multi-Mode Parallel Port, continued

SYMBOL

PIN

I/O

FUNCTION

PD4

I/O

24t

PRINTER MODE: PD4
Parallel port data bus bit 4. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: DSKCHG2
This pin is for Extension FDD B; the function of this pin is the
same as the DSKCHG pin of FDC. It is pulled high internally.

EXTENSION 2FDD MODE: DSKCHG2
This pin is for Extension FDD A and B; this function of this pin is
the same as the

DSKCHG

pin of FDC. It is pulled high internally.

PD5

I/O

24t

-
-

PRINTER MODE: PD5
Parallel port data bus bit 5. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.

PD6

I/O

24t

PRINTER MODE: PD6

Parallel port data bus bit 6. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION. 2FDD MODE: MOA2

This pin is for Extension FDD A; its function is the same as the
MOA pin of FDC.

PD7

I/O

24t

PRINTER MODE: PD7

Parallel port data bus bit 7. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION 2FDD MODE: DSA2

This pin is for Extension FDD A; its function is the same as the
DSA pin of FDC.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-16-

Revision 0.52

1.6 FDC Interface

SYMBOL

PIN

I/O

FUNCTION

DRVDEN0

Drive Density Select bit 0.

DRVDEN1

Drive Density Select bit 1. (CR2A bit 1_0 = 00, default)

GP10

24t

General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01)

(IRQIN1)

Alternate Function from GP10: Interrupt channel input.

P12

24t

KBC P12 I/O port. (CR2A bit 1_0 = 10)

SCI

System Control Interrupt. (CR2A bit 1_0 = 11)

In the ACPI power management mode,

SCI

is driven low by the

power management events.

HEAD

Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1

Write enable. An open drain output.

Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.

STEP

Step output pulses. This active low open drain output produces
a pulse to move the head to another track.

DIR

Direction of the head step motor. An open drain output.

Logic 1 = outward motion

Logic 0 = inward motion

MOB

Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.

DSA

Drive Select A. When set to 0, this pin enables disk drive A.
This is an open drain output.

DSB

Drive Select B. When set to 0, this pin enables disk drive B.
This is an open drain output.

MOA

Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.

DSKCHG

Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by a 1 K

resistor. The resistor can be disabled by bit

7 of L0-CRF0 (FIPURDWN).

W83977ATF

PRELIMINARY

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Revision 0.52

1.6 FDC Interface, continued

SYMBOL

PIN

I/O

FUNCTION

RDATA

The read data input signal from the FDD. This input pin is pulled
up internally by a 1 K

resistor. The resistor can be disabled by

bit 7 of L0-CRF0 (FIPURDWN).

Write protected. This active low Schmitt input from the disk
drive indicates that the diskette is write-protected. This input pin
is pulled up internally by a 1 K

resistor. The resistor can be

disabled by bit 7 of L0-CRF0 (FIPURDWN).

TRAK0

Track 0. This Schmitt-triggered input from the disk drive is
active low when the head is positioned over the outermost track.
This input pin is pulled up internally by a 1 K

resistor. The

resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

INDEX

This Schmitt-triggered input from the disk drive is active low
when the head is positioned over the beginning of a track
marked by an index hole. This input pin is pulled up internally by
a 1 K

resistor. The resistor can be disabled by bit 7 of L0-CRF0

(FIPURDWN).

1.7 KBC Interface

SYMBOL

PIN

I/O

FUNCTION

KDATA

I/O

16u

Keyboard Data.

MDATA

I/O

16u

PS2 Mouse Data.

KCLK

I/O

16u

Keyboard Clock.

MCLK

I/O

16u

PS2 Mouse Clock.

GA20

I/O

12t

KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default)

GP11

I/O

12t

General purpose I/O port 1 bit 1. (CR2A bit 6 = 1)

(IRQIN2)

Alternate Function from GP11: Interrupt channel input.

KBRST

I/O

12t

W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default)

GP12

I/O

12t

General purpose I/O port 1 bit 2. (CR2A bit 7 = 1)

(WDTO)

Alternate Function 1 from GP12 : Watchdog timer output.

KBLOCK

W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default)

GP13

I/O

16t

General purpose I/O port 1 bit 3. (CR2B bit 0 = 1)

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

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Revision 0.52

2.0 FDC FUNCTIONAL DESCRIPTION

2.1 W83977ATF FDC

The floppy disk controller of the W83977ATF integrates all of the logic required for floppy disk
control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to
compatible values. The FIFO provides better system performance in multi-master systems. The
digital data separator supports up to 2 M bits/sec data rate.

The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.

2.1.1 AT interface

The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.

2.1.2 FIFO (Data)

The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.

The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:

THRESHOLD #

(1/DATA/RATE) *8 - 1.5

S = DELAY

FIFO THRESHOLD

MAXIMUM DELAY TO SERVICING AT 500K BPS

Data Rate

1 Byte

S - 1.5

S = 14.5

2 Byte

S - 1.5

S = 30.5

8 Byte

S - 1.5

S = 6.5

15 Byte

S - 1.5

S = 238.5

FIFO THRESHOLD

MAXIMUM DELAY TO SERVICING AT 1M BPS

Data Rate

1 Byte

S - 1.5

S = 6.5

2 Byte

S - 1.5

S = 14.5

8 Byte

S - 1.5

S = 62.5

15 Byte

S - 1.5

S = 118.5

W83977ATF

PRELIMINARY

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Revision 0.52

At the start of a command the FIFO is always disabled

and command parameters must be sent

based upon the RQM and DIO bit settings in the main status register. When the FDC enters the
command execution phase,

it clears the FIFO of any data to ensure that invalid data are not

transferred.

An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating
the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and
addresses need not be valid.

Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only on DACK . This mode is only available when the FDC has been configured
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.

¡ @

2.1.3 Data Separator

The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.

The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
Ideally, the DDS circuit cycles once every 12 clock cycles. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.

2.1.4 Write Precompensation

The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.

The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.

2.1.5 Perpendicular Recording Mode

The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented
vertically. This scheme packs more data bits into the same area.

FDCs with perpendicular recording drives can read standard 3.5" floppy disks

and can also read and

write perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.

A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-21 -

Revision 0.52

2.1.6 FDC Core

The W83977ATF FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.

Command

The microprocessor issues all required information to the controller to perform a specific operation.

Execution

The controller performs the specified operation.

Result

After the operation is completed, status information and other housekeeping information is provided
to the microprocessor.

2.1.7 FDC Commands

Command Symbol Descriptions:

Cylinder number 0 - 256

Data Pattern

DIR:

Step Direction

DIR = 0, step out

DIR = 1, step in

DS0:

Disk Drive Select 0

DS1:

Disk Drive Select 1

DTL:

Data Length

EC:

Enable Count

EOT:

End of Track

EFIFO:

Enable FIFO

EIS:

Enable Implied Seek

EOT:

End of track

FIFOTHR:

FIFO Threshold

GAP:

Gap length selection

GPL:

Gap Length

Head number

HDS:

Head number select

HLT:

Head Load Time

HUT:

Head Unload Time

LOCK:

Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset

MFM:

MFM or FM Mode

MT:

Multitrack

The number of data bytes written in a sector

NCN:

New Cylinder Number

ND:

Non-DMA Mode

OW:

Overwritten

PCN:

Present Cylinder Number

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-22-

Revision 0.52

POLL:

Polling Disable

PRETRK:

Precompensation Start Track Number

Record

RCN:

Relative Cylinder Number

R/W:

Read/Write

SC:

Sector/per cylinder

SK:

Skip deleted data address mark

SRT:

Step Rate Time

ST0:

Status Register 0

ST1:

Status Register 1

ST2:

Status Register 2

ST3:

Status Register 3

WG:

Write gate alters timing of WE

(1) Read Data

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

MT MFM SK 0 0 1 1 0

Command codes

0 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior
to command execution

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution

Data transfer between the
FDD and system

Result

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after
command execution

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Revision 0.52

(2) Read Deleted Data

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

MT MFM SK 0 1 1 0 0

Command codes

0 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior
to command execution

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution

Data transfer between the
FDD and system

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after
command execution

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PRELIMINARY

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Revision 0.52

(3) Read A Track

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 MFM 0 0 0 0 1 0

Command codes

0 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior
to command execution

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution

Data transfer between the
FDD and system; FDD
reads contents of all
cylinders from index hole to
EOT

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after
command execution

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PRELIMINARY

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Revision 0.52

(4) Read ID

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 MFM 0 0 1 0 1 0

Command codes

0 0 0 0 0 HDS DS1 DS0

Execution

The first correct ID
information on the cylinder
is stored in Data Register

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Disk status after the
command has been
completed

(5) Verify

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

MT MFM SK 1 0 1 1 0

Command codes

EC 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior
to command execution

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL/SC -------------------

Execution

No data transfer takes
place

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after
command execution

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PRELIMINARY

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Revision 0.52

(6) Version

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 1 0 0 0 0

Command code

Result

1 0 0 1 0 0 0 0

Enhanced controller

(7) Write Data

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

MT MFM 0 0 0 1 0 1

Command codes

0 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior
to Command execution

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution

Data transfer between the
FDD and system

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
Command execution

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after
Command execution

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PRELIMINARY

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Revision 0.52

(8) Write Deleted Data

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

MT MFM 0 0 1 0 0 1

Command codes

0 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior
to command execution

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution

Data transfer between the
FDD and system

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after
command execution

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Revision 0.52

(9) Format A Track

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 MFM 0 0 1 1 0 1

Command codes

0 0 0 0 0 HDS DS1 DS0

---------------------- N ------------------------

--------------------- SC -----------------------

Bytes/Sector

Sectors/Cylinder

--------------------- GPL ---------------------

---------------------- D ------------------------

Gap 3

Filler Byte

Execution
for Each
Sector
Repeat:

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Input Sector Parameters

Result

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after
command execution

R
R

---------------- Undefined -------------------

(10) Recalibrate

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 0 0 1 1 1

Command codes

0 0 0 0 0 0 DS1 DS0

Execution

Head retracted to Track 0
Interrupt

(11) Sense Interrupt Status

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 0 1 0 0 0

Command code

Result

---------------- ST0 -------------------------

---------------- PCN -------------------------

Status information at the end
of each seek operation

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PRELIMINARY

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Revision 0.52

(12) Specify

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 0 0 0 1 1

Command codes

| ---------SRT ----------- | --------- HUT ---------- |

|------------ HLT ----------------------------------| ND

(13) Seek

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 0 1 1 1 1

Command codes

0 0 0 0 0 HDS DS1 DS0

-------------------- NCN -----------------------

Execution

Head positioned over proper
cylinder on diskette

(14) Configure

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 1 0 0 1 1

Configure information

0 0 0 0 0 0 0 0

0 EIS EFIFO POLL | ------ FIFOTHR ----|

| --------------------PRETRK ----------------------- |

Execution

Internal registers written

(15) Relative Seek

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

1 DIR 0 0 1 1 1 1

Command codes

0 0 0 0 0 HDS DS1 DS0

| -------------------- RCN ---------------------------- |

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-30-

Revision 0.52

(16) Dumpreg

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 0 1 1 1 0

Registers placed in FIFO

Result

----------------------- PCN-Drive 0--------------------

----------------------- PCN-Drive 1 -------------------

----------------------- PCN-Drive 2--------------------

----------------------- PCN-Drive 3 -------------------

--------SRT ------------------ | --------- HUT --------

----------- HLT -----------------------------------| ND

------------------------ SC/EOT ----------------------

LOCK 0 D3 D2 D1 D0 GAP WG

0 EIS EFIFO POLL | ------ FIFOTHR --------

-----------------------PRETRK -------------------------

(17) Perpendicular Mode

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 1 0 0 1 0

Command Code

OW 0 D3 D2 D1 D0 GAP WG

(18) Lock

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

LOCK 0 0 1 0 1 0 0

Command Code

Result

0 0 0 LOCK 0 0 0 0

(19) Sense Drive Status

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

0 0 0 0 0 1 0 0

Command Code

0 0 0 0 0 HDS DS1 DS0

Result

---------------- ST3 -------------------------

Status information about
disk drive

(20) Invalid

PHASE

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

------------- Invalid Codes -----------------

Invalid codes (no
operation- FDC goes to
standby state)

Result

-------------------- ST0 ----------------------

ST0 = 80H

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-31 -

Revision 0.52

2.2 Register Descriptions

There are several status, data, and control registers in W83977ATF. These registers are defined
below:

ADDRESS

REGISTER

OFFSET

READ

WRITE

base address + 0
base address + 1
base address + 2
base address + 3

SA REGISTER

SB REGISTER

TD REGISTER

DO REGISTER

TD REGISTER

base address + 4

MS REGISTER

DR REGISTER

base address + 5

DT (FIFO) REGISTER

base address + 7

DI REGISTER

CC REGISTER

2.2.1 Status Register A (SA Register) (Read base address + 0)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:

WP
INDEX
HEAD
TRAK0
STEP

DRV2

INIT PENDING

DIR

INIT PENDING (Bit 7):

This bit indicates the value of the floppy disk interrupt output.

DRV2 (Bit 6):

A second drive has been installed

A second drive has not been installed

STEP (Bit 5):

This bit indicates the complement of STEP output.

TRAK0 (Bit 4):

This bit indicates the value of TRAK0 input.

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Revision 0.52

HEAD (Bit 3):

This bit indicates the value of HEAD output.

side 1

side 0

INDEX (Bit 2):

This bit indicates the complement of INDEX output.

WP (Bit 1):

disk is not write-protected

disk is write-protected

DIR (Bit 0)

This bit indicates the direction of head movement.

inward direction

outward direction

2.2.2 Status Register B (SB Register) (Read base address + 1)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:

MOT EN A

RDATA Toggle

WDATA Toggle

Drive SEL0

MOT EN B

Drive SEL0 (Bit 5):

This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).

WDATA Toggle (Bit 4):

This bit changes state at every rising edge of the WD output pin.

RDATA Toggle (Bit 3):

This bit changes state at every rising edge of the RDATA output pin.

WE (Bit 2):

This bit indicates the complement of the WE output pin.

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Revision 0.52

MOT EN B (Bit 1)

This bit indicates the complement of the MOB output pin.

MOT EN A (Bit 0)

This bit indicates the complement of the MOA output pin.

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

DSC
DSD
WE F/F
RDATA F/F

DSA

DSB
DRV2

WD F/F

DRV2 (Bit 7):

0 A second drive has been installed

1 A second drive has not been installed

DSB (Bit 6):

This bit indicates the status of DSB output pin.

DSA (Bit 5):

This bit indicates the status of DSA output pin.

WD F/F(Bit 4):

This bit indicates the complement of the latched WD output pin at every rising edge of the WD
output pin.

RDATA F/F(Bit 3):

This bit indicates the complement of the latched RDATA output pin .

WE F/F (Bit 2):

This bit indicates the complement of latched WE output pin.

DSD (Bit 1):
0 Drive D has been selected
1 Drive D has not been selected

DSC (Bit 0):
0 Drive C has been selected
1 Drive C has not been selected

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2.2.3 Digital Output Register (DO Register) (Write base address + 2)

The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions
are as follows:

1-0

Drive Select: 00 select drive A

01 select drive B
10 select drive C
11 select drive D

Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high

2.2.4 Tape Drive Register (TD Register) (Read base address + 3)

This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are
as follows:

Tape sel 0

Tape sel 1

If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:

Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1

Tape Sel 0

Tape Sel 1

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Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.

Drive type ID1 Drive type ID0 (Bit 5, 4):

These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive
selected in the DO REGISTER.

Floppy Boot drive 1, 0 (Bit 3, 2):

These two bits reflect the value of CR8 bit 1, 0.

Tape Sel 1, Tape Sel 0 (Bit 1, 0):

These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.

TAPE SEL 1

TAPE SEL 0

DRIVE SELECTED

None

2.2.5 Main Status Register (MS Register) (Read base address + 4)

The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:

FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.

FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.

FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.

FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.

2.2.6 Data Rate Register (DR Register) (Write base address + 4)

The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of
the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and
not by the DR REGISTER. The real data rate is determined by the most recent write to either of the
DR REGISTER or CC REGISTER.

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DRATE1 DRATE0 (Bit 1, 0):

These two bits select the data rate of the FDC and reduced write current control.

00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1

01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0

10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0

11 1 MB/S (MFM), Illegal (FM), RWC = 1

The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRT1 and DRT0 bits

which are two of the Configure Register CRF4 or CRF5

bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for
individual data rates setting.

2.2.7 FIFO Register (R/W base address + 5)

The Data Register consists of four status registers in a stack

with only one register presented to the

data bus at a time. This register stores data, commands, and parameters and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after
a command. In the W83977ATF, this register defaults to FIFO disabled mode after reset. The FIFO
can change its value and enable its operation through the CONFIGURE command.

Status Register 0 (ST0)

7-6

1-0

US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected

HD Head address:
1 Head selected
0 Head selected

NR Not Ready:

1 Drive is not ready
0 Drive is ready

EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error

SE Seek end:
1 seek end
0 seek error

IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command execution

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Status Register 1 (ST1)

Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.

NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.

ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.

DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.

Not used. This bit is always 0.

EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.

Status Register 2 (ST2)

BC (Bad Cylinder)

MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error

1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)

1 If the FDC detects a CRC error in the data field

0 No error
CM (Control Mark)
1 During execution of the read data or scan command

0 No error

Not used. This bit is always 0

Status Register 3 (ST3)

US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0

RY Ready

WP Write Protected
FT Fault

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2.2.8 Digital Input Register (DI Register) (Read base address + 7)

The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or
AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of

DSKCHG

while other bits of the data bus remain in tri-state. Bit definitions are as follows:

Reserved for the hard disk controller
During a read of this register, these bits are in tri-state

DSKCHG

In the PS/2 mode, the bit definitions are as follows:

HIGH DENS
DRATE0

DRATE1

DSKCHG

DSKCHG (Bit 7):

This bit indicates the complement of the DSKCHG input.

Bit 6-3: These bits are always a logic 1 during a read.

DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.

HIGH DENS (Bit 0):
0 500 KB/S or 1 MB/S data rate (high density FDD)
1 250 KB/S or 300 KB/S data rate

In the PS/2 Model 30 mode, the bit definitions are as follows:

DRATE0

DRATE1

DSKCHG

NOPREC
DMAEN

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DSKCHG (Bit 7):

This bit indicates the status of DSKCHG input.

Bit 6-4: These bits are always a logic 1 during a read.

DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.

NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.

DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.

2.2.9 Configuration Control Register (CC Register) (Write base address + 7)

This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:

DRATE0
DRATE1

X: Reserved

Bit 7-2: Reserved. These bits should be set to 0.

DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:

DRATE0

DRATE1

NOPREC

Reserved

Bit 7-3: Reserved. These bits should be set to 0.

NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.

DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.

W83977ATF Data Sheet Revision History

Pages

Dates

Version

Version
on Web

Main Contents

n.a.

08/25/97

0.50

First published.

53,54,58,63,64,65,
69,138.1,139

11/17/97

0.51

1,2,3,20,45,53,63,
65,99,103,150

04/01/98

0.52

Typo correction and data calibrated

112

05/14/98

0.53

spec. revision; configuration register
programming method.

Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.

W83977ATF

WINBOND I/O

Publication Release Date:April 1998

-I -

Preliminary Revision 0.52

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................1

FEATURES ..........................................................................................................................2

PIN CONFIGURATION......................................................................................................5

1.0 PIN DESCRIPTION.....................................................................................................6

1.1 HOST INTERFACE...................................................................................................................................6

1.2 GENERAL PURPOSE I/O PORT...............................................................................................................9

1.3 SERIAL PORT INTERFACE...................................................................................................................10

1.4 INFRARED INTERFACE........................................................................................................................11

1.5 MULTI-MODE PARALLEL PORT .........................................................................................................11

1.6 FDC INTERFACE ...................................................................................................................................16

1.7 KBC INTERFACE...................................................................................................................................17

1.8 POWER PINS ..........................................................................................................................................18

1.9 ACPI INTERFACE ..................................................................................................................................18

2.0 FDC FUNCTIONAL DESCRIPTION........................................................................19

2.1 W83977ATF FDC....................................................................................................................................19

2.1.1 AT interface.......................................................................................................................................19
2.1.2 FIFO (Data) ......................................................................................................................................19
2.1.3 Data Separator..................................................................................................................................20
2.1.4 Write Precompensation......................................................................................................................20
2.1.5 Perpendicular Recording Mode .........................................................................................................20
2.1.6 FDC Core..........................................................................................................................................21
2.1.7 FDC Commands ................................................................................................................................21

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2.2 REGISTER DESCRIPTIONS...................................................................................................................31

2.2.1 Status Register A (SA Register) (Read base address + 0) ...................................................................31
2.2.2 Status Register B (SB Register) (Read base address + 1) ...................................................................33
2.2.3 Digital Output Register (DO Register) (Write base address + 2)........................................................35
2.2.4 Tape Drive Register (TD Register) (Read base address + 3) ..............................................................35
2.2.5 Main Status Register (MS Register) (Read base address + 4).............................................................36
2.2.6 Data Rate Register (DR Register) (Write base address + 4)...............................................................36
2.2.7 FIFO Register (R/W base address + 5) ..............................................................................................38
2.2.8 Digital Input Register (DI Register) (Read base address + 7) ............................................................40
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) ............................................41

3.0 UART PORT.................................................................................................................42

3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ............................42

3.2 REGISTER ADDRESS .............................................................................................................................42

3.2.1 UART Control Register (UCR) (Read/Write).......................................................................................42
3.2.2 UART Status Register (USR) (Read/Write)..........................................................................................44
3.2.3 Handshake Control Register (HCR) (Read/Write) ...............................................................................45
3.2.4 Handshake Status Register (HSR) (Read/Write) ..................................................................................46
3.2.5 UART FIFO Control Register (UFR) (Write only)...............................................................................47
3.2.6 Interrupt Status Register (ISR) (Read only) .........................................................................................48
3.2.7 Interrupt Control Register (ICR) (Read/Write)....................................................................................49
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)...................................................................49
3.2.9 User-defined Register (UDR) (Read/Write) .........................................................................................50

4.0 INFRARED (IR) PORT ..............................................................................................51

4.1 IR REGISTER DESCRIPTION ................................................................................................................51

4.2 SET0-LEGACY/ADVANCED IR CONTROL AND STATUS REGISTERS............................................52

4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) .....................................52
4.2.2 Set0.Reg1 - Interrupt Control Register (ICR).....................................................................................53
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR).......................................54
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): .......................................................57
4.2.5 Set0.Reg4 - Handshake Control Register (HCR) ................................................................................58
4.2.6 Set0.Reg5 - IR Status Register (USR).................................................................................................60
4.2.7 Set0.Reg6 - Reserved.........................................................................................................................60
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR) ..............................................................................61

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4.3 SET1 - LEGACY BAUD RATE DIVISOR REGISTER ...........................................................................62

4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ..........................................................................62
4.3.2 Set1.Reg 2~7 .....................................................................................................................................63

4.4 SET2 - INTERRUPT STATUS OR IR FIFO CONTROL REGISTER (ISR/UFR).....................................63

4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) .............................................................63
4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)..............................................................................63
4.4.3 Reg3 - Sets Select Register (SSR).......................................................................................................64
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)..............................................................................65
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ...................................................................67
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only)........................................................................67

4.5 SET3 - VERSION ID AND MAPPED CONTROL REGISTERS..............................................................67

4.5.1 Reg0 - Advanced IR ID (AUID) .........................................................................................................67
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR) ................................................................................68
4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR) .......................................................................68
4.5.4. Reg3 - Sets Select Register (SSR)......................................................................................................68

4.6 SET4 - TX/RX/TIMER COUNTER REGISTERS AND IR CONTROL REGISTERS. .............................68

4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)..........................................................................69
4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) ......................................................................................69
4.6.3 Set4.Reg3 - Set Select Register (SSR).................................................................................................69
4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) ...............................................................70
4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) ...................................................................70

4.7 SET 5 - FLOW CONTROL AND IR CONTROL AND FRAME STATUS FIFO REGISTERS ................70

4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)............................71
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) ........................................................................71
4.7.3 Set5.Reg3 - Sets Select Register (SSR) ...............................................................................................71
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1).........................................................................72
4.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO).............................................................................72
4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU) .....73

4.8 SET6 - IR PHYSICAL LAYER CONTROL REGISTERS........................................................................74

4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2).......................................................................74
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width ..........................................................................75
4.8.3 Set6.Reg2 - SIR Pulse Width..............................................................................................................75
4.8.4 Set6.Reg3 - Set Select Register ..........................................................................................................76
4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) .............................................76

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4.9 SET7 - REMOTE CONTROL AND IR MODULE SELECTION REGISTERS ........................................77

4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC)................................................................77
4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC)............................................................79
4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)..................................................................80
4.9.4 Set7.Reg3 - Sets Select Register (SSR) ...............................................................................................81
4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) ...........................................................81
4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) ...........................................................82
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) ...........................................................82
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)..................................................................83

5.0 PARALLEL PORT.....................................................................................................84

5.1 PRINTER INTERFACE LOGIC ..............................................................................................................84

5.2 ENHANCED PARALLEL PORT (EPP)...................................................................................................85

5.2.1 Data Swapper ....................................................................................................................................86
5.2.2 Printer Status Buffer..........................................................................................................................86
5.2.3 Printer Control Latch and Printer Control Swapper ..........................................................................87
5.2.4 EPP Address Port..............................................................................................................................87
5.2.5 EPP Data Port 0-3 ............................................................................................................................88
5.2.6 Bit Map of Parallel Port and EPP Registers ......................................................................................88
5.2.7 EPP Pin Descriptions ........................................................................................................................89
5.2.8 EPP Operation ..................................................................................................................................89

5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ........................................................................90

5.3.1 ECP Register and Mode Definitions ..................................................................................................90
5.3.2 Data and ecpAFifo Port.....................................................................................................................91
5.3.3 Device Status Register (DSR).............................................................................................................91
5.3.4 Device Control Register (DCR) .........................................................................................................92
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010....................................................................................93
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011...........................................................................................93
5.3.7 tFifo (Test FIFO Mode) Mode = 110 .................................................................................................93
5.3.8 cnfgA (Configuration Register A) Mode = 111...................................................................................93
5.3.9 cnfgB (Configuration Register B) Mode = 111...................................................................................93
5.3.10 ecr (Extended Control Register) Mode = all ....................................................................................94
5.3.11 Bit Map of ECP Port Registers ........................................................................................................95
5.3.12 ECP Pin Descriptions......................................................................................................................96
5.3.13 ECP Operation ................................................................................................................................97
5.3.14 FIFO Operation...............................................................................................................................97
5.3.15 DMA Transfers ................................................................................................................................98

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5.3.16 Programmed I/O (NON-DMA) Mode ...............................................................................................98

5.4 EXTENSION FDD MODE (EXTFDD)....................................................................................................98

5.5 EXTENSION 2FDD MODE (EXT2FDD) ................................................................................................98

6.0 KEYBOARD CONTROLLER ...................................................................................99

6.1 OUTPUT BUFFER...................................................................................................................................99

6.2 INPUT BUFFER ......................................................................................................................................99

6.3 STATUS REGISTER .............................................................................................................................100

6.4 COMMANDS ........................................................................................................................................100

6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC .....................................................102

6.5.1 KB Control Register (Logic Device 5, CR-F0) .................................................................................102
6.5.2 Port 92 Control Register (Default Value = 0x24).............................................................................103

7.0 GENERAL PURPOSE I/O........................................................................................104

7.1 BASIC I/O FUNCTIONS .......................................................................................................................106

7.2 ALTERNATE I/O FUNCTIONS............................................................................................................108

7.2.1 Interrupt Steering ............................................................................................................................108
7.2.2 Watch Dog Timer Output.................................................................................................................109
7.2.3 Power LED......................................................................................................................................109
7.2.4 General Purpose Address Decoder ..................................................................................................109
7.2.5 General Purpose Write Strobe .........................................................................................................109

8.0 PLUG AND PLAY CONFIGURATION ..................................................................110

8.1 COMPATIBLE PNP ..............................................................................................................................110

8.1.1 Extended Function Registers ...........................................................................................................110
8.1.2 Extended Functions Enable Registers (EFERs)................................................................................111
8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) ................111

8.2 CONFIGURATION SEQUENCE...........................................................................................................111

9.0 ACPI REGISTERS FEATURES ..............................................................................113

9.1 SMI TO SCI/SCI TO SMI AND BUS MASTER ....................................................................................114

9.2 POWER MANAGEMENT TIMER ........................................................................................................115

9.3 ACPI REGISTERS (ACPIRS) ................................................................................................................116

9.3.1 Power Management 1 Status Register 1 (PM1STS1).........................................................................116
9.3.2 Power Management 1 Status Register 2 (PM1STS2).........................................................................117
9.3.3 Power Management 1 Enable Register 1(PM1EN1) .........................................................................118
9.3.4 Power Management 1 Enable Register 2 (PM1EN2) ........................................................................118

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9.3.5 Power Management 1 Control Register 1 (PM1CTL1) .....................................................................119
9.3.6 Power Management 1 Control Register 2 (PM1CTL2) .....................................................................119
9.3.7 Power Management 1 Control Register 3 (PM1CTL3) .....................................................................120
9.3.8 Power Management 1 Control Register 4 (PM1CTL4) .....................................................................120
9.3.9 Power Management 1 Timer 1 (PM1TMR1).....................................................................................121
9.3.10 Power Management 1 Timer 2 (PM1TMR2) ...................................................................................121
9.3.11 Power Management 1 Timer 3 (PM1TMR3) ...................................................................................122
9.3.12 Power Management 1 Timer 4 (PM1TMR4) ...................................................................................123
9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1)..................................................................123
9.3.14 General Purpose Event 0 Status Register 2 (GP0STS2)..................................................................124
9.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1) .................................................................125
9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2) .................................................................125
9.3.17 General Purpose Event 1 Status Register 1 (GP1STS1)..................................................................126
9.3.18 General Purpose Event 1 Status Register 2 (GP1STS2)..................................................................126
9.3.19 General Purpose Event 1 Enable Register 1 (GP1EN1) .................................................................127
9.3.20 General Purpose Event 1 Enable Register 2 (GP1EN2) .................................................................127
9.3.21 Bit Map Configuration Registers ...................................................................................................129

10.0 SERIAL IRQ............................................................................................................130

10.1 START FRAME...................................................................................................................................131

10.2 IRQ/DATA FRAME ............................................................................................................................131

10.3 STOP FRAME .....................................................................................................................................132

10.4 RESET AND INITIALIZATION .........................................................................................................132

11.0 CONFIGURATION REGISTER............................................................................133

11.1 CHIP (GLOBAL) CONTROL REGISTER ...........................................................................................133

11.2 LOGICAL DEVICE 0 (FDC) ...............................................................................................................137

11.3 LOGICAL DEVICE 1 (PARALLEL PORT).........................................................................................140

11.4 LOGICAL DEVICE 2 (UART A)¢).....................................................................................................141

11.5 LOGICAL DEVICE 3 (UART B) .........................................................................................................141

11.6 LOGICAL DEVICE 5 (KBC)...............................................................................................................142

11.7 LOGICAL DEVICE 6 (IR)...................................................................................................................143

11.8 LOGICAL DEVICE 7 (GP I/O PORT I)...............................................................................................144

11.9 LOGICAL DEVICE 8 (GP I/O PORT II) .............................................................................................148

11.10 LOGICAL DEVICE 9 (GP I/O PORT III) ..........................................................................................151

11.11 LOGICAL DEVICE A (ACPI) ...........................................................................................................154

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12.0 SPECIFICATIONS..................................................................................................161

12.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................................161

12.2 DC CHARACTERISTICS....................................................................................................................161

12.3 AC CHARACTERISTICS....................................................................................................................165

12.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. ................................................................165
12.3.2 UART/Parallel Port .......................................................................................................................167
12.3.3 Parallel Port Mode Parameters .....................................................................................................167
12.3.4 EPP Data or Address Read Cycle Timing Parameters ...................................................................168
12.3.5 EPP Data or Address Write Cycle Timing Parameters...................................................................169
12.3.6 Parallel Port FIFO Timing Parameters..........................................................................................170
12.3.7 ECP Parallel Port Forward Timing Parameters.............................................................................170
12.3.8 ECP Parallel Port Reverse Timing Parameters..............................................................................170
12.3.9 KBC Timing Parameters................................................................................................................171
12.3.10 GPIO Timing Parameters ............................................................................................................172

13.0 TIMING WAVEFORMS ........................................................................................173

13.1 FDC .....................................................................................................................................................173

13.2 UART/PARALLEL ..............................................................................................................................174

13.2.1 Modem Control Timing..................................................................................................................175

13.3. PARALLEL PORT..............................................................................................................................176

13.3.1 Parallel Port Timing......................................................................................................................176
13.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) .....................................................................177
13.3.3 EPP Data or Address Write Cycle (EPP Version 1.9).....................................................................178
13.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) .....................................................................179
13.3.5 EPP Data or Address Write Cycle (EPP Version 1.7).....................................................................180
13.3.6 Parallel Port FIFO Timing ............................................................................................................180
13.3.7 ECP Parallel Port Forward Timing ...............................................................................................181
13.3.8 ECP Parallel Port Reverse Timing ................................................................................................181

13.4 KBC.....................................................................................................................................................182

13.4.1 Write Cycle Timing........................................................................................................................182
13.4.2 Read Cycle Timing ........................................................................................................................182
13.4.3 Send Data to K/B...........................................................................................................................182
13.4.4 Receive Data from K/B ..................................................................................................................183
13.4.5 Input Clock....................................................................................................................................183
13.4.6 Send Data to Mouse.......................................................................................................................183
13.4.7 Receive Data from Mouse..............................................................................................................183

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13.5 GPIO WRITE TIMING DIAGRAM .....................................................................................................184

13.6 MASTER RESET (MR) TIMING ........................................................................................................184

14.0 APPLICATION CIRCUITS....................................................................................185

14.1 PARALLEL PORT EXTENSION FDD................................................................................................185

14.2 PARALLEL PORT EXTENSION 2FDD ..............................................................................................185

14.3 FOUR FDD MODE..............................................................................................................................186

15.0 ORDERING INFORMATION ...............................................................................186

16.0 HOW TO READ THE TOP MARKING ...............................................................186

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3.0 UART PORT

3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)

The UARTs are used to convert parallel data into serial format on the transmit side and

convert serial

data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use
this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore,
the UARTs also include complete modem control capability and a processor interrupt system that
may be software trailed to the computing time required to handle the communication link. The
UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART,
there are 16-byte FIFOs for both receive and transmit mode.

3.2 Register Address

3.2.1 UART Control Register (UCR) (Read/Write)

The UART

Control Register controls and defines the protocol for asynchronous data communications,

including data length, stop bit, parity, and baud rate selection.

Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)

Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary

format) from the divisor latches of the baudrate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.

Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is

affected by this bit; the transmitter is not affected.

Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,

(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.

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TABLE 3-1 UART Register Bit Map

Bit Number

+ 0

BDLAB = 0

Receiver

Buffer

Register

(Read Only)

RBR

RX Data

Bit 0

RX Data

Bit 1

RX Data

Bit 2

RX Data

Bit 3

RX Data

Bit 4

RX Data

Bit 5

RX Data

Bit 6

RX Data

Bit 7

+ 0

BDLAB = 0

Transmitter

Buffer Register

(Write Only)

TBR

TX Data

Bit 0

TX Data

Bit 1

TX Data

Bit 2

TX Data

Bit 3

TX Data

Bit 4

TX Data

Bit 5

TX Data

Bit 6

TX Data

Bit 7

+ 1

BDLAB = 0

Interrupt

Control

Register

ICR

RBR Data

Ready

Interrupt

Enable

(ERDRI)

TBR

Empty

Interrupt

Enable

(ETBREI)

USR

Interrupt

Enable

(EUSRI)

HSR

Interrupt

Enable

(EHSRI)

+ 2

Interrupt

Status

Register

(Read Only)

ISR

"0" if

Interrupt
Pending

Interrupt

Status

Bit (0)

Interrupt

Status

Bit (1)

Interrupt

Status

Bit (2)**

FIFOs

Enabled

FIFOs

Enabled

+ 2

UART FIFO

Control

Register

(Write Only)

UFR

FIFO

Enable

RCVR

FIFO

Reset

XMIT

FIFO

Reset

DMA

Mode

Select

Reserved

Reversed

Interrupt

Active Level

(LSB)

Interrupt

Active Level

(MSB)

+ 3

UART Control

Register

UCR

Data

Length

Select

Bit 0

(DLS0)

Data

Length

Select

Bit 1

(DLS1)

Multiple

Stop Bits

Enable

(MSBE)

Parity

Bit

Enable

(PBE)

Even

Parity

Enable

(EPE)

Parity

Bit Fixed

Enable

PBFE)

Set

Silence

Enable

(SSE)

Baudrate

Divisor

Latch

Access Bit

(BDLAB)

+ 4

Handshake

Control

Register

HCR

Data

Terminal

Ready
(DTR)

Request

Send

(RTS)

Loopback

Input

IRQ

Enable

Internal

Loopback

Enable

+ 5

UART Status

Register

USR

RBR Data

Ready

(RDR)

Overrun

Error

(OER)

Parity Bit

Error

(PBER)

No Stop

Bit

Error

(NSER)

Silent

Byte

Detected

(SBD)

TBR

Empty

(TBRE)

TSR

Empty

(TSRE)

RX FIFO

Error

Indication

(RFEI) **

+ 6

Handshake

Status Register

HSR

CTS

Toggling

(TCTS)

DSR

Toggling

(TDSR)

RI Falling

Edge

(FERI)

DCD

Toggling

(TDCD)

Clear

to Send

(CTS)

Data Set

Ready

(DSR)

Ring

Indicator

(RI)

Data Carrier

Detect
(DCD)

+ 7

User Defined

Register

UDR

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

+ 0

BDLAB = 1

Baudrate

Divisor Latch

Low

BLL

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

+ 1

BDLAB = 1

Baudrate

Divisor Latch

High

BHL

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.

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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit

3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.

Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT

will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.

Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or

received.

(1) If MSBE is set to a logical 0, one stop bit is sent and checked.

(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and

checked.

(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and

checked.

Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in

each serial character.

TABLE 3-2 WORD LENGTH DEFINITION

DLS1

DLS0

DATA LENGTH

5 bits

6 bits

7 bits

8 bits

3.2.2 UART Status Register (USR) (Read/Write)

This 8-bit register provides information about the status of the data transfer during communication.

RBR Data ready (RDR)

Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)

Transmitter Shift Register empty (TSRE)

RX FIFO Error Indication (RFEI)

Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic

1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO.
In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.

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Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In

16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
than

in these two cases, this bit will be reset to a logical 0.

Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be

set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU
to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO
is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.

Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full

word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit
to a logical 0.

Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550

mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.

Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In

16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.

Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next

received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in

the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.

3.2.3 Handshake Control Register (HCR) (Read/Write)

This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.

Data terminal ready (DTR)

Request to send (RTS)

Loopback RI input
IRQ enable
Internal loopback enable

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Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as

follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the

TSR.

(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR

(bit 0 of HCR)

DSR, RTS ( bit 1 of HCR)

CTS, Loopback RI input ( bit 2 of HCR)

RI and IRQ enable ( bit 3 of HCR)

DCD .

Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.

Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this

bit is internally connected to the modem control input DCD .

Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally

connected to the modem control input RI .

Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .

Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .

3.2.4 Handshake Status Register (HSR) (Read/Write)

This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.

RI falling edge (FERI)

Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)

CTS toggling (TCTS)

DSR toggling (TDSR)

DCD toggling (TDCD)

Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback

mode.

Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.

Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback

mode.

Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback

mode.

Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.

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Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read

by the CPU.

Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.

Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.

3.2.5 UART FIFO Control Register (UFR) (Write only)

This register is used to control the FIFO functions of the UART.

FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)

Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if

the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.

TABLE 3-3 FIFO TRIGGER LEVEL

BIT 7

BIT 6

RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)

Bit 4, 5: Reserved

Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if

UFR bit 0 = 1.

Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to

a logical 0 by itself after being set to a logical 1.

Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to

a logical 0 by itself after being set to a logical 1.

Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1

before other bits of UFR are programmed.

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3.2.6 Interrupt Status Register (ISR) (Read only)

This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.

0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled

Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.

Bit 5, 4: These two bits are always logic 0.

Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-

out interrupt is pending.

Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.

Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has

occurred, this bit will be set to a logical 0.

TABLE 3-4 INTERRUPT CONTROL FUNCTION

ISR

INTERRUPT SET AND FUNCTION

Bit

Interrupt
priority

Interrupt Type

Interrupt Source

Clear Interrupt

No Interrupt pending

First

UART Receive
Status

1. OER = 1 2. PBER =1

3. NSER = 1 4. SBD = 1

Read USR

Second

RBR Data Ready

1. RBR data ready

2. FIFO interrupt active level
reached

1. Read RBR

2. Read RBR until FIFO
data under active level

Second

FIFO Data Timeout

Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.

Read RBR

Third

TBR Empty

TBR empty

1. Write data into TBR

2. Read ISR (if priority is
third)

Fourth

Handshake status

1. TCTS = 1 2. TDSR = 1

3. FERI = 1 4. TDCD = 1

Read HSR

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.

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3.2.7 Interrupt Control Register (ICR) (Read/Write)

This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.

RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)

Bit 7-4: These four bits are always logic 0.

Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.

Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.

Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.

Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.

3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)

Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to

generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2

-1. The output frequency of

the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable
baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-
speed mode, the data transmission rate can be as high as 1.5M bps.

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3.2.9 User-defined Register (UDR) (Read/Write)

This is a temporary register that can be accessed and defined by the user.

TABLE 3-5 BAUD RATE TABLE

BAUD RATE FROM DIFFERENT PRE-DIVIDER

Pre-Div: 13

1.8461M Hz

Pre-Div:1.625

14.769M Hz

Pre-Div: 1.0

24M Hz

Decimal divisor used

to generate 16X

clock

Error Percentage between

desired and actual

400

650

2304

600

975

1536

110

880

1430

1047

0.18%

134.5

1076

1478.5

857

0.099%

150

1200

1950

768

300

2400

3900

384

600

4800

7800

192

1200

9600

15600

1800

14400

23400

2000

16000

26000

0.53%

2400

19200

31200

3600

28800

46800

4800

38400

62400

7200

57600

93600

9600

76800

124800

19200

153600

249600

38400

307200

499200

57600

460800

748800

115200

921600

1497600

** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.

Note. Pre-Divisor is determined by CRF0 of UART A and B.

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3.0 UART PORT

3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)

The UARTs are used to convert parallel data into serial format on the transmit side and

convert serial

3.2 Register Address

3.2.1 UART Control Register (UCR) (Read/Write)

The UART

Control Register controls and defines the protocol for asynchronous data communications,

including data length, stop bit, parity, and baud rate selection.

Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)

Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary

Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is

affected by this bit; the transmitter is not affected.

Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,

(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.

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TABLE 3-1 UART Register Bit Map

Bit Number

+ 0

BDLAB = 0

Receiver

Buffer

Register

(Read Only)

RBR

RX Data

Bit 0

RX Data

Bit 1

RX Data

Bit 2

RX Data

Bit 3

RX Data

Bit 4

RX Data

Bit 5

RX Data

Bit 6

RX Data

Bit 7

+ 0

BDLAB = 0

Transmitter

Buffer Register

(Write Only)

TBR

TX Data

Bit 0

TX Data

Bit 1

TX Data

Bit 2

TX Data

Bit 3

TX Data

Bit 4

TX Data

Bit 5

TX Data

Bit 6

TX Data

Bit 7

+ 1

BDLAB = 0

Interrupt

Control

Register

ICR

RBR Data

Ready

Interrupt

Enable

(ERDRI)

TBR

Empty

Interrupt

Enable

(ETBREI)

USR

Interrupt

Enable

(EUSRI)

HSR

Interrupt

Enable

(EHSRI)

+ 2

Interrupt

Status

Register

(Read Only)

ISR

"0" if

Interrupt
Pending

Interrupt

Status

Bit (0)

Interrupt

Status

Bit (1)

Interrupt

Status

Bit (2)**

FIFOs

Enabled

FIFOs

Enabled

+ 2

UART FIFO

Control

Register

(Write Only)

UFR

FIFO

Enable

RCVR

FIFO

Reset

XMIT

FIFO

Reset

DMA

Mode

Select

Reserved

Reversed

Interrupt

Active Level

(LSB)

Interrupt

Active Level

(MSB)

+ 3

UART Control

Register

UCR

Data

Length

Select

Bit 0

(DLS0)

Data

Length

Select

Bit 1

(DLS1)

Multiple

Stop Bits

Enable

(MSBE)

Parity

Bit

Enable

(PBE)

Even

Parity

Enable

(EPE)

Parity

Bit Fixed

Enable

PBFE)

Set

Silence

Enable

(SSE)

Baudrate

Divisor

Latch

Access Bit

(BDLAB)

+ 4

Handshake

Control

Register

HCR

Data

Terminal

Ready
(DTR)

Request

Send

(RTS)

Loopback

Input

IRQ

Enable

Internal

Loopback

Enable

+ 5

UART Status

Register

USR

RBR Data

Ready

(RDR)

Overrun

Error

(OER)

Parity Bit

Error

(PBER)

No Stop

Bit

Error

(NSER)

Silent

Byte

Detected

(SBD)

TBR

Empty

(TBRE)

TSR

Empty

(TSRE)

RX FIFO

Error

Indication

(RFEI) **

+ 6

Handshake

Status Register

HSR

CTS

Toggling

(TCTS)

DSR

Toggling

(TDSR)

RI Falling

Edge

(FERI)

DCD

Toggling

(TDCD)

Clear

to Send

(CTS)

Data Set

Ready

(DSR)

Ring

Indicator

(RI)

Data Carrier

Detect
(DCD)

+ 7

User Defined

Register

UDR

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

+ 0

BDLAB = 1

Baudrate

Divisor Latch

Low

BLL

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

+ 1

BDLAB = 1

Baudrate

Divisor Latch

High

BHL

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.

W83977ATF

PRELIMINARY

Publication Release Date: April 1998

-44 -

Revision 0.52

Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit

3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.

Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT

will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.

Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or

received.

(1) If MSBE is set to a logical 0, one stop bit is sent and checked.

(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and

checked.

(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and

checked.

Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in

each serial character.

TABLE 3-2 WORD LENGTH DEFINITION

DLS1

DLS0

DATA LENGTH

5 bits

6 bits

7 bits

8 bits

3.2.2 UART Status Register (USR) (Read/Write)

This 8-bit register provides information about the status of the data transfer during communication.

RBR Data ready (RDR)

Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)

Transmitter Shift Register empty (TSRE)

RX FIFO Error Indication (RFEI)

Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic