W83977ATF
WINBOND
I/O
W83977ATF Data Sheet Revision History
Pages Dates
Version
Version
on Web
Main Contents
1 n.a.
08/25/97 0.50
First
published.
2
53,54,58,63,64,65,
69,138.1,139
11/17/97 0.51
Register
correction
3
1,2,3,20,45,53,63,
65,99,103,150
04/01/98
0.52
A1
Typo correction and data calibrated
4 112
05/14/98 0.53
A2
spec. revision; configuration register
programming method.
5
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result in
personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
W83977ATF
Publication Release Date: October 2001
- I -
Revision 0.53
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................................................1
FEATURES............................................................................................................................................................2
PIN CONFIGURATION ......................................................................................................................................5
1.0 PIN DESCRIPTION......................................................................................................................................6
1.1 H
OST
I
NTERFACE
...............................................................................................................................................6
1.2 G
ENERAL
P
URPOSE
I/O P
ORT
............................................................................................................................9
1.3 S
ERIAL
P
ORT
I
NTERFACE
.................................................................................................................................10
1.4 I
NFRARED
I
NTERFACE
.....................................................................................................................................11
1.5 M
ULTI
-M
ODE
P
ARALLEL
P
ORT
.......................................................................................................................11
1.6 FDC I
NTERFACE
..............................................................................................................................................16
1.7 KBC I
NTERFACE
.............................................................................................................................................17
1.8 POWER PINS ................................................................................................................................................18
1.9 ACPI I
NTERFACE
............................................................................................................................................18
2.0 FDC FUNCTIONAL DESCRIPTION .......................................................................................................19
2.1 W83977ATF FDC ..........................................................................................................................................19
2.1.1 AT interface .............................................................................................................................................19
2.1.2 FIFO (Data) ............................................................................................................................................19
2.1.3 Data Separator ........................................................................................................................................20
2.1.4 Write Precompensation ...........................................................................................................................20
2.1.5 Perpendicular Recording Mode ..............................................................................................................20
2.1.6 FDC Core ................................................................................................................................................21
2.1.7 FDC Commands ......................................................................................................................................21
2.2 R
EGISTER
D
ESCRIPTIONS
.................................................................................................................................31
2.2.1 Status Register A (SA Register) (Read base address + 0) .......................................................................31
2.2.2 Status Register B (SB Register) (Read base address + 1) .......................................................................33
2.2.3 Digital Output Register (DO Register) (Write base address + 2) ...........................................................35
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)..................................................................35
2.2.5 Main Status Register (MS Register) (Read base address + 4) ................................................................36
2.2.6 Data Rate Register (DR Register) (Write base address + 4)...................................................................36
2.2.7 FIFO Register (R/W base address + 5)...................................................................................................38
2.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................................40
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)...............................................41
3.0 UART PORT.................................................................................................................................................43
3.1 U
NIVERSAL
A
SYNCHRONOUS
R
ECEIVER
/T
RANSMITTER
(UART A, UART B)...............................................43
3.2 R
EGISTER
A
DDRESS
.........................................................................................................................................43
3.2.1 UART Control Register (UCR) (Read/Write) ..........................................................................................43
3.2.2 UART Status Register (USR) (Read/Write)..............................................................................................45
3.2.3 Handshake Control Register (HCR) (Read/Write) ..................................................................................46
W83977ATF
Publication Release Date: Apr 2001
- II -
Revision 0.53
3.2.4 Handshake Status Register (HSR) (Read/Write)......................................................................................47
3.2.5 UART FIFO Control Register (UFR) (Write only)..................................................................................48
3.2.6 Interrupt Status Register (ISR) (Read only).............................................................................................49
3.2.7 Interrupt Control Register (ICR) (Read/Write) .......................................................................................50
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) .....................................................................50
3.2.9 User-defined Register (UDR) (Read/Write).............................................................................................51
4.0 INFRARED (IR) PORT...............................................................................................................................52
4.1 IR R
EGISTER
D
ESCRIPTION
.............................................................................................................................52
4.2 S
ET
0-L
EGACY
/A
DVANCED
IR C
ONTROL AND
S
TATUS
R
EGISTERS
..................................................................53
4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ........................................53
4.2.2 Set0.Reg1 - Interrupt Control Register (ICR)..........................................................................................54
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)..........................................55
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ...........................................................59
4.2.5 Set0.Reg4 - Handshake Control Register (HCR).....................................................................................59
4.2.6 Set0.Reg5 - IR Status Register (USR) ......................................................................................................61
4.2.7 Set0.Reg6 - Reserved ...............................................................................................................................62
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)...................................................................................62
4.3 S
ET
1 - L
EGACY
B
AUD
R
ATE
D
IVISOR
R
EGISTER
.............................................................................................63
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)...............................................................................63
4.3.2 Set1.Reg 2~7............................................................................................................................................64
4.4 S
ET
2 - I
NTERRUPT
S
TATUS OR
IR FIFO C
ONTROL
R
EGISTER
(ISR/UFR) .......................................................64
4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) .................................................................64
4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1) ..................................................................................64
4.4.3 Reg3 - Sets Select Register (SSR) ............................................................................................................65
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2) ..................................................................................66
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only).......................................................................68
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only) ...........................................................................68
4.5 S
ET
3 - V
ERSION
ID
AND
M
APPED
C
ONTROL
R
EGISTERS
.................................................................................68
4.5.1 Reg0 - Advanced IR ID (AUID)...............................................................................................................68
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR).....................................................................................69
4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR)...........................................................................69
4.5.4. Reg3 - Sets Select Register (SSR) ...........................................................................................................69
4.6 S
ET
4 - TX/RX/T
IMER COUNTER REGISTERS AND
IR
CONTROL REGISTERS
. .....................................................69
4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)..............................................................................70
4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL)...........................................................................................70
4.6.3 Set4.Reg3 - Set Select Register (SSR) ......................................................................................................70
4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH)...................................................................71
4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) .......................................................................71
4.7 S
ET
5 - F
LOW CONTROL AND
IR
CONTROL AND
F
RAME
S
TATUS
FIFO
REGISTERS
...........................................71
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) ..............................72
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)............................................................................72
4.7.3 Set5.Reg3 - Sets Select Register (SSR).....................................................................................................72
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1).............................................................................73
4.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO).................................................................................73
4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU)......74
4.8 S
ET
6 - IR P
HYSICAL
L
AYER
C
ONTROL
R
EGISTERS
.........................................................................................75
4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)...........................................................................75
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width ..............................................................................76
4.8.3 Set6.Reg2 - SIR Pulse Width....................................................................................................................76
4.8.4 Set6.Reg3 - Set Select Register ................................................................................................................77
W83977ATF
Publication Release Date: Apr 2001
- III -
Revision 0.53
4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU)................................................77
4.9 S
ET
7 - R
EMOTE CONTROL AND
IR
MODULE SELECTION REGISTERS
.................................................................78
4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC)....................................................................78
4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) ...............................................................80
4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)......................................................................81
4.9.4 Set7.Reg3 - Sets Select Register (SSR).....................................................................................................82
4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1)...............................................................82
4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2)...............................................................83
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3)...............................................................83
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)......................................................................84
5.0 PARALLEL PORT .....................................................................................................................................85
5.1 P
RINTER
I
NTERFACE
L
OGIC
.............................................................................................................................85
5.2 E
NHANCED
P
ARALLEL
P
ORT
(EPP) .................................................................................................................86
5.2.1 Data Swapper ..........................................................................................................................................87
5.2.2 Printer Status Buffer................................................................................................................................87
5.2.3 Printer Control Latch and Printer Control Swapper ..............................................................................88
5.2.4 EPP Address Port....................................................................................................................................88
5.2.5 EPP Data Port 0-3 ..................................................................................................................................89
5.2.6 Bit Map of Parallel Port and EPP Registers...........................................................................................89
5.2.7 EPP Pin Descriptions..............................................................................................................................90
5.2.8 EPP Operation ........................................................................................................................................90
5.3 E
XTENDED
C
APABILITIES
P
ARALLEL
(ECP) P
ORT
..........................................................................................91
5.3.1 ECP Register and Mode Definitions........................................................................................................91
5.3.2 Data and ecpAFifo Port ..........................................................................................................................92
5.3.3 Device Status Register (DSR) ..................................................................................................................92
5.3.4 Device Control Register (DCR)...............................................................................................................93
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ........................................................................................94
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ...............................................................................................94
5.3.7 tFifo (Test FIFO Mode) Mode = 110 ......................................................................................................94
5.3.8 cnfgA (Configuration Register A) Mode = 111 .......................................................................................94
5.3.9 cnfgB (Configuration Register B) Mode = 111 .......................................................................................94
5.3.10 ecr (Extended Control Register) Mode = all .........................................................................................95
5.3.11 Bit Map of ECP Port Registers..............................................................................................................97
5.3.12 ECP Pin Descriptions............................................................................................................................98
5.3.13 ECP Operation ......................................................................................................................................99
5.3.14 FIFO Operation.....................................................................................................................................99
5.3.15 DMA Transfers ....................................................................................................................................100
5.3.16 Programmed I/O (NON-DMA) Mode..................................................................................................100
5.4 E
XTENSION
FDD M
ODE
(EXTFDD).............................................................................................................100
5.5 E
XTENSION
2FDD M
ODE
(EXT2FDD).........................................................................................................100
6.0 KEYBOARD CONTROLLER..................................................................................................................101
6.1 O
UTPUT
B
UFFER
............................................................................................................................................101
6.2 I
NPUT
B
UFFER
...............................................................................................................................................101
6.3 S
TATUS
R
EGISTER
.........................................................................................................................................102
6.4 C
OMMANDS
...................................................................................................................................................102
6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL
LOGIC .......................................................104
6.5.1 KB Control Register (Logic Device 5, CR-F0)......................................................................................104
6.5.2 Port 92 Control Register (Default Value = 0x24) .................................................................................105
7.0 GENERAL PURPOSE I/O ........................................................................................................................106
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