W83977EF/CTF
WINBOND I/O
W83977EF/CTF Data Sheet Revision History
Pages
Dates
Version
Version
on Web
Main Contents
1
N.A.
06/01/98
0.40
First published.
For Beta Site customers only
2
4, 7, 49, 50, 53,
55, 90, 91
06/16/98
0.41
Data correction
3
14, 15, 16
08/17/98
0.42
Parallel port pin description
correction
4
119, 120
09/07/98
0.43
Explanation of Keyboard/Mouse
Wake-Up and ACPI function.
5
1, 2, 8, 83, 116
11/09/98
0.50
A1
Typo correction.
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All the trade marks
of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-I -
Revision A1
Table of Contents-
GENERAL DESCRIPTION..........................................................................................1
FEATURES .................................................................................................................2
PIN CONFIGURATION ...............................................................................................5
1.0 PIN DESCRIPTION..................................................................................................................... 6
1.1 HOST INTERFACE...................................................................................................................... 6
1.2 GENERAL PURPOSE I/O PORT ................................................................................................. 8
1.3 SERIAL PORT INTERFACE ........................................................................................................ 9
1.4 INFRARED INTERFACE............................................................................................................ 10
1.5 MULTI-MODE PARALLEL PORT ............................................................................................... 11
1.6 FDC INTERFACE ...................................................................................................................... 16
1.7 KBC INTERFACE ...................................................................................................................... 18
1.8 POWER PINS............................................................................................................................ 18
1.9 ACPI INTERFACE ..................................................................................................................... 18
2.0 FDC FUNCTIONAL DESCRIPTION ...................................................................19
2.1 W83977EF/CTF FDC................................................................................................................. 19
2.1.1 AT interface ......................................................................................................................... 19
2.1.2 FIFO (Data) ......................................................................................................................... 19
2.1.3 Data Separator .................................................................................................................... 20
2.1.4 Write Precompensation........................................................................................................ 20
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.6 FDC Core ............................................................................................................................ 21
2.1.7 FDC Commands .................................................................................................................. 21
2.2 REGISTER DESCRIPTIONS ..................................................................................................... 33
2.2.1 Status Register A (SA Register) (Read base address + 0) ................................................... 33
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-II -
Revision A1
2.2.2 Status Register B (SB Register) (Read base address + 1) ................................................... 35
2.2.3 Digital Output Register (DO Register) (Write base address + 2) ........................................... 37
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)................................................ 37
2.2.5 Main Status Register (MS Register) (Read base address + 4).............................................. 38
2.2.6 Data Rate Register (DR Register) (Write base address + 4)................................................. 38
2.2.7 FIFO Register (R/W base address + 5) ................................................................................ 40
2.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................ 42
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)................................ 43
3.0 UART PORT .......................................................................................................45
3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) .................... 45
3.2 REGISTER ADDRESS............................................................................................................... 45
3.2.1 UART Control Register (UCR) (Read/Write)......................................................................... 45
3.2.2 UART Status Register (USR) (Read/Write) .......................................................................... 47
3.2.3 Handshake Control Register (HCR) (Read/Write)................................................................. 48
3.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................. 49
3.2.5 UART FIFO Control Register (UFR) (Write only) .................................................................. 50
3.2.6 Interrupt Status Register (ISR) (Read only) .......................................................................... 51
3.2.7 Interrupt Control Register (ICR) (Read/Write) ....................................................................... 52
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ..................................................... 52
3.2.9 User-defined Register (UDR) (Read/Write)........................................................................... 53
4.0 INFRARED (IR) PORTS......................................................................................54
4.1 IR PORT .................................................................................................................................... 54
4.2 CIR PORT(FOR W83977CTF ONLY) ........................................................................................ 54
4.2.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)........................................................ 54
4.2.2 Bank0.Reg1 - Interrupt Control Register (ICR) ..................................................................... 54
4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR)....................................................................... 55
4.2.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) ...... 56
4.2.5 Bank0.Reg4 - CIR Control Register (CTR) ........................................................................... 57
4.2.6 Bank0.Reg5 - UART Line Status Register (USR) ................................................................ 58
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-III -
Revision A1
4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ................................................. 58
4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR).............................................................. 59
4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ........................................................... 60
4.2.10 Bank1.Reg2 - Version ID Regiister I (VID).......................................................................... 61
4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .... 61
4.2.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)................................................................. 61
4.2.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ............................................................... 61
4.3 DEMODULATION BLOCK DIAGRAM ........................................................................................ 62
5.0 PARALLEL PORT .............................................................................................63
5.1 PRINTER INTERFACE LOGIC .................................................................................................. 63
5.2 ENHANCED PARALLEL PORT (EPP) ....................................................................................... 64
5.2.1 Data Swapper..................................................................................................................... 65
5.2.2 Printer Status Buffer ............................................................................................................ 65
5.2.3 Printer Control Latch and Printer Control Swapper .............................................................. 66
5.2.4 EPP Address Port................................................................................................................ 66
5.2.5 EPP Data Port 0-3 ............................................................................................................... 67
5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................... 67
5.2.7 EPP Pin Descriptions.......................................................................................................... 68
5.2.8 EPP Operation..................................................................................................................... 68
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .............................................................. 69
5.3.1 ECP Register and Mode Definitions ..................................................................................... 69
5.3.2 Data and ecpAFifo Port........................................................................................................ 70
5.3.3 Device Status Register (DSR)............................................................................................. 70
5.3.4 Device Control Register (DCR) ............................................................................................ 71
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ....................................................................... 72
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................... 72
5.3.7 tFifo (Test FIFO Mode) Mode = 110.................................................................................... 72
5.3.8 cnfgA (Configuration Register A) Mode = 111 ..................................................................... 72
5.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................... 72
5.3.10 ecr (Extended Control Register) Mode = all ....................................................................... 73
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