WINBOND I/O
W83977F
&
W83977AF
W83977F/ AF Data Sheet Revision History
Pages
Dates
Versio
n
Versio
n
on
Web
Main Contents
1
n.a.
01/20/97
0.50
First publication
2
2,3,6,8,9,10,
122,126,128-
132,134,138,168
01/27/97
0.51
Spec. Correction; typo correction
3
117-125,127
01/30/97
0.52
Register Correction; pages rearranging.
4
9,10,120-122
02/13/97
0.53
Spec. Correction; typo correction
5
127,135,136,169
03/03/97
0.54
Spec. Correction; typo correction
6
VIII,IX,166-169
05/24/97
0.55
Add section 15.0; pages rearranging.
7
P118
7/15/97
0.56
CR24: Pin 22
Pin1
8
53,54,58,61,62,
63,65,124,125
11/17/97
0.57
Register Correction
9
1,3,11,52,91,105,
109,110,111,113,
114,115,119,124,
130,131,148
03/10/97
0.58
Typo correction and data calibrated
10
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Winbond for any damages resulting from such
improper use or sales.
W83977F/ W83977AF
PRELIMINARY
Publication Release Date:March 1998
-I -
Preliminary Revision 0.58
TABLE OF CONTENTS
1. PIN DESCRIPTION........................................................................................................6
1.1 HOST INTERFACE....................................................................................................................................6
1.2 ADVANCED POWER MANAGEMENT....................................................................................................8
1.3 SERIAL PORT INTERFACE......................................................................................................................9
1.4 INFRARED INTERFACE.........................................................................................................................10
1.5 MULTI-MODE PARALLEL PORT ..........................................................................................................11
1.6 FDC INTERFACE ....................................................................................................................................16
1.7 KBC INTERFACE....................................................................................................................................17
1.8 RTC INTERFACE ....................................................................................................................................17
1.9 POWER PINS ...........................................................................................................................................17
2. FDC FUNCTIONAL DESCRIPTION...........................................................................18
2.1 W83977F/ AF FDC ...................................................................................................................................18
2.1.1 AT interface........................................................................................................................................18
2.1.2 FIFO (Data) .......................................................................................................................................18
2.1.3 Data Separator...................................................................................................................................19
2.1.4 Write Precompensation.......................................................................................................................19
2.1.5 Perpendicular Recording Mode ..........................................................................................................19
2.1.6 FDC Core...........................................................................................................................................20
2.1.7 FDC Commands .................................................................................................................................20
2.2 REGISTER DESCRIPTIONS....................................................................................................................31
2.2.1 Status Register A (SA Register) (Read base address + 0) ....................................................................31
2.2.2 Status Register B (SB Register) (Read base address + 1) ....................................................................33
2.2.3 Digital Output Register (DO Register) (Write base address + 2).........................................................35
2.2.4 Tape Drive Register (TD Register) (Read base address + 3) ...............................................................35
2.2.5 Main Status Register (MS Register) (Read base address + 4)..............................................................36
2.2.6 Data Rate Register (DR Register) (Write base address + 4)................................................................36
2.2.7 FIFO Register (R/W base address + 5) ...............................................................................................38
2.2.8 Digital Input Register (DI Register) (Read base address + 7) .............................................................40
W83977F/ W83977AF
PRELIMINARY
Publication Release Date:March 1998
-II -
Preliminary Revision 0.58
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) .............................................42
3. UART PORT ..................................................................................................................43
3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ............................43
3.2 REGISTER ADDRESS .............................................................................................................................43
3.2.1 UART Control Register (UCR) (Read/Write).......................................................................................43
3.2.2 UART Status Register (USR) (Read/Write)..........................................................................................45
3.2.3 Handshake Control Register (HCR) (Read/Write) ...............................................................................46
3.2.4 Handshake Status Register (HSR) (Read/Write) ..................................................................................47
3.2.5 UART FIFO Control Register (UFR) (Write only)...............................................................................48
3.2.6 Interrupt Status Register (ISR) (Read only) .........................................................................................48
3.2.7 Interrupt Control Register (ICR) (Read/Write)....................................................................................49
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)...................................................................50
3.2.9 User-defined Register (UDR) (Read/Write) .........................................................................................50
4. INFRARED (IR) PORT .................................................................................................52
4.1 IR REGISTER DESCRIPTION .................................................................................................................52
4.2 SET0-LEGACY/ADVANCED IR CONTROL AND STATUS REGISTERS.............................................53
4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ......................................53
4.2.2 Set0.Reg1 - Interrupt Control Register (ICR)......................................................................................53
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)........................................54
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ........................................................57
4.2.5 Set0.Reg4 - Handshake Control Register (HCR) .................................................................................58
4.2.6 Set0.Reg5 - IR Status Register (USR)..................................................................................................59
4.2.7 Set0.Reg6 - Reserved..........................................................................................................................59
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR) ...............................................................................59
4.3 SET1 - LEGACY BAUD RATE DIVISOR REGISTER ............................................................................60
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ...........................................................................61
4.3.2 Set1.Reg 2~7 ......................................................................................................................................61
4.4 SET2 - INTERRUPT STATUS OR IR FIFO CONTROL REGISTER (ISR/UFR)......................................61
4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ..............................................................61
4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)...............................................................................61
4.4.3 Reg3 - Sets Select Register (SSR)........................................................................................................62
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)...............................................................................62
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