W89C841F/D
3-IN-1 10/100M FAST ETHERNET CONTROLLER
Publication Release Date: October 18, 2001
- 1 - Revision A3
W89C841F/D
3-IN-1 100BASE-TX/FX &
10BASE-T Ethernet Controller
W89C841F/D
- 2 -
The information described in this document is the exclusive intellectual property of Winbond
Electronics Corporation and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes of W89C841F-based system
design. Winbond assumes no responsibility for errors or omissions. All data and specifications are
subject to change without notice.
PC, AT and IBM are registered trademarks of International Business Machines, Inc. DOS and
Windows are registered trademarks of Microsoft corporation. All other trademarks mentioned in this
document are property of their respective owners.
For additional information or questions, please contact:
Winbond Electronics Corp.
W89C841F/D
Publication Release Date: October 18, 2001
- 3 - Revision A3
Table of Contents-
1. GENERAL DESCRIPTION.......................................................................................................................... 4
2. FEATURES ................................................................................................................................................. 4
3. PIN CONFIGURATIONS............................................................................................................................. 6
4. PIN DESCRIPTION..................................................................................................................................... 9
PCI Interface.............................................................................................................................................. 9
Power Management Interface ................................................................................................................. 14
BootROM/Flash and EEPROM Interface ................................................................................................ 15
Transceiver Interface............................................................................................................................... 19
LED Interface........................................................................................................................................... 20
Configuration and Test Interface ............................................................................................................. 20
Power Pins .............................................................................................................................................. 20
5. BLOCK DIAGRAM .................................................................................................................................... 23
6. SYSTEM DIAGRAM.................................................................................................................................. 24
7. FUNCTIONAL DESCRIPTION.................................................................................................................. 25
Operation Mode Configuration ................................................................................................................ 25
Direct Memory Access Function.............................................................................................................. 25
Media Access Control (MAC) Function ................................................................................................... 26
Full Duplex and Half Duplex Function ..................................................................................................... 26
Network Media Speed Function .............................................................................................................. 26
Flow Control in Full Duplex Mode............................................................................................................ 26
Priority Tagged Frame Supporting QOS.................................................................................................. 26
EEPROM Auto-load and Software Programming Function ..................................................................... 27
BootROM Read and Flash Programming Function ................................................................................. 30
MII Management Function ....................................................................................................................... 32
System Resource Configuring................................................................................................................. 32
Power Management Function.................................................................................................................. 33
8. CONFIGURATION REGISTERS .............................................................................................................. 33
Configuration Register Mapping .............................................................................................................. 34
9. FUNCTION REGISTERS .......................................................................................................................... 47
Cxx Function Registers ........................................................................................................................... 47
Dxx Function Registers ........................................................................................................................... 62
MII Management Registers ..................................................................................................................... 79
10. ELECTRICAL CHARACTERISTICS ....................................................................................................... 90
Absolute Maximum Ratings..................................................................................................................... 90
Power Supply .......................................................................................................................................... 90
DC Characteristics................................................................................................................................... 90
AC Characteristics................................................................................................................................... 91
11. PACKAGE DIMENSIONS ..................................................................................................................... 100
W89C841F: 128L QFP (14 x 20 x 2.75 mm footprint 3.2 mm) .............................................................. 100
W89C841D: 128L LQFP (14 x 20 x 1.4 mm)......................................................................................... 101
W89C841F/D
- 4 -
1. GENERAL DESCRIPTION
W89C841F is a highly integrated PCI Fast Ethernet MAC controller with embedded Ethernet
transceiver for 100BaseTX, 100BaseFX and 10BaseT. It is compliant with IEEE 802.3, 802.3u
specification. Auto cross-over function is supported on TP terminal and the network status of
W89C841F is indicated by 3 LED pins. W89C841F supports full/half duplex, asymmetrical flow control
operation compliant with IEEE 802.3x and VLAN tagged frame compliant with IEEE 802.1p.
According to different applications, W89C841F can be configured into one of 3 modes to operate by
setting the pins CONFIG[1:0] and ModeSel[2:0] after power-on reset. The 3 operational modes of
W89C841F are listed as below.
1. PCI Ethernet MAC controller with internal Ethernet PHYceiver.
2. Pure PCI Ethernet MAC Controller
3. Pure 10/100M PHYceiver
W89C841F provides a host bus interface complying with the PCI local bus specification R2.2, Mini PCI
Specification R1.0 and CardBus. W89C841F plays as a bus master role to improve network
performance and reduce the bus utilization. There are built-in 2K bytes TX FIFO and 2K bytes RX
FIFO to store data. The DMA controller handles the data transfer between the host memory and the
FIFOs. The data received from network are queued into the RX FIFO then directly moved into the host
memory through the PCI bus. On the other hand, the transmitted data are fetched from the host
memory and directly queued into the transmit FIFO. No extra on-board memory is needed for data
buffering during operation.
For PC99/2001, W89C841F implements power management function that are compliant with
Advanced Configuration and Power Interface (ACPI) specification R1.0, PCI Power Management
Interface specification R1.1 and Network Device Class Power Management Reference specification
V1.0a. W89C841F supports D3
cold
power management state if auxiliary power is detected. 3 types of
wakeup events are acceptable like link status change, Magic Packet and 5 sets of wake-up frames.
EEPROM (93C46) is supported by W89C841F to store configuration and Vital Product Data (VPD)
information. The length of VPD information is up to 64 bytes. W89C841F can access the CardBus
information Structure (CIS) information that is stored at EEPROM (93C56) or BootROM. W89C841F
also supports BootROM/Flash interface to read/write BootROM or Flash memory.
2. FEATURES
Integrated Fast Ethernet MAC controller with10/100M Ethernet transceiver in one chip
Supports MII interface for programmable single PHYceiver or single MAC controller
Complies with IEEE 802.3, 802.3u specification
Supports 10BAST-T, 100BASE-TX and 100BASE-FX
Supports auto cross-over operation
Supports half duplex and full duplex for 10/100M operation
Supports flow control for full duplex mode compliant with IEEE 802.3x
W89C841F/D
Publication Release Date: October 18, 2001
- 5 - Revision A3
Complies with IEEE802.3ac, 802.1Q for VLAN-tagged frame
Supports LED pins for network activity indication
Configurable to PCI, MiniPCI or CardBus bus interface
Supports PCI/MiniPCI bus master mode for DMA operation, fully compliant with PCI Local Bus
Specification R2.2 and Mini PCI Specification R1.0
Supports CardBus Information Structure (CIS)
Supports 25 to 33 MHz PCI clock speed
Compliant with APCI R1.0, PCI power management R1.1 and Network device Class Power
management Reference specification V1.0a
Supports power management event asserted from D3
(cold)
device state with auxiliary power existing
Supports wakeup function for Link status change, Magic Packet and 5 sets of wakeup frames
Supports Vital Product Data (VPD) data structure up to 64 Bytes
Supports 2 sets of independent embedded 2K bytes FIFO for transmit and receive
Flexible multicast address filtering modes
-
64-bit hash-table
-
All multicast and promiscuous
Supports 25 MHz crystal or oscillator as internal clock source
Provides EEPROM (93C46 or 93C56) to store configuration parameters, VPD, and CIS information
Supports 8KB to 256 KB BootROM interface for both PROM and Flash memory
3.3V powered I/Os with 5V tolerant inputs
Packaged in 128-pin PQFP for W89C841F/ LQFP for W89C841D
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