W89C840AF
Publication Release Date:October 2000
-3 - Revision 1.01
W89C840AF is a highly integrated Ethernet LAN controller for both 100BaseT and 10BaseT Ethernet.
It provides a host bus interface complying with the PCI local bus specification revision 2.1, and the MII
interface complying with the IEEE802.3u standard for easily implementing an Ethernet LAN adapter. The
built-in 2K bytes transmit FIFO and 4K bytes receive FIFO, controlled by the on-chip bus master, are designed
for improving network performance and reducing the host bus utilitzation.
The on-chip DMA controller handles the data transfer between the host memory and the FIFOs. The data
received from network are queued into the receive FIFO and then, directly moved into the host memory
through the PCI bus. On the other hand, the transmitted data are fetched from the host memory and directly
queued into the transmit FIFO. No extra on-board memory is needed for data buffering during the data
transceiving operation.
For featuring the specifications of PC97/98, W89C840AF implements power management functinos
which are compliant with Advanced Configuration and Power Interface ( ACPI) specification Rev. 1.0, PCI
Power Management Interface specification Rev. 1.0, and Network Device Class Power Management Reference
specification V1.0a as well as remote wakeup function based on the OnNow initiative and the ACPI
specification requirement of PC 97 and PC 98.
Many versatile registers, total 48 inside, including host bus control registers, direct memory
access(DMA) control registers, media access control registers(MAC), power management control/status
registers and signature identification registers, are implemented for system configuring and control. All of these
long word accessible registers perform the status report and the precisely control on the operation of transmit
and receive. It also provides an extra channel for the on-line application program to update the on-board
expansion ROM device in some specific application environment.
Features
l Complies with IEEE 802.3, 802.3u, ANSI 8802-3 and Ethernet standards
l Supports PCI bus master mode for DMA operation, fully complying with PCI 2.1 standard
l Compliant with APCI R1.0, PCI power management R1.0 and Network device Class Power
management Reference specification V1.0a
l Supports remote wakeup function
l Both half duplex and full duplex available for 10/100M operation
l Flexible data structure for host compatibility and system performance
l Supports 25 to 33 Mhz PCI clock speed
l Supports full MII management function
l Provides EEPROM and flash memory on-board programming function
l Supports both big and little endian byte ordering for descriptor and buffer
l Flexible address filtering modes
-- 64-bit hash-table and one perfect address
-- all multicast and promiscuous
l A boot ROM interface, capable of supporting up to 256KB
l Supports automatic loading configuration register
l Internal and external loopback mode for diagnostic
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