W91530N SERIES
13-MEMORY TONE/PULSE DIALER WITH SAVE,
KEYTONE, LOCK, AND HANDFREE FUNCTIONS
Publication Release Date: May 1997
- 1 -
Revision A3
GENERAL DESCRIPTION
The W91530N series are tone/pulse switchable telephone dialers with 13 memories, keytone or lock,
and handfree dialing control. These chips are fabricated using Winbond's high-performance CMOS
technology and thus offer good performance in low-voltage, low-power operations.
FEATURES
DTMF/pulse switchable dialer
Two by 32 digits redial and save memory
Three by 16 digits one-touch direct repertory memory
Ten by 16 digits two-touch indirect repertory memory
Pulse-to-tone (*/T) keypad for long distance call operation
Cascaded dialing
Uses 5
5 keyboard
Easy operation with redial, flash, pause, and */T keypads
Pause, P
T (pulse-to-tone) can be stored as a digit in memory
0 or 9 dialing inhibition pin for PABX system or long distance dialing lock out
Dialing rate (10 ppS or 20 ppS) selectable by bonding option
Minimum tone output duration: 93 mS (W91534AN: 87 mS)
Minimum intertone pause: 93 mS (W91534AN: 87 mS)
Pause time: 3.6 sec.
300 mS off-hook delay in lock mode (
DP
remains low for 300 mS while off hook)
Flash break time (73 mS, 100 mS, 300 mS, or 600 mS) selectable by keypad; pause time is 1.0 mS
Make/break ratio (2:3 or 1:2) selectable by MODE pin
Key tone output for valid keypad entry recognition
On-chip power-on reset
Uses 3.579545 MHz crystal or ceramic resonator
18 or 20-pin dual-in-line plastic package
The different dialers in the W91530N series are shown in the following table:
TYPE NO.
REPLACEMENT
TYPE NO.
PULSE
(
pp
S)
FLASH
(mS)
M/B
KEY
TONE
HANDFREE
DIALING
LOCK
PACKAGE
(PINS)
W91530N
W91530
10
600/300/73/100
Pin
Yes
-
-
18
W91531
W91530AN
W91530A
10
600/300/73/100
Pin
Yes
Yes
-
20
W91531A
W91531LN
W91531L
10
600/300/73/100
Pin
-
-
Yes
18
W91531ALN
W91531AL
10
600/300/73/100
Pin
-
Yes
Yes
20
W91532N
W91532
20
600/300/73/100
Pin
Yes
-
-
18
W91532AN
W91532A
20
600/300/73/100
Pin
Yes
Yes
-
20
W91534AN
New type
10
600/300/73/100
Pin
Yes
Yes
-
20
Note: The W91534AN is for use in France only. In this version, the pause time is not be added in pulse-to-tone function
mode.
W91530N SERIES
- 2 -
PIN CONFIGURATIONS
1
16
R3
C2
C3
C4
V
2
3
4
5
6
11
12
13
14
15
R1
R2
DD
DTMF
V
7
8
9
10
T/P MUTE
17
18
XT
C1
R4
SS
XT
DP/C5
MODE
KT
HKS
W91530N
1
18
R4
C1
C2
C3
C4
SS
V
2
3
4
5
6
13
14
15
16
17
R1
R2
R3
DD
MODE
V
7
8
9
10
11
12
DTMF
HKS
HFO
XT
T/P MUTE
HFI
19
20
DP/C5
KT
XT
W91530AN/532AN/534AN
1
16
R3
C2
C3
C4
V
2
3
4
5
6
11
12
13
14
15
R1
R2
DD
DTMF
V
7
8
9
10
T/P MUTE
17
18
XT
C1
R4
SS
XT
DP/C5
MODE
HKS
W91531LN
1
18
R4
C1
C2
C3
C4
SS
V
2
3
4
5
6
13
14
15
16
17
R1
R2
R3
DD
MODE
V
7
8
9
10
11
12
DTMF
HKS
HFO
XT
T/P MUTE
HFI
19
20
DP/C5
XT
W91531ALN
LOCK
LOCK
W91530N SERIES
Publication Release Date: May 1997
- 3 -
Revision A3
PIN DESCRIPTION
SYMBOL
18-PIN 20-PIN
I/O
FUNCTION
Column-
Row Inputs
1
-
4
&
15
-
18
1
-
4
&
17
-
20
I
The keyboard input is compatible with a standard 5 x 5
keyboard, an inexpensive single contact (Form A)
keyboard, and electronic input.
In normal operation, any single button can be pushed to
produce dual tone, pulses, or functions. Activation of two or
more buttons will result in no response except for single
tone.
XT
7
7
I
A built-in inverter provides oscillation with an inexpensive
3.579545 MHz crystal. The oscillator ceases when a
keypad input is not sensed. The crystal frequency deviation
is 0.02%.
XT
8
8
O
Crystal oscillator output pin.
T/P MUTE
9
9
O
The T/P MUTE is a conventional CMOS N-channel open
drain output.
The output transistor is switched on low level during dialing
sequence (both pulse and tone mode). Otherwise, it is
switched off.
MODE
13
15
I
Pulling mode pin to V
SS
places dialer in tone mode.
Pulling mode pin to V
DD
places dialer in pulse mode (10
ppS) with M/B ratio of 40:60 (W91532/532AN is 20 ppS).
Leaving mode pin floating places dialer in pulse mode (10
ppS) with M/B ratio of 33.3:66.7 (W91532/532AN is 20
ppS).
HKS
10
12
I
The HKS (hook switch) input is used to sense whether the
handset is on-hook or off-hook.
In on-hook state, HKS = 1: chip is in sleeping mode, no
operation.
In off-hook state, HKS = 0: chip is enabled for normal
operation.
HKS pin is pulled to V
DD
by internal resistor.
KT
5
(except
W91531LN)
5
(except
W91531ALN)
O
The key tone output is a conventional CMOS inverter. The
key tone is generated when any valid key is pressed; the
KT pin generates a 1.2 KHz square wave at 35 mS. When
no key is pressed, the KT pin remains in low state.
W91530N SERIES
- 4 -
Pin Description, continued
SYMBOL
18-PIN
20-PIN
I/O
FUNCTION
LOCK
5
(only for
W91531LN)
5
(only for
W91531ALN)
I
The function of this terminal is to prevent "0" dialing and
"9" dialing under PABX system long distance call
control. When the first key input after reset is 0 or 9, all
key inputs, including the 0 or 9 key, become invalid and
the chip generates no output. The telephone is
reinitialized by a reset.
The function of the LOCK pin is shown below:
LOCK PIN
FUNCTION
V
DD
V
SS
Floating
"0", "9" dialing inhibited
Normal dialing mode
"0" dialing inhibited
DP /
C5
11
13
O
N-channel open drain dialing pulse output.
Flash key will cause DP to be active in either tone mode
or pulse mode.
In lock mode, the DP remains low for 300 mS during off-
hook delay time.
The timing diagram for pulse mode is shown in Figure
1(a, b, c, d).
DTMF
12
14
O
During pulse dialing, this pin remains in low state
regardless of keypad input. In tone mode, it will output a
dual or single tone.
A detailed timing diagram for tone mode is shown in
Figure 2(a, b, c, d).
R1
R2
R3
R4
C1
C2
C3
Specified
697
770
852
941
1209
1336
1477
699
766
848
948
1216
1332
1472
Actual
+0.28
-0.52
-0.47
+0.74
+0.57
-0.30
-0.34
Error %
OUTPUT FREQUENCY
V
DD
, V
SS
14, 6
16, 6
I
Power input pins for the dialer chip. V
DD
is the main
power and V
SS
is the ground.
W91530N SERIES
Publication Release Date: May 1997
- 5 -
Revision A3
Pin Description, continued
SYMBOL
18-PIN
20-PIN
I/O
FUNCTION
HFI,
HFO
-
10, 11
I, O
Handfree control pins.
A low pulse on the HFI input pin toggles the handfree
control state.
Status of the handfree control state is listed in the
following table:
HOOK SW.
-
On Hook
Off Hook
On Hook
Off Hook
Off Hook
CURRENT STATE
NEXT STATE
HFO
Low
High
High
-
Low
High
INPUT
HFI
HFI
HFI
Off Hook
On Hook
On Hook
HFO
High
Low
Low
Low
Low
High
DIALING
Yes
No
Yes
Yes
No
Yes
HFI pin is pulled to V
DD
by an internal resistor.
Detailed timing diagram is shown in Figure 3.
BLOCK DIAGRAM
ROW
COLUMN
DTMF
XT
XT
HKS
MODE
RAM
COUNTER
SYSTEM CLOCK
GENERATOR
LOCATION
LATCH
D/A
ROW & COLUMN
PROGRAMMABLE
COUNTER
DATA LATCH
& DECODER
READ/WRITE
HFI
(R1 to R4, Vx)
(C1 to C4)
T/P MUTE
HFO
CONTROL
LOGIC
PULSE
CONTROL
LOGIC
KEYBOARD
INTERFACE
CONVERTER
LOCK
DP/C5
KT
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