W942504CH

16M

× 4 BANKS × 4 BIT DDR SDRAM

Publication Release Date: February 14, 2003

- 1 -

Revision A1

Table of Contents-

1. GENERAL DESCRIPTION.................................................................................................................. 3

2. FEATURES ......................................................................................................................................... 3

3. KEY PARAMETERS............................................................................................................................ 3

4. PIN CONFIGURATION ....................................................................................................................... 4

5. PIN DESCRIPTION............................................................................................................................. 5

6. BLOCK DAIAGRAM ............................................................................................................................ 6

7. ELECTRICAL CHARACTERISTICS ................................................................................................... 7

Absolute Maximum Ratings ..................................................................................................................... 7

Recommended DC Operating Conditions ............................................................................................... 7

Capacitance............................................................................................................................................. 8

Leakage and Output Buffer Characteristics............................................................................................. 8

DC Characteristics................................................................................................................................... 9

AC Characteristics and Operating Condition ......................................................................................... 10

AC Test Conditions................................................................................................................................ 11

8. OPERATION MODE.......................................................................................................................... 13

Simplified Truth Table............................................................................................................................ 13

Function Truth Table.............................................................................................................................. 14

Function Truth Table for CKE ................................................................................................................ 17

Simplified State Diagram ....................................................................................................................... 18

9. FUNCTIONAL DESCRIPTION.......................................................................................................... 19

Power Up Sequence.............................................................................................................................. 19

Command Function ............................................................................................................................... 19

Read Operation ..................................................................................................................................... 22

Write Operation...................................................................................................................................... 22

Precharge .............................................................................................................................................. 22

Burst Termination .................................................................................................................................. 22

Refresh Operation ................................................................................................................................. 23

Power Down Mode ................................................................................................................................ 23

Mode Register Operation....................................................................................................................... 23

10. TIMING WAVEFORMS ................................................................................................................... 27

Command Input Timing ......................................................................................................................... 27

Timing of the CLK Signals ..................................................................................................................... 27

Read Timing (Burst Length = 4)............................................................................................................. 28

W942504CH

- 2 -

Write Timing (Burst Length = 4)............................................................................................................. 29

Mode Register Set (MRS) Timing.......................................................................................................... 31

Extend Mode Register Set (EMRS) Timing ........................................................................................... 32

Auto Precharge Timing (Read Cycle, CL = 2) ....................................................................................... 33

Auto Precharge Timing (Write Cycle) .................................................................................................... 35

Read interrupted by Read (CL = 2, BL = 2, 4, 8) ................................................................................... 36

Burst Read Stop (BL = 8)....................................................................................................................... 36

Read Interrupted by Write & BST (BL = 8) ............................................................................................ 37

Read Interrupted by Precharge (BL = 8)................................................................................................ 37

Write Interrupted by Write (BL = 2, 4, 8) ................................................................................................ 38

Write Interrupted by Read (CL = 2, BL = 8) ........................................................................................... 38

Write Interrupted by Read (CL = 2. 5, BL = 4) ....................................................................................... 39

Write Interrupted by Precharge (BL = 8)................................................................................................ 39

2 Bank Interleave Read Operation (CL = 2, BL = 4).............................................................................. 40

4 Bank Interleave Read Operation (CL = 2, BL = 2).............................................................................. 41

4 Bank Interleave Read Operation (CL = 2, BL = 4).............................................................................. 41

Auto Refresh Cycle................................................................................................................................ 42

Active Power Down Mode Entry and Exit Timing .................................................................................. 42

Precharged Power Down Mode Entry and Exit Timing.......................................................................... 42

Self Refresh Entry and Exit Timing........................................................................................................ 43

11. PACKAGE DIMENSION.................................................................................................................. 44

TSOP 66l - 400 mil ................................................................................................................................ 44

12. VERSION HISTORY ....................................................................................................................... 45

W942504CH

Publication Release Date: February 14, 2003

- 3 -

Revision A1

1. GENERAL DESCRIPTION

W942504CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 16,777,216 words

× 4 banks × 4 bits. Using pipelined architecture and 0.13 µm

process technology, W942504CH delivers a data bandwidth of up to 286M words per second (-7). To
fully comply with the personal computer industrial standard, W942504CH is sorted into three speed
grades: -7, -75 and The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is
compliant to the DDR266/CL2.5 specification.
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and

CLK

signals cross during a transition. And Write

and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942504CH is ideal for main memory in
high performance applications.

2. FEATURES

2.5V

±0.2V Power Supply

Up to 143 MHz Clock Frequency

Double Data Rate architecture; two data transfers per clock cycle

Differential Clock Inputs (CLK and

CLK

)

DQS is edge-aligned with data for Read; center-aligned with data for Write

CAS Latency: 2 and 2.5

Burst Length: 2, 4 and 8

Auto Refresh and Self Refresh

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = 1

8K Refresh Cycles /64 mS

Interface:

SSTL-2

Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65 mm pin pitch

3. KEY PARAMETERS

SYMBOL

DESCRIPTION

MIN./MAX.

-7

-75

Clock Cycle Time

CL = 2

Min.

7.5 nS

8 nS

CL = 2.5

Min.

7 nS

7.5 nS

RAS

Active to Precharge Command Period

Min.

45 nS

Active to Ref/Active Command Period

Min.

65 nS

DD1

Operation Current (Single bank)

Max.

120 mA

DD4

BURST OPERATION CURRENT

Max.

165 mA

155 mA

DD6

Self-Refresh Current

Max.

3 mA

W942504CH

Publication Release Date: February 14, 2003

- 5 -

Revision A1

5. PIN DESCRIPTION

PIN NUMBER

PIN NAME FUNCTION

DESCRIPTION

- 32,

- 42

- A12

Address

Multiplexed pins for row and column address.
Row address: A0

- A12.

Column address: A0

- A9, A11. (A10 is used for Auto Precharge)

26,27

BS0, BS1

Bank Select

Select bank to activate during row address latch time, or bank to
read/write during column address latch time.

5, 11, 56, 62

DQ0

- DQ3

Data Input/

Output

The DQ0 DQ7 input and output data are synchronized with both
edges of DQS.

51 DQS

Data

Strobe

DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.

Chip Select

Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.

23, 22, 21

RAS , CAS ,

Command

Inputs

Command inputs (along with

) define the command being

entered.

47 DM

Write

mask

When DM is asserted

high

in burst write, the input data is

masked. DM is synchronized with both edges of DQS.

45, 46

CLK,

CLK

Differential

clock inputs

All address and control input signals are sampled on the crossing
of the positive edge of CLK and negative edge of

CLK

44 CKE

Clock

Enable

CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode, or Self Refresh mode is
entered.

49 V

REF

Reference

Voltage

REF

is reference voltage for inputs.

1, 18, 33

Power

(+2.5V)

Power for logic circuit inside DDR SDRAM.

34, 48, 66

Ground

Ground for logic circuit inside DDR SDRAM.

3, 9, 15, 55, 61

Power

(+2.5V) for

I/O buffer

Separated power from V

, used for output buffer, to improve

noise.

6, 12, 52, 58, 64

Ground for

I/O buffer

Separated ground from V

, used for output buffer, to improve

noise.

2, 4, 7, 8, 10, 13,

14, 16, 17, 19,
20, 25, 43, 50,
53, 54, 57, 59,

60, 63, 65

NC1, NC2

Connection

No connection

W942504CH

Publication Release Date: February 14, 2003

- 7 -

Revision A1

7. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER SYMBOL

RATING

UNIT

Input, Output Voltage

IN,

OUT

-0.3

- V

Q +0.3

Power Supply Voltage

DD,

-0.3

- 3.6

Operating Temperature

OPR

- 70

°C

Storage Temperature

STG

-55

- 150

°C

Soldering Temperature (10s)

SOLDER

260

°C

Power Dissipation

1 W

Short Circuit Output Current

OUT

50 mA

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

Recommended DC Operating Conditions

= 0 to 70°C)

SYMBOL PARAMETER

MIN.

TYP.

MAX.

UNIT

NOTES

Power Supply Voltage

2.3 2.5 2.7

V 2

DDQ

Power Supply Voltage (for I/O
Buffer)

2.3 2.5

V 2

REF

Input reference Voltage

0.49 x

Q 0.50

Q 0.51

V 2,

Termination Voltage (System)

REF

-0.04

REF

+0.04

V 2,

IH (DC)

Input High Voltage (DC)

REF

+0.15

Q +0.3

V 2

IL (DC)

Input Low Voltage (DC)

-0.3 -

REF

-0.15

V 2

ICK (DC)

Differential Clock DC Input Voltage

-0.3 -

Q +0.3

V 15

ID (DC)

Input Differential Voltage. CLK and

CLK

inputs (DC)

0.36 -

Q +0.6

V 13,

IH (AC)

Input High Voltage (AC)

REF

+0.31

V 2

IL (AC)

Input Low Voltage (AC)

- -

REF

-0.31

V 2

ID (AC)

Input Differential Voltage. CLK and

CLK

inputs (AC)

0.7 -

Q +0.6

V 13,

X (AC)

Differential AC input Cross Point
Voltage

Q/2 -0.2

Q/2 +0.2

V 12,

ISO (AC)

Differential Clock AC Middle Point

Q/2 -0.2

Q/2 +0.2

V 14,

Note: Undershoot Limit : V

(min.) = -0.9V with a pulse width < 5 nS

Overshoot Limit : V

(max.) = V

Q +0.9V with a pulse width < 5 nS

IH (DC)

and V

IL (DC)

are levels to maintain the current logic state.

IH (AC)

and V

IL (AC)

are levels to change to the new logic state.

W942504CH

- 8 -

Capacitance

= V

Q = 2.5V

±0.2V, f = 1 MHz, T

= 25°C, V

OUT(DC)

= V

Q/2, V

OUT (Peak to Peak)

= 0.2V)

SYM. PARAMETER MIN.

MAX.

DELTA

(MAX.)

UNIT

Input Capacitance (except for CLK pins)

2.0

3.0

0.5

CLK

Input Capacitance (CLK pins) 2.0

3.0

0.25

I/O

DQ, DQS, DM Capacitance

4.0

5.0

0.5

NC1

NC1 pin Capacitance

1.5

NC2

NC2 Pin Capacitance

4.0

5.0

Note: These parameters are periodically sampled and not 100% tested.

The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance.

The NC2 pins have Power and Ground clamp.

Leakage and Output Buffer Characteristics

SYM. PARAMETER MIN.

MAX.

UNITS

NOTES

I(L)

Input Leakage Current

(0V < V

< V

Q, All other pins not under test = 0V)

-2 2

µA

O(L)

Output Leakage Current
(Output disabled, 0V < V

OUT

< V

-5 5

µA

Output High Voltage
(Under AC test load condition)

+0.76

- V

Output Low Voltage
(Under AC test load condition)

-0.76

(DC)

Output Minimum Source DC Current

-15.2 - mA 4,

(DC)

Output Minimum Sink DC Current

Full

Strength

15.2 - mA 4,

(DC)

Output Minimum Source DC Current

-10.4 - mA 5

(DC)

Output Minimum Sink DC Current

Half

Strength

10.4 - mA 5

W942504CH

Publication Release Date: February 14, 2003

- 9 -

Revision A1

DC Characteristics

SYM. PARAMETER -7

-75

UNIT

NOTES

DD0

OPERATING CURRENT: One Bank Active-Precharge; t

= t

min; t

= t

min; DQ, DM and DQS inputs changing twice per clock cycle;

Address and control inputs changing once per clock cycle

110 110

DD1

OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2;
t

= t

min; CL=2.5; t

= t

min; I

OUT

= 0 mA; Address and control

inputs changing once per clock cycle.

120 120

DD2P

PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle;
Power down mode; CKE < V

max; t

= t

min; Vin = V

REF

for DQ,

DQS and DM

2 2

DD2F

IDLE FLOATING STANDBY CURRENT:

CS > V

min; All Banks Idle;

CKE > V

min; Address and other control inputs changing once per

clock cycle; Vin = Vref for DQ, DQS and DM

45 40

DD2N

IDLE STANDBY CURRENT: CS > V

min; All Banks Idle; CKE > V

min; t

= t

min; Address and other control inputs changing once per

clock cycle; Vin > V

min or Vin < V

max for DQ, DQS and DM

45 40

DD2Q

IDLE QUIET STANDBY CURRENT: CS > V

min; All Banks Idle; CKE

> V

min; t

= t

min; Address and other control inputs stable; Vin >

REF

for DQ, DQS and DM

40 35

DD3P

ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active;
Power down mode; CKE < V

max; t

= t

min

20 20

DD3N

ACTIVE STANDBY CURRENT: CS > V

min; CKE > V

min; One

Bank Active-Precharge; t

= t

RAS

max; t

= t

min; DQ, DM and DQS

inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle

70 65

DD4R

OPERATING CURRENT: Burst=2; Reads; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle;
CL=2.5; t

= t

min; I

OUT

=0mA

165 155

DD4W

OPERATING CURRENT: Burst=2; Write; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle;
CL=2.5; t

= t

min; DQ, DM and DQS inputs changing twice per clock

cycle

165 155

DD5

AUTO REFRESH CURRENT: t

= t

RFC

min

190

DD6

SELF REFRESH CURRENT: CKE < 0.2V

DD7

RANDOM READ CURRENT: 4 Banks Active Read with activate every
20ns, Auto-Precharge Read every 20ns; Burst=4; t

RCD

= 3; I

OUT

= 0 mA;

DQ, DM and DQS inputs changing twice per clock cycle; Address
changing once per clock cycle

270 270

DQS

RANDOM READ CURRENT Timing

RCD

CK = 10ns

(

DD7)

Bank 0
Row d

Bank 3
Row c

Bank 1
Row e

ADDRESS

Bank 0
Row d

Bank 2

Row f

Bank 3
Row q

Bank 2

Col f

READ

ACT

READ

COMMAND

READ

ACT

READ

ACT

Bank 0
Row h

ACT

Bank 0

Col d

READ

ACT

Bank 1

Col e

Bank 2

Row f

Bank 3
Row q

Bank 2

Col f

Bank 0
Row h

READ

Bank 1
Row e

Bank 3

Col c

Bank 0
Row d

W942504CH

- 10 -

AC Characteristics and Operating Condition

(Notes: 10, 12)

-70 -75

SYM. PARAMETER

MIN. MAX. MIN. MAX.

UNITS NOTES

Active to Ref/Active Command Period

RFC

Ref to Ref/Active Command Period

RAS

Active to Precharge Command Period

100000

45 100000

RCD

Active to Read/Write Command Delay Time

RAP

Active to Read with Auto Precharge Enable

CCD

Read/Write(a) to Read/Write(b) Command Period

Precharge to Active Command Period

RRD

Active(a) to Active(b) Command Period

Write Recovery Time

DAL

Auto Precharge Write Recovery + Precharge Time

CL = 2

7.5

CLK Cycle Time

CL = 2.5

7.5

Data Access Time from CLK,

CLK

-0.75 0.75 -0.75 0.75

DQSCK

DQS Output Access Time from CLK, CLK

-0.75 0.75 -0.75 0.75

DQSQ

Data Strobe Edge to Output Data Edge Skew

0.5

CLk High Level Width

0.45

0.55

0.45

0.55

CLK Low Level Width

0.45

0.55

0.45

0.55

CLK Half Period (minimum of actual t

CH,

)

Min.

)

Min.

)

DQ Output Data Hold Time from DQS

-0.75

RPRE

DQS Read Preamble Time

0.9

1.1

0.9

1.1

RPST

DQS Read Postamble Time

0.4

0.6

0.4

0.6

DQ and DM Setup Time

0.5

DQ and DM Hold Time

0.5

DIPW

DQ and DM Input Pulse Width (for each input)

1.75

DQSH

DQS Input High Pulse Width

0.35

DQSL

DQS Input Low Pulse Width

0.35

DSS

DQS Falling Edge to CLK Setup Time

0.2

DSH

DQS Falling Edge Hold Time from CLK

0.2

WPRES

Clock to DQS Write Preamble Set-up Time

WPRE

DQS Write Preamble Time

0.25

WPST

DQS Write Postamble Time

0.4

DQSS

Write Command to First DQS Latching Transition

0.75

1.25

0.75

1.25

DSSK

UDQS LDQS Skew (x 16)

-0.25

0.25

-0.25

0.25

Input Setup Time

0.9

Input Hold Time

0.9

IPW

Control & Address Input Pulse Width (for each input)

2.2

Data-out High-impedance Time from CLK, CLK

-0.75 0.75 -0.75 0.75

Data-out Low-impedance Time from CLK, CLK

-0.75 0.75 -0.75 0.75

T(SS)

SSTL Input Transition

0.5

1.5

0.5

1.5

WTR

Internal Write to Read Command Delay

XSNR

Exit Self Refresh to non-Read Command

XSRD

Exit Self Refresh to Read Command

REF

Refresh Time (8k)

MRD

Mode Register Set Cycle Time

W942504CH

Publication Release Date: February 14, 2003

- 11 -

Revision A1

AC Test Conditions

PARAMETER SYMBOL

VALUE

UNIT

Input High Voltage (AC)

REF

+ 0.31

Input Low Voltage (AC)

REF

- 0.31

Input Reference Voltage

REF

0.5 x V

DDQ

Termination Voltage

0.5 x V

DDQ

Input Signal Peak to Peak Swing

SWING

1.0

Differential Clock Input Reference Voltage

(AC) V

Input Difference Voltage. CLK and

CLK

inputs (AC)

ID(AC)

1.5

Input Signal Minimum Slew Rate

SLEW

1.0

V/nS

Output timing Measurement Reference Voltage

OTR

0.5 x V

DDQ

SWING (MAX)

min (AC)

REF

max (AC)

SLEW = (V

min (AC) - V

max (AC)) / T

Output

= 50 ohms

VTT

A.C. TEST LOAD (A)

Z = 50 ohms

output

30pF

Measurement point

Notes:

(1)

Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the
device.

(2)

All voltages are referenced to V

, V

SSQ.

(3)

Peak to peak AC noise on V

REF

may not exceed

±2% V

REF(DC).

(4) V

= 1.95V, V

= 0.35V

(5) V

= 1.9V, V

= 0.4V

(6)

The values of I

OH(DC)

is based on V

DDQ

=2.3V and V

= 1.19V.

The values of I

OL(DC)

is based on V

DDQ

=2.3V and V

= 1.11V.

(7)

These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values
of t

and t

W942504CH

- 12 -

(8) V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set

equal to V

REF

and must track variations in the DC level of V

REF

(9)

These parameters depend on the output loading. Specified values are obtained with the output open.

(10) Transition times are measured between V

min(AC) and V

max(AC)

.Transition (rise and fall) of input signals have a

fixed slope.

(11) IF the result of nominal calculation with regard to t

contains more than one decimal place, the result is rounded up to

the nearest decimal place.
(i.e., t

DQSS

= 0.75

× t

, t

= 7.5 nS, 0.75

× 7.5 ns = 5.625 ns is rounded up to 5.6 nS.)

(12) V

is the differential clock cross point voltage where input timing measurement is referenced.

(13) V

is magnitude of the difference between CLK input level and CLK input level.

(14) V

ISO

means {V

ICK

(CLK)+V

ICK

( CLK )}/2.

(15) Refer to the figure below.

CLK

ICK

ID(AC)

0 V Differential

ISO

ISO(min)

ISO(max)

(16) t

and t

DQSCK

depend on the clock jitter. These timing are measured at stable clock.

W942504CH

Publication Release Date: February 14, 2003

- 13 -

Revision A1

8. OPERATION MODE

The following table shows the operation commands.

Simplified Truth Table

SYM. COMMAND

DEVICE

STATE

CKE

N-1

CKE

(4)

BS0,

BS1

A10

A12,
A11,

A9-A0

CS RAS CAS

ACT Bank

Active

Idle

(3)

H X X V

V V L

L H H

PRE Bank

Precharge Any

(3)

H X X V L X L L H L

PREA Precharge

All

Any H X X X H X L L H L

WRIT Write

Active

(3)

H X X V

L V L

H L L

WRITA

Write with Auto
Precharge

Active

(3)

H X X V H V L H L L

READ Read

Active

(3)

H X X V L V L H L H

READA

Read with Auto
Precharge

Active

(3)

H X X V H V L H L H

MRS

Mode Register
Set

Idle H

EMRS

Extended Mode
Regiser Set

Idle H

NOP No

Operation

Any H X X X X X L H H H

BST

Burst Read Stop

Active

DSL Device

Deselect Any H X X X

X X H

X X X

AREF Auto

Refresh

Idle H H X X X X L L L H

SELF

Self Refresh Entry

Idle

H X X X

SELEX

Self Refresh Exit

Idle (Self

Refresh)

L H X X

X X

L H

H X X X

Power Down
Mode Entry

Idle/

Active

(5)

H L X X

X X

L H

H X X X

PDEX

Power Down
Mode Exit

Any

(Power

Down)

L H X X

X X

L H

WDE

Data Write Enable

Active

WDD

Data Write
Disable

Active H X H X X X X X X X

Notes

1. V = Valid X = Don't Care L = Low level H = High level
2. CKE

signal is input level when commands are issued.

CKE

n-1

signal is input level one clock cycle before the commands are issued.

3. These are state designated by the BS0, BS1 signals.
4. LDM, UDM (W942516CH)
5. Power Down Mode can not entry in the burst cycle.

W942504CH

- 14 -

Function Truth Table

(Note 1)

CURRENT

STATE

RAS

CAS

ADDRESS COMMAND

ACTION

NOTES

H X X X X

DSL

Nop

L H H X X

NOP/BST

Nop

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

BS, RA

ACT

Row activating

L L H L BS,

A10

PRE/PREA

Nop

AREF/SELF

Refresh or Self refresh

Idle

Op-Code

MRS/EMRS

Mode register accessing

H X X X X

DSL

Nop

L H H X X

NOP/BST

Nop

BS, CA, A10

READ/READAA

Begin read: Determine AP

BS, CA, A10

WRIT/WRITA

Begin write: Determine AP

L L H H BS,

ACT

ILLEGAL

L L H L BS,

A10

PRE/PREA

Precharge

L L L H X

AREF/SELF

ILLEGAL

Row Active

L L L L Op-Code MRS/EMRS

ILLEGAL

DSL

Continue burst to end

NOP

Continue burst to end

L H H L X

BST

Burst

stop

BS, CA, A10

READ/READA

Term burst, new read: Determine AP

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

BS, A10

PRE/PREA

Term burst, precharging

L L L H X

AREF/SELF

ILLEGAL

Read

L L L L Op-Code MRS/EMRS

ILLEGAL

DSL

Continue burst to end

NOP

Continue burst to end

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

Term burst, start read: Determine AP

6, 7

BS, CA, A10

WRIT/WRITA

Term burst, start read: Determine AP

L L H H BS,

ACT

ILLEGAL

BS, A10

PRE/PREA

Term burst. precharging

L L L H X

AREF/SELF

ILLEGAL

Write

L L L L Op-Code MRS/EMRS

ILLEGAL

W942504CH

Publication Release Date: February 14, 2003

- 15 -

Revision A1

Function Truth Table, continued

CURRENT

STATE

RAS

CAS

ADDRESS COMMAND

ACTION

NOTES

DSL

Continue burst to end

NOP

Continue burst to end

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

L L H L BS,

A10

PRE/PREA ILLEGAL

L L L H X

AREF/SELF ILLEGAL

Read with
Auto
Prechange

L L L L Op-Code

MRS/EMRS ILLEGAL

DSL

Continue burst to end

NOP

Continue burst to end

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

L L H L BS,

A10

PRE/PREA ILLEGAL

L L L H X

AREF/SELF ILLEGAL

Write with
Auto
Precharge

L L L L Op-Code

MRS/EMRS ILLEGAL

H X X X X

DSL

Nop-> Idle after t

L H H H X

NOP

Nop-> Idle after t

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

L L H L BS,

A10

PRE/PREA Nop-> Idle after t

L L L H X

AREF/SELF ILLEGAL

Precharging

L L L L Op-Code

MRS/EMRS ILLEGAL

H X X X X

DSL

Nop-> Row active after t

RCD

L H H H X

NOP

Nop-> Row active after t

RCD

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

L L H L BS,

A10

PRE/PREA ILLEGAL

L L L H X

AREF/SELF ILLEGAL

Row
Activating

L L L L Op-Code

MRS/EMRS ILLEGAL

W942504CH

- 16 -

Function Truth Table, continued

CURRENT

STATE

RAS

CAS

ADDRESS COMMAND

ACTION

NOTES

H X X X X

DSL

Nop->R

active after t

L H H H X

NOP

Nop->R

active after t

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

L L H L BS,A10

PRE/PREA

ILLEGAL

L L L H X

AREF/SELF

ILLEGAL

Write
Recovering

L L L L Op-Code MRS/EMRS

ILLEGAL

H X X X X

DSL

Nop->Enter precharge after t

L H H H X

NOP

Nop->Enter precharge after t

L H H L X

BST

ILLEGAL

BS, CA, A10

READ/READA

ILLEGAL

BS, CA, A10

WRIT/WRITA

ILLEGAL

L L H H BS,

ACT

ILLEGAL

L L H L BS,

A10

PRE/PREA

ILLEGAL

L L L H X

AREF/SELF

ILLEGAL

Write
Recovering
with Auto
Precharge

L L L L Op-Code MRS/EMRS

ILLEGAL

H X X X X

DSL

Nop->Idle after t

L H H H X

NOP

Nop->Idle after t

L H H L X

BST

ILLEGAL

L H L H X

READ/WRIT

ILLEGAL

L L H X X

ACT/PRE/PREA

ILLEGAL

Refreshing

L L L X X

AREF/SELF/MRS/
EMRS

ILLEGAL

H X X X X

DSL

Nop->Row after t

MRD

L H H H X

NOP

Nop->Row after t

MRD

L H H L X

BST

ILLEGAL

L H L X X

READ/WRIT

ILLEGAL

Mode
Register
Accessing

L L X X X

ACT/PRE/PREA/ARE
F/SELF/MRS/EMRS

ILLEGAL

Notes

1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state

of that bank.

4. Illegal if t

RCD

is not satisfied.

5. Illegal if t

RAS

is not satisfied.

6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don't satisfy t

Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data

W942504CH

Publication Release Date: February 14, 2003

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Revision A1

Function Truth Table for CKE

CKE

CURRENT

STATE

n-1 n

RAS

CAS

ADDRESS ACTION

NOTES

H X X X X X

INVALID

Exit Self Refresh->Idle after t

XSNR

Exit Self Refresh->Idle after t

XSNR

L H L H L X

ILLEGAL

L H L L X X

ILLEGAL

Self Refresh

Maintain Self Refresh

H X X X X X

INVALID

Exit Power down->Idle after t

Power Down

Maintain power down mode

Refer to Function Truth Table

Enter Power down

H L L L L H

Self

Refresh

H L L H L X

ILLEGAL

H L L L X X

ILLEGAL

All Banks Idle

L X X X X X

Power

down

Refer to Function Truth Table

Enter Power down

H L L L L H

ILLEGAL

H L L H L X

ILLEGAL

H L L L X X

ILLEGAL

Row Active

L X X X X X

Power

down

Any State Other
Than Listed
Above

Refer to Function Truth Table

Notes

1. Self refresh can enter only from the all banks idle state.

2. Power down can enter only from bank idle or row active state.

Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data

W942504CH

Publication Release Date: February 14, 2003

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Revision A1

9. FUNCTIONAL DESCRIPTION

Power Up Sequence

1. Apply power and attempt to CKE at a low state (

0.2V), all other inputs may be undefined

1) Apply V

before or at the same time as V

2) Apply V

Q before or at the same time as V

and V

REF

2. Start Clock and maintain stable condition for 200

µS(min).

3. After stable power and clock, apply NOP and take CKE high.
4. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
5. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.

(an additional 200 cycles(min) of clock are required for DLL Lock)

6. Issue precharge command for all banks of the device.
7. Issue two or more Auto Refresh commands.
8. Issue MRS-Initialize device operation.

(If device operation mode is set at sequence 5, sequence 8 can be skipped.)

Command Function

1. Bank Activate Command

(

RAS

= "L",

CAS

= "H",

= "H", BS0, BS1 = Bank, A0 to A12 = Row Address)

The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row
addresses are latched on A0 to A12 when this command is issued and the cell data is read out of
the sense amplifiers. The maximum time that each bank can be held in the active state is specified
as t

RAS (max)

. After this command is issued, Read or Write operation can be executed.

2. Bank Precharge Command

(

RAS

= "L",

CAS

= "H",

= "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don't

care)
The Bank Precharge command percharges the bank designated by BS. The precharged bank is
switched from the active state to the idle state.

3. Precharge All Command

(

RAS

= "L",

CAS

= "H",

= "L", BS0, BS1 = Don't care, A10 = "H", A0 to A9, A11, A12 =

Don't care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to
the idle state.

4. Write Command

(

RAS

= "H",

CAS

= "L",

= "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column

Address)
The write command performs a Write operation to the bank designated by BS. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.

W942504CH

- 20 -

5. Write with Auto Precharge Command

(

RAS

= "H",

CAS

= "L",

= "L", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column

Address)
The Write with Auto Precharge command performs the Precharge operation automatically after the
Write operation. This command must not be interrupted by any other commands.

6. Read Command

(

RAS

= "H",

CAS

= "L",

= "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column

Address)
The Read command performs a Read operation to the bank designated by BS. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and

CAS

Latency (access time from

CAS

command in a clock cycle) must be programmed in

the Mode Register at power-up prior to the Read operation.

7. Read with Auto Precharge Command

(

RAS

= "H",

CAS

= "L",

= "H", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column

Address)
The Read with Auto precharge command automatically performs the Precharge operation after the
Read operation.

1) READA

RAS (min)

- (BL/2) x t

Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command.

2) t

RCD(min)

READA < t

RAS(min)

- (BL/2) x t

Data can be read with shortest latency, but the internal Precharge operation does not begin until
after t

RAS (min)

has completed.

This command must not be interrupted by any other command.

8. Mode Register Set Command

(

RAS

= "L",

CAS

= "L",

= "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data)

The Mode Register Set command programs the values of

CAS

latency, Addressing Mode, Burst

Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.

9. Extended Mode Register Set Command

(

RAS

= "L",

CAS

= "L",

= "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data)

The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL
enable/disable, decoded by A0. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.

W942504CH

Publication Release Date: February 14, 2003

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Revision A1

10. No-Operation Command

(

RAS

= "H",

CAS

= "H",

= "H")

The No-Operation command simply performs no operation (same command as Device Deselect).

11. Burst Read Stop Command

(

RAS

= "H",

CAS

= "H",

= "L")

The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.

12. Device Deselect Command

(

= "H")

The Device Deselect command disables the command decoder so that the

RAS

CAS

and Address inputs are ignored. This command is similar to the No-Operation command.

13. Auto Refresh Command

(

RAS

= "L",

CAS

= "L",

= "H", CKE = "L", BS0, BS1, A0 to A12 = Don't care)

The Auto Refresh command is used to refresh the row address provided by the internal refresh
counter. The Refresh operation must be performed 8192 times within 64 mS. The next command
can be issued after t

REF

from the end of the Auto Refresh command. When the Auto Refresh

command is used, all banks must be in the idle state.

14. Self Refresh Entry Command

(

RAS

= "L",

CAS

= "L",

= "H", CKE = "L", BS0, BS1, A0 to A12 = Don't care)

The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self
Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh
operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self
Refresh Exit command). During self refresh, DLLl is disable.

15. Self Refresh Exit Command

(CKE = "H",

= "H" or CKE = "H",

RAS

= "H",

CAS

= "H")

This command is used to exit from Self Refresh mode. Any subsequent commands can be issued
after t

XSNR

XSRD

for Read Command) from the end of this command.

16. Data Write Enable /Disable Command
(DM = "L/H" or LDM, UDM = "L/H")
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.

W942504CH

- 22 -

Read Operation

Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after t

RCD

from the Bank Activate command, the data is read out sequentially,

synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available
after

CAS

latency from the issuing of the Read command. The

CAS

latency must be set in the Mode

Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst
operation is terminated.
When the Read with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command cannot
be interrupted by any other commands. Refer to the diagrams for Read operation.

Write Operation

Issuing the Write command after t

RCD

from the bank activate command. The input data is latched

sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst
write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set
in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto
Precharge command cannot be interrupted by any other command for the entire burst data duration.
Refer to the diagrams for Write operation.

Precharge

There are two Commands, which perform the precharge operation (Bank Precharge and Precharge
All). When the Bank Precharge command is issued to the active bank, the bank is precharged and
then switched to the idle state. The Bank Precharge command can precharge one bank independently
of the other bank and hold the unprecharged bank in the active state. The maximum time each bank
can be held in the active state is specified as t

RAS (max)

. Therefore, each bank must be precharged

within t

RAS(max)

from the bank activate command.

The Precharge All command can be used to precharge all banks simultaneously. Even if banks are
not in the active state, the Precharge All command can still be issued. In this case, the Precharge
operation is performed only for the active bank and the precharge bank is then switched to the idle
state.

Burst Termination

When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.
When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after
clock cycle of (

CAS

latency) from the Precharge command. When the Burst Write cycle is interrupted

by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge
command is issued. In this case, the DM signal must be asserted "high": during t

to prevent writing

the invalided data to the cell array.

W942504CH

Publication Release Date: February 14, 2003

- 23 -

Revision A1

When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Refer to the diagrams for Burst termination.

Refresh Operation

Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 8192 times (rows) within 64 mS. The period between the Auto Refresh command
and the next command is specified by t

RFC

Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are
in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192
burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8us
before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh
commands, distributed auto refresh commands must be issued every 7.8

µS and the last distributed

Auto Refresh commands must be performed within 7.8us before entering the self refresh mode. After
exiting from the Self Refresh mode, the refresh operation must be performed within 7.8

µS. In Self

Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE
buffer). Refer to the diagrams for Refresh operation.

Power Down Mode

Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode
and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting
in low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking
CKE: "high" can exit this mode. When CKE goes high, a No operation command must be input at next
CLK rising edge. Refer to the diagrams for Power Down Mode.

Mode Register Operation

The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks
are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and
BS0, BS1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is divided
into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to
designate the column access sequence in a Burst cycle (3)

CAS

Latency field to set the assess time

in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a
type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL
enable/Disable mode)
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.

W942504CH

- 24 -

1. Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4, and 8 words.

A2 A1 A0 Burst

Length

0 0 0 Reserved
0 0 1 2

words

0 1 0 4

words

0 1 1 8

words

1 x x Reserved

2. Addressing Mode Select (A3)

The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both
addressing Mode support burst length 2, 4, and 8 words.

A3 Addressing

mode

0 Sequential
0 Interleave

· Address sequence of Sequential mode

A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.

Addressing Sequence of Sequential Mode

DATA

ACCESS ADDRESS

BURST LENGTH

Data 0

2 words (address bits is A0)

Data 1

n + 1

not carried from A0 to A1

Data 2

n + 2

4 words (address bit A0, A1)

Data 3

n + 3

not carried from A1 to A2

Data 4

n + 4

Data 5

n + 5

8 words(address bits A2, A1 and A0)

Data 6

n + 6

not carried from A2 to A3

Data 7

n + 7

W942504CH

Publication Release Date: February 14, 2003

- 25 -

Revision A1

· Addressing sequence of Interleave mode

A Column access is started from the inputted column address and is performed by
interleaving the address bits in the sequence shown as the following.

Address Sequence for Interleave Mode

DATA

ACCESS ADDRESS

BURST LENGTH

Data 0

A8 A7 A6 A5 A4 A3 A2 A1 A0

2 words

Data 1

A8 A7 A6 A5 A4 A3 A2 A1

Data 2

A8 A7 A6 A5 A4 A3 A2

4 words

Data 3

A8 A7 A6 A5 A4 A3 A2

Data 4

A8 A7 A6 A5 A4 A3

A1 A0

8 words

Data 5

A8 A7 A6 A5 A4 A3

Data 6

A8 A7 A6 A5 A4 A3

Data 7

A8 A7 A6 A5 A4 A3

CAS Latency field (A6 to A4)

This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of

CAS

Latency depends on the frequency of CLK.

A6 A5 A4

CAS

Latency

0 0 0 Reserved
0 0 1 Reserved

0 1 0

0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0

2.5

1 1 1 Reserved

4. DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.

W942504CH

Publication Release Date: February 14, 2003

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Revision A1

Timing Waveforms, continued

Write Timing (Burst Length = 4)

tDSH

DSS

DSH

WPRES

DQSS

DSH

DSS

Postamble

WPRE

Preamble

tDQSH

tDQSL

tWPST

DA0

DA1

DA2

DA3

WPRES

DQSS

DSH

DSS

Postamble

WPRE

Preamble

DQSH

DQSL

WPST

WPRES

DQSS

DSH

Postamble

WPRE

Preamble

DQSH

DQSL

WPST

DA0

DA1

DA2

DA3

DSSK

DQS

Input

(Data)

LDQS

DQ0~7

UDQS

DQ8~15

x4, x8 device

x16 device

ADD

CMD

CLK

WRIT

Col

DA0

DA1

DA2

DA3

DA0

DA1

DA2

DA3

DA0

DA1

DA2

DA3

DA0

DA1

DA2

DA3

Note: x16 has 2DQS's (UDQS for uper byte and LDQS for lower byte).Even if one of the 2
bytes is not used, both UDQS and LDQS must be toggled.

W942504CH

Publication Release Date: February 14, 2003

- 41 -

Revision A1

Timing Waveforms, continued

4 Bank Interleave Read Operation (CL = 2, BL = 2)

CMD

DQS

CLK

Q0a

Q1a

Q0b

Q1b

ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d

ACTa

ACTb

READAa

ACTc

READAb

ACTd

READAc

ACTa

APa

APb

RCD(a)

RAS(a)

RAS(b)

RCD(b)

CL(a)

CL(b)

Preamble

Postamble Preamble

RRD

RC(a)

RRD

RAS(c)

RAS(d)

RCD(d)

RCD(c)

RRD

4 Bank Interleave Read Operation (CL = 2, BL = 4)

CMD

DQS

CLK

ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d

ACTa

READAa

ACTb

READAb

ACTc

READAc

ACTd

READAd

ACTa

APa

APb

RCD(a)

RAS(a)

RP(a)

RAS(b)

RCD(b)

CL(a)

CL(b)

RRD

RC(a)

RRD

RAS(c)

RAS(d)

RCD(d)

RCD(c)

RRD

Q2a

Q3a

Q2b

Q3b

CL(c)

Preamble

Q0a

Q1a

Q0b

Q1b

Q0a

Q1a

CL(b)

APc

W942504CH

Publication Release Date: February 14, 2003

- 45 -

Revision A1

12. VERSION HISTORY

VERSION DATE PAGE

DESCRIPTION

Feb. 14, 2003

- Preliminary

datasheet

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

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