W981216BH
2M
4 BANKS
16 BITS SDRAM
Publication Release Date: September 20, 2001
- 1 - Revision A3
Table of Contents-
1. GENERAL DESCRIPTION ..................................................................................................................3
2. FEATURES ..........................................................................................................................................3
3. AVAILABLE PART NUMBER ..............................................................................................................3
4. PIN CONFIGURATION........................................................................................................................4
5. PIN DESCRIPTION .............................................................................................................................5
6. BLOCK DIAGRAM ...............................................................................................................................6
7. ELECRICAL CHARACTERISTICS ......................................................................................................7
Absolute Maximum Ratings ...................................................................................................................... 7
Recommended DC Operating Conditions ................................................................................................ 7
Capacitance.............................................................................................................................................. 7
AC Characteristics and Operating Condition ............................................................................................ 8
DC Characteristics.................................................................................................................................... 9
8. OPERATION MODE ..........................................................................................................................11
9. FUNCTIONAL DESCRIPTION ..........................................................................................................12
Power Up and Initialization ..................................................................................................................... 12
Programming Mode Register.................................................................................................................. 12
Bank Activate Command ........................................................................................................................ 12
Read and Write Access Modes .............................................................................................................. 12
Burst Read Command ............................................................................................................................ 13
Burst Write Command ............................................................................................................................ 13
Read Interrupted by a Read ................................................................................................................... 13
Read Interrupted by a Write.................................................................................................................... 13
Write Interrupted by a Write.................................................................................................................... 13
Write Interrupted by a Read.................................................................................................................... 13
Burst Stop Command ............................................................................................................................. 13
Addressing Sequence of Sequential Mode............................................................................................. 14
Addressing Sequence of Interleave Mode.............................................................................................. 14
Auto Pre-charge Command .................................................................................................................... 15
Pre-charge Command ............................................................................................................................ 15
Self Refresh Command .......................................................................................................................... 15
Power Down Mode ................................................................................................................................. 15
No Operation Command......................................................................................................................... 16
Deselect Command ................................................................................................................................ 16
Clock Suspend Mode.............................................................................................................................. 16
W981216BH
- 2 -
10. TIMING WAVEFORMS....................................................................................................................17
Command Input Timing .......................................................................................................................... 17
Read Timing ........................................................................................................................................... 18
Control Timing of Input/Output Data ....................................................................................................... 19
11. OPERATING TIMING EXAMPLE ....................................................................................................21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ................................................................ 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Pre-charge) .................................... 22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ................................................................ 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Pre-charge) .................................... 24
Interleaved Bank Write (Burst Length = 8) ............................................................................................. 25
Interleaved Bank Write (Burst Length = 8, Auto Pre-charge) ................................................................. 26
Page Mode Read (Burst Length = 4, CAS Latency = 3)......................................................................... 27
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ............................................................... 28
Auto Pre-charge Read (Burst Length = 4, CAS Latency = 3) ................................................................. 29
Auto Pre-charge Write (Burst Length = 4) .............................................................................................. 30
Auto Refresh Cycle................................................................................................................................. 31
Self Refresh Cycle .................................................................................................................................. 32
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ....................................................... 33
Power Down Mode ................................................................................................................................. 34
Auto Pre-charge Timing (Read Cycle).................................................................................................... 35
Auto Pre-charge Timing (Write Cycle) .................................................................................................... 36
Timing Chart of Read to Write Cycle ...................................................................................................... 37
Timing Chart of Write to Read Cycle ...................................................................................................... 37
Timing Chart of Burst Stop Cycle (Burst Stop Command)...................................................................... 38
Timing Chart of Burst Stop Cycle (Pre-charge Command)..................................................................... 38
CKE/DQM Input Timing (Write Cycle) .................................................................................................... 39
CKE/DQM Input Timing (Read Cycle) .................................................................................................... 40
Self Refresh/Power Down Mode Exit Timing.......................................................................................... 41
12. PACKAGE DIMENSION ..................................................................................................................42
54L TSOP (II)-400 mil............................................................................................................................. 42
W981216BH
Publication Release Date: September 20, 2001
- 3 - Revision A3
1. GENERAL DESCRIPTION
W981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words
4 banks
16 bits. Using pipelined architecture and 0.175
m process technology,
W981216BH delivers a data bandwidth of up to 166M words per second (-6). For different application,
W981216BH is sorted into four speed grades: -6, -7, -75, and -8H. The -7 is compliant to the 166 MHz
/CL3 specification, the -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is
compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification. For
handheld device application, we also provide a low power option, the grade of 75L, with Self Refresh
Current under 600
A, and an industrial temperature option, the grade of 75I, which is guaranteed to
support -40
C 85
C.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V
0.3V Power Supply
Up to 166 MHz Clock Frequency
2,097,152 Words
4 banks
16 bits organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Auto pre-charge and Controlled Pre-charge
4K Refresh cycles / 64 mS
Interface: LVTTL
Packaged in TSOP II 54 pin, 400 mil - 0.80
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED
MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
W981216BH-6
166 MHz/CL3
2 mA
0
C
-
70
C
W981216BH-7
PC133/CL2
2 mA
0
C
-
70
C
W981216BH-75
PC133/CL3
2 mA
0
C
-
70
C
W981216BH75L
PC133/CL3
600
A
0
C
-
70
C
W981216BH75I
PC133/CL3
600
A
-40
C
-
85
C
W981216BH-8H
PC100/CL2
2 mA
0
C
-
70
C
W981216BH
- 4 -
4. PIN CONFIGURATION
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
CC
V
CC
Q
V
CC
Q
V
SS
Q
V
SS
Q
V
CC
V
CC
V
SS
V
SS
Q
V
CC
Q
V
SS
Q
V
CC
Q
V
SS
V
SS
W981216BH
Publication Release Date: September 20, 2001
- 5 - Revision A3
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
23
-
26, 22,
29
-
35
A0
-
A11
Address
Multiplexed pins for row and column address.
Row address: A0
-
A11. Column address: A0
-
A8.
20, 21
BS0, BS1
Bank Select Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
DQ0
-
DQ15
Data Input/
Output
Multiplexed pins for data output and input.
19
CS
Chip Select Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
18
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the
operation to be executed.
17
CAS
Column Address
Strobe
Referred to RAS
16
WE
Write Enable Referred to RAS
39, 15
UDQM/
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
Clock Inputs System clock used to sample inputs on the rising edge
of clock.
37
CKE
Clock Enable CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
1, 14, 27
V
CC
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
28, 41, 54
V
SS
Ground
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
V
CC
Q
Power (+3.3V)
for I/O Buffer
Separated power from V
CC
, used for output buffers to
improve noise.
6, 12, 46, 52
V
SS
Q
Ground for I/O
Buffer
Separated ground from V
SS
, used for output buffers to
improve noise.
36, 40
NC
No Connection No connection
W981216BH
- 6 -
6. BLOCK DIAGRAM
D Q 0
DQ15
U D Q M
L D Q M
C L K
C K E
C S
R A S
C A S
W E
A 1 0
A 0
A 9
A 1 1
B S 0
B S 1
C L O C K
B U F F E R
C O M M A N D
D E C O D E R
A D D R E S S
B U F F E R
R E F R E S H
C O U N T E R
C O L U M N
C O U N T E R
C O N T R O L
SIGNAL
G E N E R A T O R
M O D E
R E G ISTER
C O L U M N D E C O D E R
SENSE AMPLIFIER
CELL ARRAY
BANK #2
C O L U M N D E C O D E R
SENSE AMPLIFIER
CELL ARRAY
BANK #0
C O L U M N D E C O D E R
SENSE AMPLIFIER
CELL ARRAY
BANK #3
D A T A C O N T R O L
CIRCUIT
D Q
BUFFER
C O L U M N D E C O D E R
SENSE AMPLIFIER
CELL ARRAY
BANK #1
Note: The cell array configuration is 4096 * 512 * 16.
D M n
R
O
W
D
E
C
O
D
E
R
R
O
W
D
E
C
O
D
E
R
R
O
W
D
E
C
O
D
E
R
R
O
W
D
E
C
O
D
E
R
W981216BH
Publication Release Date: September 20, 2001
- 7 - Revision A3
7. ELECRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
Input/Output Voltage
V
IN,
V
OUT
-0.3
-
V
CC
+0.3
V
Power Supply Voltage
V
CC
, V
CCQ
-0.3
-
4.6
V
Operating Temperature (-6/-7/-75/75L/-8H)
T
OPR
0
-
70
C
Operating Temperature (75I)
T
OPR
-40
-
85
C
Storage Temperature
T
STG
-55
-
150
C
Soldering Temperature (10s)
T
SOLDER
260
C
Power Dissipation
P
D
1
W
Short Circuit Output Current
I
OUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Recommended DC Operating Conditions
(T
A
= 0 to 70
C for -6/-7/-75/75L/-8H, T
A
= -40 to 85
C for 75I)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Power Supply Voltage
V
CC
3.0
3.3
3.6
V
Power Supply Voltage (for I/O Buffer)
V
CCQ
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
V
Input Low Voltage
V
IL
-0.3
-
0.8
V
Note: V
IH
(max) = V
CC
/ V
CCQ
+1.2V for pulse width < 5 nS
V
IL
(min) = V
SS
/ V
SSQ
-1.2V for pulse width < 5 nS
Capacitance
(V
CC
= 3.3V, f = 1 MHz, T
A
= 25
C)
PARAMETER
SYMBOL MIN.
MAX.
UNIT
Input Capacitance
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM,
CKE)
C
I
-
3.8
pf
Input Capacitance (CLK)
C
CLK
-
3.5
pf
Input/Output capacitance
C
IO
-
6.5
pf
Note: These parameters are periodically sampled and not 100% tested.
W981216BH
- 8 -
AC Characteristics and Operating Condition
(Vcc = 3.3V
0.3V, T
A
= 0 to 70
C for -6/-7/-75/75L/-8H, T
A
= -40 to 85
C for 75I ; Notes: 5, 6, 7, 8)
PARAMETER
SYM.
-6
-7
-75/75L/75I
-8H
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active
Command Period
t
RC
57
57
65
68
Active to Pre-charge Command
Period
t
RAS
42 100000 42 100000 45 100000 48 100000 nS
Active to Read/Write Command
Delay Time
t
RCD
15
15
20
20
Read/Write(a) to Read/Write(b)
Command Period
t
CCD
1
1
1
1
Cycle
Pre-charge to Active Command
Period
t
RP
15
15
20
20
Active(a) to Active(b) Command
Period
t
RRD
12
15
15
20
Write Recovery Time
CL* = 2
t
WR
7.5
7.5
10
10
CL* = 3
6
7
7.5
8
CLK Cycle Time
CL* = 2
t
CK
7.5 1000 7.5 1000
10
1000
10
1000
CL* = 3
6
1000
7
1000 7.5 1000
8
1000
CLK High Level width
t
CH
2
2.5
2.5
3
CLK Low Level width
t
CL
2
2.5
2.5
3
Access Time from
CL* = 2
t
AC
5.4
5.4
6
6
CLK
CL* = 3
5
5.4
5.4
6
nS
Output Data Hold Time
t
OH
2.75
3
3
3
Output Data High Impedance
Time
t
HZ
2.75
6
3
7
3
7.5
3
8
Output Data Low Impedance Time
t
LZ
0
0
0
0
Power Down Mode Entry Time
t
SB
0
6
0
7
0
7.5
0
8
Transition Time of CLK
(Rise and Fall)
t
T
0.5
10
0.5
10
0.5
10
0.5
10
Data-in Set-up Time
t
DS
1.5
1.5
1.5
2
Data-in Hold Time
t
DH
0.8
0.8
0.8
1
Address Set-up Time
t
AS
1.5
1.5
1.5
2
Address Hold Time
t
AH
0.8
0.8
0.8
1
CKE Set-up Time
t
CKS
1.5
1.5
1.5
2
CKE Hold Time
t
CKH
0.8
0.8
0.8
1
Command Set-up Time
t
CMS
1.5
1.5
1.5
2
Command Hold Time
t
CMH
0.8
0.8
0.8
1
Refresh Time
t
REF
64
64
64
64
mS
Mode Register Set Cycle Time
t
RSC
12
14
15
16
nS
*CL = CAS Latency
W981216BH
Publication Release Date: September 20, 2001
- 9 - Revision A3
DC Characteristics
(V
CC
= 3.3V
0.3V, T
A
= 0 to 70
C for -6/-7/-75/75L/-8H, T
A
= -40 to 85
C for 75I)
PARAMETER
SYM.
-6
-7
-75/75L/75I
-8H
UNIT NOTES
MAX.
MAX.
MAX.
MAX.
Operating Current
t
CK
= min.,
t
RC
= min.
Active pre-charge
command cycling without
burst operation
1 bank
operation
I
CC1
85
80
75
70
3
Standby Current
t
CK
= min,
CS
= V
IH
CKE = V
IH
I
CC2
45
40
35
30
3
V
IH
/
L
= V
I
(min) /V
IL
(max.)
Bank: Inactive state
CKE = V
IL
(Power Down
mode)
I
CC2P
1
1
1
1
3
Standby Current
CLK = V
IL
,
CS
= V
IH
CKE = V
IH
I
CC2S
10
10
10
10
V
IH
/
L
= V
IH
(min) /V
IL
(max)
BANK: Inactive state
CKE = V
IL
(Power down
mode)
I
CC2PS
1
1
1
1
mA
No Operating Current
t
CK
= min.,
CS
= V
IH
(min)
CKE = V
IH
I
CC3
65
60
55
50
BANK: Active state
(4 banks)
CKE = V
IL
(Power down
mode)
I
CC3P
10
10
10
10
Burst Operating Current
t
CK
= min.
Read/ Write command cycling
I
CC4
105
100
95
90
3, 4
Auto Refresh Current
t
CK
= min.
Auto refresh command cycling
I
CC5
180
170
160
150
3
Normal
(-6/-7/-75/-8H)
2
2
2
2
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
Low Power
(75L/75I)
I
CC6
-
-
0.6
-
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTES
Input Leakage Current
(0V
V
IN
V
CC
, all other pins not under test = 0V)
I
I(L)
-5
5
A
Output Leakage Current
(Output disable, 0V
V
OUT
V
CCQ
)
I
O(L)
-5
5
A
LVTTL Output
H
Level Voltage
(I
OUT
= -2 mA)
V
OH
2.4
-
V
LVTTL Output
L
Level Voltage
(I
OUT
= 2 mA)
V
OL
-
0.4
V
W981216BH
- 10 -
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.
2. All voltages are referenced to V
SS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of t
CK
and t
RC
.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the "Functional Description" section.
6. AC Testing Conditions
Output Reference Level
1.4V/1.4V
Output Load
See diagram below
Input Signal Levels
2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal
2 nS
Input Reference Level
1.4V
50 ohms
1.4 V
A C T E S T L O A D
Z = 50 ohms
Output
50 pF
7. Transition times are measured between V
IH
and V
IL
.
8. t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
W981216BH
Publication Release Date: September 20, 2001
- 11 - Revision A3
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
DEVICE
STATE
CKEN-1 CKEN DQM BS0, 1 A10 A0
-
A9
A11
CS RAS CAS
WE
Bank Active
Idle
H
x
x
v
v
v
L
L
H
H
Bank Pre-charge
Any
H
x
x
v
L
x
L
L
H
L
Pre-charge All
Any
H
x
x
x
H
x
L
L
H
L
Write
Active (3)
H
x
x
v
L
v
L
H
L
L
Write with Auto Pre-charge
Active (3)
H
x
x
v
H
v
L
H
L
L
Read
Active (3)
H
x
x
v
L
v
L
H
L
H
Read with Auto Pre-charge
Active (3)
H
x
x
v
H
v
L
H
L
H
Mode Register Set
Idle
H
x
x
v
v
v
L
L
L
L
No-operation
Any
H
x
x
x
x
x
L
H
H
H
Burst Stop
Active (4)
H
x
x
x
x
x
L
H
H
L
Device Deselect
Any
H
x
x
x
x
x
H
x
x
x
Auto Refresh
Idle
H
H
x
x
x
x
L
L
L
H
Self Refresh Entry
Idle
H
L
x
x
x
x
L
L
L
H
Self Refresh Exit
idle
(S.R.)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock Suspend Mode Entry
Active
H
L
x
x
x
x
x
x
x
x
Power Down Mode Entry
Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock Suspend Mode Exit
Active
L
H
x
x
x
x
x
x
x
x
Power Down Mode Exit
Any
(power
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Data Write/Output Enable
Active
H
x
L
x
x
x
x
x
x
x
Data Write/Output Disable
Active
H
x
H
x
x
x
x
x
x
x
Notes:
(1) v = valid x = Don't care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W981216BH
- 12 -
9. FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all Vcc and Vcc
Q
pins must be ramp up simultaneously to the specified voltage when
the input signals are held in the "NOP" state. The power up voltage must not exceed V
CC
+0.3V on
any of the input pins or Vcc supplies. After power up, an initial pause of 200
S is required followed by
a pre-charge of all banks using the pre-charge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been pre-charged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a pre-charged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this
cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to t
RSC
has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
RCD
). Once a bank has been activated it must be pre-charged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
RC
).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (t
RRD
). The maximum time that each bank can be held active is
specified as t
RAS
(max).
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by
setting RAS high and CAS low at the clock rising edge after minimum of t
RCD
delay. WE pin voltage
level defines whether the access cycle is a read operation (WE high), or a write operation (WE low).
The address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be pre-charged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and pre-charge operations between multiple banks, seamless data access operation among
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
W981216BH
Publication Release Date: September 20, 2001
- 13 - Revision A3
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
W981216BH
- 14 -
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write
operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BUST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
W981216BH
Publication Release Date: September 20, 2001
- 15 - Revision A3
Auto Pre-charge Command
If A10 is set to high when the Read or Write Command is issued, then the auto pre-charge function is
entered. During auto pre-charge, a Read Command will execute as normal with the exception that the
active bank will begin to pre-charge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto pre-charge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Pre-charge Command is prohibited during
a read or write cycle with auto pre-charge. Once the pre-charge operation has started, the bank
cannot be reactivated until the Pre-charge time (t
RP
) has been satisfied. Issue of Auto Pre-charge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is
issued, the Write with Auto Pre-charge function is initiated. The SDRAM automatically enters the pre-
charge operation one clock delay from the last burst write cycle. This delay is referred to as Write t
WR
.
The bank undergoing auto pre-charge can not be reactivated until t
WR
and t
RP
are satisfied. This is
referred to as t
DAL
, Data-in to Active delay (t
DAL
= t
WR
+ t
RP
). When using the Auto Pre-charge
Command, the interval between the Bank Activate Command and the beginning of the internal pre-
charge operation must satisfy t
RAS
(min).
Pre-charge Command
The Pre-charge Command is used to pre-charge or close a bank that has been activated. The Pre-
charge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the
clock. The Pre-charge Command can be used to pre-charge each bank separately or all banks
simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be pre-
charged when the command is issued. After the Pre-charge Command is issued, the pre-charged
bank must be reactivated before a new read or write access can be executed. The delay between the
Pre-charge Command and the Activate Command must be greater than or equal to the Pre-charge
time (t
RP
).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at
the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once
the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the
SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled.
The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits
Self Refresh Operation and before the next command can be issued. This delay is equal to the t
AC
cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (t
REF
) of the
device.
W981216BH
- 16 -
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
CK
. The input buffers need to be
enabled with CKE held high for a period equal to t
CKS
(min) + t
CK
(min).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the
clock. A No Operation Command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W981216BH
Publication Release Date: September 20, 2001
- 17 - Revision A3
10. TIMING WAVEFORMS
Command Input Timing
CLK
A0-A11
BS0, 1
V
IH
V
IL
t
CMH
t
CMS
t
CH
t
CL
t
T
t
T
t
CKS
t
CKH
t
CKH
t
CKS
t
CKS
t
CKH
CS
RAS
CAS
WE
CKE
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
t
CK
W981216BH
- 18 -
Timing Waveforms, continued
Read Timing
Read CAS Latency
t
AC
t
LZ
t
AC
t
OH
t
HZ
t
OH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
DQ
Valid
Data-Out
Valid
Data-Out
W981216BH
Publication Release Date: September 20, 2001
- 19 - Revision A3
Timing Waveforms, continued
Control Timing of Input/Output Data
t
CMH
t
CMS
t
CMH
t
CMS
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CKH
t
CKS
t
CKH
t
CKS
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CMH
t
CMS
t
CMH
t
CMS
t
OH
t
AC
t
OH
t
AC
t
OH
t
HZ
OPEN
t
LZ
t
AC
t
OH
t
AC
t
CKH
t
CKS
t
CKH
t
CKS
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
CLK
DQM
DQ0 -15
(Word Mask)
(Clock Mask)
CLK
CKE
DQ0 -15
CLK
Control Timing of Input Data
Control Timing of Output Data
(Output Enable)
(Clock Mask)
DQM
DQ0 -15
CKE
CLK
DQ0 -15
W981216BH
- 20 -
Timing Waveforms, continued
Mode Register Set Cycle
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
Reserved
A0
A7
A0
A9
A0
Write Mode
A10
A0
A11
BS0
"0"
"0"
A0
A3
A0
Addressing Mode
A0
0
A0
Sequential
A0
1
A0
Interleave
A0
A9
Single Write Mode
A0
0
A0
Burst read and Burst write
A0
1
A0
Burst read and single write
A0
A0
A2 A1 A0
A0
0 0 0
A0
0 0 1
A0
0 1 0
A0
0 1 1
A0
1 0 0
A0
1 0 1
A0
1 1 0
A0
1 1 1
A0
Burst Length
A0
Sequential
A0
Interleave
1
A0
1
A0
2
A0
2
A0
4
A0
4
A0
8
A0
8
A0
Reserved
A0
Reserved
A0
Full Page
A0
CAS Latency
A0
Reserved
A0
Reserved
2
A0
3
Reserved
A0
A6 A5 A4
A0
0 0 0
A0
0 1 0
A0
0 1 1
A0
1 0 0
A0
0 0 1
t
RSC
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
CLK
CS
RAS
CAS
WE
A0-A11
BS0,1
Register
set data
next
command
A0
Reserved
"0"
"0"
BS1
"0"
"0"
W981216BH
Publication Release Date: September 20, 2001
- 21 - Revision A3
11. OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RP
t
RAS
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
Precharge
Precharge
Precharge
RAa
RBb
RAc
RBd
RAe
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W981216BH
- 22 -
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Pre-charge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
t
RC
RAa
RBb
RAc
RBd
RAe
DQ
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
dz0
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
AP*
AP*
RAa
CAw
RBb
CBx
RAc
CAy
RBd
RAe
CBz
W981216BH
Publication Release Date: September 20, 2001
- 23 - Revision A3
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAc
RAc
CAz
ax0
ax1
ax2
ax3
ax4
ax5
ax6
by0
by1
by4
by5
by6
by7
CZ0
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active
Read
Precharge
Active
Read
Precharge
Active
t
AC
t
AC
Read
Precharge
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W981216BH
- 24 -
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Pre-charge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
ax0
ax1
ax2
ax3
ax4
ax5
ax6
ax7
by0
by1
by4
by5
by6
CZ0
RAa
RAa
CAx
RBb
RBb
CBy
(CLK = 100 MHz)
RAc
RAc
CAz
* AP is the internal precharge start timing
Active
Read
Active
Active
Read
t
CAC
t
CAC
t
CAC
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
Bank #0
Idle
Bank #1
Bank #2
Bank #3
Read
AP*
AP*
BS0
W981216BH
Publication Release Date: September 20, 2001
- 25 - Revision A3
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAc
RAc
CAz
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
(CLK = 100 MHz)
Write
Precharge
Active
Active
Write
Precharge
Active
Write
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Idle
Bank #0
Bank #1
Bank #2
Bank #3
t
RAS
W981216BH
- 26 -
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8, Auto Pre-charge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAb
RAc
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
CAz
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active
Write
Write
Active
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
Active
Write
AP*
W981216BH
Publication Release Date: September 20, 2001
- 27 - Revision A3
Operating Timing Example, continued
Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
CCD
t
CCD
t
CCD
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RRD
RAa
RAa
CAI
RBb
RBb
CBx
CAy
CAm
CBz
a0
a1
a2
a3
bx0
bx1
Ay0
Ay1
Ay2
am0
am1
am2
bz0
bz1
bz2
bz3
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active
Read
Active
Read
Read
Read
Read
Precharge
t
AC
t
AC
t
AC
t
AC
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
W981216BH
- 28 -
Operating Timing Example, continued
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RAS
t
RP
t
RCD
t
WR
RAa
RAa
CAx
CAy
ax0
ax1
ax2
ax3
ax4
ax5
ay1
ay0
ay2
ay4
ay3
Q Q
Q
Q
Q
Q
D
D
D
D
D
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active
Read
Write
Precharge
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W981216BH
Publication Release Date: September 20, 2001
- 29 - Revision A3
Operating Timing Example, continued
Auto Pre-charge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
AC
Active
Read
AP*
Active
Read
RAa
RAb
RAa
CAw
RAb
CAx
aw0
aw1
aw2
aw3
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
t
AC
AP*
bx0
bx1
bx2
bx3
W981216BH
- 30 -
Operating Timing Example, continued
Auto Pre-charge Write (Burst Length = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
RAa
t
RCD
t
RCD
RAb
RAc
RAa
CAw
RAb
CAx
RAc
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
Active
Active
Write
AP*
Active
Write
AP*
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W981216BH
Publication Release Date: September 20, 2001
- 31 - Revision A3
Operating Timing Example, continued
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
t
RC
t
RP
t
RC
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
WE
CAS
RAS
CS
BS0,1
W981216BH
- 32 -
Operating Timing Example, continued
Self Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0,1
WE
CAS
RAS
CS
t
CKS
t
SB
t
CKS
t
CKS
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
t
RP
Self Refresh Cycle
t
RC
No Operation Cycle
W981216BH
Publication Release Date: September 20, 2001
- 33 - Revision A3
Operating Timing Example, continued
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
(CLK = 100 MHz)
t
RCD
RBa
RBa
CBv
CBw
CBx
CBy
CBz
av0
av1
av2
av3
aw0
ax0
ay0
az0
az1
az2
az3
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
t
AC
t
AC
Read
Read
Single Write
Active
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W981216BH
- 34 -
Operating Timing Example, continued
Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
RAa
CAa
RAa
CAx
RAa
RAa
ax0
ax1
ax2
ax3
t
SB
t
CKS
t
CKS
t
CKS
t
SB
t
CKS
Active Standby
Power Down mode
Precharge Standby
Power Down mode
Active
NOP
Precharge
NOPActive
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
CLK
DQ
CKE
DQM
A0-A9
A11
A10
BS
WE
CAS
RAS
CS
Read
W981216BH
Publication Release Date: September 20, 2001
- 35 - Revision A3
Operating Timing Example, continued
Auto Pre-charge Timing (Read Cycle)
Read
AP
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Q0
Read
AP
Act
Q1
Read
AP
Act
Q1
Q2
AP
Act
Read
Act
Q0
Q3
(1) CAS Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note )
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0
Read
AP
Act
Q0
Read
AP
Act
Q1
Q0
Read
AP
Act
Q1
Q2
Q3
Read
AP
Act
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(2) CAS Latency=3
t
RP
t
RP
t
RP
t
RP
W981216BH
- 36 -
Operating Timing Example, continued
Auto Pre-charge Timing (Write Cycle)
Write
Act
AP
0
11
10
9
8
7
6
5
4
3
2
1
D0
D0
D0
D0
AP
Act
D1
AP
Act
D1
D1
D2
D2
D3
D3
D4
D5
D6
D7
AP
Act
Write
Write
Write
(1) CAS Latency=2
Write
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS (min).
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note )
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
D0
AP
Act
AP
Act
D1
D0
AP
Act
D1
D2
D3
AP
Act
D0
D1
D2
D3
D4
D5
D6
D7
Write
Write
Write
Write
D0
(2) CAS Latency=3
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W981216BH
Publication Release Date: September 20, 2001
- 37 - Revision A3
Operating Timing Example, continued
Timing Chart of Read to Write Cycle
Note: The Output data must be masked by DQM to avoid I/O conflict
11
10
9
8
7
6
5
4
3
2
1
0
(1) CAS Latency=2
In the case of Burst Length = 4
Read
Read
Write
Write
DQ
DQ
( b ) Command
DQM
DQM
D0
D1
D2
D3
D0
D1
D2
D3
( a ) Command
(2) CAS Latency=3
Read
Write
Read
Write
D0
D1
D2
D3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
D0
D1
D2
D3
Timing Chart of Write to Read Cycle
Read
Write
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Read
Q1
Q2
Q3
Read
Read
Write
Write
Q0
Q1
Q2
Q3
Write
Q0
Q1
Q2
Q3
D0
D1
DQ
DQ
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
( a ) Command
( b ) Command
DQM
DQM
In the case of Burst Length=4
(1) CAS Latency=2
(2) CAS Latency=3
D0
D0
D1
Q0
Q1
Q2
Q3
D0
W981216BH
- 38 -
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Burst Stop Command)
Read
BST
0
11
10
9
8
7
6
5
4
3
2
1
DQ
Q0
Q1
Q2
Q3
BST
( a ) CAS latency =2
Command
( b )CAS latency = 3
(1) Read cycle
Q4
(2) Write cycle
Command
Read
Command
Q0
Q1
Q2
Q3
Q4
Q0
Q1
Q2
Q3
Q4
DQ
DQ
Write
BST
Note: represents the Burst stop command
BST
Timing Chart of Burst Stop Cycle (Pre-charge Command)
In the case of Burst Lenght = 8
Read
PRCG
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Read
PRCG
Q4
Q4
( a )CAS latency =2
Command
( b )CAS latency = 3
Command
DQ
DQ
DQ
( b )CAS latency = 3
Command
(1) Read cycle
(2) Write cycle
Write
Write
PRCG
PRCG
( a ) CAS latency =2
Command
DQM
DQM
t
WR
t
WR
D0
D1
D2
D3
D4
DQ
D0
D1
D2
D3
D4
DQ
W981216BH
Publication Release Date: September 20, 2001
- 39 - Revision A3
Operating Timing Example, continued
CKE/DQM Input Timing (Write Cycle)
7
6
5
4
3
2
1
CKE MASK
( 1 )
D1
D6
D5
D3
D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5
4
3
2
1
( 2 )
D1
D6
D5
D3
D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5
4
3
2
1
( 3 )
D1
D6
D5
D4
D3
D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK
CKE MASK
CKE MASK
Internal
CLK
CLK
CLK
W981216BH
- 40 -
Operating Timing Example, continued
CKE/DQM Input Timing (Read Cycle)
7
6
5
4
3
2
1
( 1 )
Q1
Q6
Q4
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
Open
7
6
5
4
3
2
1
Q1
Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
( 2 )
7
6
5
4
3
2
1
Q1
Q6
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Q5
Q4
( 3 )
Q4
CLK
CLK
CLK
Q3
W981216BH
Publication Release Date: September 20, 2001
- 41 - Revision A3
Operating Timing Example, continued
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)
Command
NOP
CLK
CKE
Command
A ) tCK < tCKS(min)+t CK(min)
Input Buffer Enable
Command
CLK
CKE
Command
B) tCK
>= tCKS(min) + t CK
(min)
Input Buffer Enable
Note )
Command
NOP
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
Represents the No-Operation command
Represents one command
t
CK
t
CK
t
CKS
(min)+t
CK
(min)
t
CKS
(min)+t
CK
(min)
W981216BH
- 42 -
12. PACKAGE DIMENSION
54L TSOP (II)-400 mil
SEATING PLANE
E
D
A2
A1
A
e
b
ZD
1
27
54
28
H
E
Y
L
C
L1
ZD
0.71
0.028
0.002
0.009
MAX.
MIN.
NOM.
A2
b
A
A1
0.24
1.00
0.05
0.40
1.20
0.15
SYM.
DIMENSION
(MM)
MAX.
MIN.
NOM.
e
0.80
0.0315
0.016
L
0.40
0.50
0.60
0.020
0.024
0.396
E
10.06
10.16
10.26
0.400
0.404
0.871
D
22.22
22.12
22.62
0.875
0.905
0.039
0.016
0.047
0.006
DIMENSION
(INCH)
0.10
0.004
0.32
L1
0.80
0.032
c
0.15
0.006
0.012
0.455
11.76
11.56
11.96
0.463
0.471
H
E
Y
0.10
0.004
Controlling Dimension: Millimeters
W981216BH
Publication Release Date: September 20, 2001
- 43 - Revision A3
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886 -3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886 -2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886 -2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852 -27513100
FAX: 852 -27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886 -3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886 -2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886 -2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852 -27513100
FAX: 852 -27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
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