W981616BH

512K

×
×

2 BANKS

×
×

16 BITS SDRAM

Publication Release Date: February 2000

- 1 - Revision A2

GENERAL DESCRIPTION

W981616BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words

2 banks

16 bits. Using pipelined architecture and 0.175

m process technology,

W981616BH delivers a data bandwidth of up to 332M bytes per second (-5). For different applications
the W981616BH is sorted into the following speed grades: -5, -6, and 7(L).

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981616BH is ideal for main memory in
high performance applications.

FEATURES

3.3V ±0.3V power supply

Up to 166 MHz clock frequency

524,288 words x 2 banks x 16 bits organization

Auto Refresh and Self Refresh

CAS latency: 2 and 3

Burst Length: 1, 2, 4, 8, and full page

Burst read, Single Write Mode

Byte data controlled by UDQM and LDQM

Auto-precharge and controlled precharge

4K refresh cycles/64 mS

Interface: LVTTL

Packaged in 50-pin, 400 mil TSOP II

PIN CONFIGURATION

DQ0

DQ1

V Q

DQ2

DQ3

V Q

DQ4

DQ5

V Q

DQ6

DQ7

V Q

CAS

RAS

LDQM

A10

DQ15

DQ14

V Q

DQ13

DQ12

V Q

DQ11

DQ10

V Q

DQ9

DQ8

V Q

UDQM

CLK

CKE

W981616BH

- 2 -

PIN DESCRIPTION

PIN NUMBER PIN NAME FUNCTION

DESCRIPTION

24,

A10

Address

Multiplexed pins for row and column address.
Row address: A0

A10. Column address: A0

A7.

Bank Select Select bank to activate during row address latch time,

or bank to read/write during column address latch
time.

2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49

DQ0

DQ15

Data Input/

Output

Multiplexed pins for data input and output.

Chip Select Disable or enable the command decoder. When

command decoder is disabled, new command is
ignored and previous operation continues.

RAS

Row Address

Strobe

Command input. When sampled at the rising edge of

the clock,

RAS

CAS

and

define the operation

to be executed.

CAS

Column

Address Strobe

Referred to

RAS

Write Enable Referred to

RAS

36, 14

UDQM/

LDQM

Input/Output

Mask

The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.

CLK

Clock Inputs System clock used to sample inputs on the rising

edge of clock.

CKE

Clock Enable CKE controls the clock activation and deactivation.

W hen CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.

1, 25

Power (+3.3V) Power for input buffers and logic circuit inside DRAM.

26, 50

Ground

Ground for input buffers and logic circuit inside
DRAM.

7, 13, 38, 44,

Power (+3.3V)

for I/O buffer

Separated power from V

, used for output buffers to

improve noise immunity.

4, 10, 41, 47

Ground for I/O

buffer

Separated ground from V

, used for output buffers

to improve noise immunity.

33, 37

No Connection No connection

W981616BH

- 4 -

FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all V

and V

Q pins must be ramp up simultaneously to the

specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed V

+0.3V on any of the input pins or V

supplies. After power up, an initial pause of 200

is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of

RAS

CAS

and

at the positive edge of the clock. The address input data during

this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to t

RSC

has

elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.

The operation is similar to

RAS

activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t

RCD

). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and
vice versa) is the Bank-to-Bank delay time (t

RRD

). The maximum time that each bank can be held

active is specified as t

RAS

(max.).

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by

setting

RAS

high and

CAS

low at the clock rising edge after minimum of t

RCD

delay.

voltage level defines whether the access cycle is a read operation (

high), or a write operation

(

low). The address inputs determine the starting column address. Reading or writing to a

different row within an activated bank requires the bank be precharged and a new Bank Activate
command be issued. When more than one bank is activated, interleaved bank Read or Write
operations are possible. By using the programmed burst length and alternating the access and
precharge operations between multiple banks, seamless data access operation among many different
pages can be realized. Read or Write Commands can also be issued to the same bank or between
active banks on every clock cycle.

W981616BH

Publication Release Date: February 2000

- 5 - Revision A2

Burst Read Command

The Burst Read command is initiated by applying logic low level to

and

CAS

while holding

RAS

and

high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.

Burst Write Command

The Burst Write command is initiated by applying logic low level to

CAS

and

while

holding

RAS

high at the rising edge of the clock. The address inputs determine the starting column

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When
the previous burst is interrupted, the remaining addresses are overridden by the new address and
data will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is
full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst

W981616BH

- 6 -

Stop Command is defined by having

RAS

and

CAS

high with

and

low at the rising edge

of the clock. The data DQs go to a high impedance state after a delay, which is equal to the

CAS

Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2

Table 2 Address Sequence of Sequential Mode

DATA

Access Address

Burst Length

Data 0

BL = 2 (disturb address is A0)

Data 1

n + 1

No address carry from A0 to A1

Data 2

n + 2

BL = 4 (disturb addresses are A0 and A1)

Data 3

n + 3

No address carry from A1 to A2

Data 4

n + 4

Data 5

n + 5

BL = 8 (disturb addresses are A0, A1 and A2)

Data 6

n + 6

No address carry from A2 to A3

Data 7

n + 7

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA

Access Address

Bust Length

Data 0

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 2

Data 1

A8 A7 A6 A5 A4 A3 A2 A1

Data 2

A8 A7 A6 A5 A4 A3 A2

BL = 4

Data 3

A8 A7 A6 A5 A4 A3 A2

Data 4

A8 A7 A6 A5 A4 A3

A1 A0

BL = 8

Data 5

A8 A7 A6 A5 A4 A3

Data 6

A8 A7 A6 A5 A4 A3

Data 7

A8 A7 A6 A5 A4 A3

W981616BH

Publication Release Date: February 2000

- 7 - Revision A2

Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by

CAS

latency.

A Read or Write Command with auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (t

) has been satisfied. Issue of Auto-Precharge command is

illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write t

DPL

. The bank

undergoing auto-precharge can not be reactivated until t

DPL

and t

are satisfied. This is referred to as

DAL

, Data-in to Active delay (t

DAL

= t

DPL

+ t

). When using the Auto-precharge Command, the interval

between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy t

RAS

(min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when

RAS

and

are low and

CAS

is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge
time (t

Self Refresh Command

The Self-Refresh Command is defined by having

RAS

CAS

and CKE held low with

high

at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device
will exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after t

from the end of Self Refresh command.

If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 Auto-Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (t

REF

) of the

device.

W981616BH

- 8 -

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t

. The input buffers need to be

enabled with CKE held high for a period equal to t

CES

(min) + t

(min).

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when

is low with

RAS

CAS

, and

held high at the rising edge of

the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect

Command occurs when

is brought high, the

RAS

CAS

, and

signals become don't cares.

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.

W981616BH

Publication Release Date: February 2000

- 9 - Revision A2

TABLE OF OPERATING MODES

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (NOTE 1, 2)

Command

Device

State

CKEn-1 CKEn DQM BA A10 A9-0 CS RAS CAS

Bank Active

Idle

Bank Precharge

Any

Precharge All

Any

Write

Active (3)

Write with
Autoprecharge

Active (3)

Read

Active (3)

Read with
Autoprecharge

Active (3)

Mode Register Set

Idle

No-Operation

Any

Burst Stop

Active (4)

Device Deselect

Any

Auto-Refresh

Idle

Self-Refresh Entry

Idle

Self-Refresh Exit

Idle

(S.R)

L
L

H
H

X
X

X
H

X
X

Clock Suspend Mode
Entry

Active

Power Down Mode
Entry

Idle

Active (5)

H
H

L
L

X
X

X
H

X
X

Clock Suspend Mode
Exit

Active

Power Down Mode Exit

Any

(Power

down)

L
L

H
H

X
X

Data Write/Output
Enable

Active

Data Write/Output
Disable

Active

Notes:

(1) V = Valid, X = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input level when commands are provided.

(3) These are state of bank designated by BA signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

W981616BH

- 10 -

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

UNIT

NOTES

Input, Output Voltage

, V

OUT

-0.3

4.6

Power Supply Voltage

, V

-0.3

4.6

Operating Temperature

OPR

Storage Temperature

STG

-55

150

Soldering Temperature (10s)

SOLDER

260

Power Dissipation

Short Circuit Output Current

OUT

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

RECOMMENDED DC OPERATING CONDITIONS

= 0 to 70

PARAMETER

SYM.

MIN.

TYP.

MAX.

UNIT

NOTES

Power Supply Voltage

3.0

3.3

3.6

Power Supply Voltage (for I/O
Buffer)

3.0

3.3

3.6

Input High Voltage

2.0

+0.3

Input Low Voltage

-0.3

0.8

Note

(max.) = V

Q +1.2V for pulse width < 5 nS

(min.) = V

Q -1.2V for pulse width < 5 nS

CAPACITANCE

= 3.3V, T

= 25

C, f = 1MHz)

PARAMETER

SYM.

MIN. MAX. UNIT

Input Capacitance (A0 to A10, BA,

RAS

CAS

UDQM, LDQM, CKE)

Input Capacitance (CLK)

Input/Output capacitance (DQ0 to DQ15)

6.5

Note: These parameters are periodically sampled and not 100% tested

W981616BH

Publication Release Date: February 2000

- 11 - Revision A2

DC CHARACTERISTICS

= 3.3V

0.3V, T

= 0

~70

PARAMETER

SYM

-5

MAX.

-6

MAX.

-7

MAX.

-7L

MAX.

UNIT NOTES

Operating Current
t

= min., t

= min.

Active precharge command
cycling without burst
operation

1 bank operation

CC1

100

Standby Current

= min., CS

= V

/L = V

(min.) /V

(max.)
Bank: inactive state

CKE = V

CC2

CKE = V

(Power down mode)

CC2P

Standby Current

CLK = V

, CS

= V

/L = V

(min.) /V

(max.)

Bank: inactive state

CKE = V

CC2S

CKE = V

(Power down mode)

CC2P

No Operating Current

= min., CS

= V

(min.)

Bank: active state (2 banks)

CKE = V

CC3

CKE = V

(Power Down mode)

CC3P

Burst Operating Current (t

= min.)

Read/ Write command cycling

CC4

190

165

145

3, 4

Auto Refresh Current (t

= min.)

Auto refresh command cycling

CC5

125

120

110

Self Refresh Current (CKE = 0.2V)
Self refresh mode

CC6

0.45

PARAMETER

SYM.

MIN.

MAX. UNIT NOTES

Input Leakage Current

(0V

, all other pins not under test = 0V)

I(L)

-5

Output Leakage Current

(Output disable , 0V

OUT

Q )

O(L)

-5

LVTTL OutputT

Level Voltage

OUT

= -2 mA)

2.4

LVTTL Output

Level Voltage

OUT

= 2 mA)

0.4

W981616BH

- 12 -

AC CHARACTERISTICS

= 3.3V

0.3V, V

= 0V, T

= 0 to 70

C, Notes: 5, 6, 7, 8)

PARAMETER

SYM.

-5

-6

-7(L)

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Ref/Active to Ref/Active Command Period

Active to Precharge Command Period

RAS

100000

Active to Read/Write Command Delay
Time

RCD

Read/Write(a) to Read/Write(b)Command
Period

CCD

Cycle

Precharge to Active(b) Command Period

Active(a) to Active(b) Command Period

RPD

Write Recovery Time

CL* = 2

CL* = 3

CLK Cycle Time

CL* = 2

1000

CL* = 3

1000

CLK High Level Width

CLK Low Level Width

Access Time from CLK

CL* = 2

4.5

5.5

CL* = 3

4.5

Output Data Hold Time

2.75

Output Data High Impedance Time

2.75

Output Data Low Impedance Time

Power Down Mode Entry Time

Transition Time of CLK (Rise and Fall)

0.5

Data-in-Set-up Time

1.5

Data-in Hold Time

Address Set-up Time

1.5

Address Hold Time

CKE Set-up Time

CKS

1.5

CKE Hold Time

CKH

Command Set-up Time

CMS

1.5

Command Hold Time

CMH

Refresh Time

REF

Mode Register Set Cycle Time

RSC

(L):For low power

W981616BH

Publication Release Date: February 2000

- 13 - Revision A2

Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the

devices.

2. All voltages are referenced to V

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the

minimum values of t

and t

4. These parameters depend on the output loading conditions. Specified values are obtained with

output open.

5. Power up sequence is further described in the "Functional Description" section.

6. AC test conditions.

PARAMETER

CONDITIONS

Output Reference Level

1.4V/1.4V

Output Load

See diagram below

Input Signal Levels

2.4V/0.4V

Transition Time (Rise and Fall) of Input Signal

2 nS

Input Reference Level

1.4V

50 ohms

1.4 V

Z = 50 ohms

output

AC TEST LOAD

30pF

7. Transition times are measured between V

and V

8. t

defines the time at which the outputs achieve the open circuit condition and is not referenced

to output level.

W981616BH

- 16 -

Control Timing of Input/Output Data

CMH

CMS

CMH

CMS

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

CKH

CKS

CKH

CKS

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

CMH

CMS

CMH

CMS

OPEN

CKH

CKS

CKH

CKS

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

CLK

DQM

DQ0 -15

(Word Mask)

(Clock Mask)

CLK

CKE

DQ0 -15

CLK

Input Data

Output Data

(Output Enable)

(Clock Mask)

DQM

DQ0 -15

CKE

CLK

DQ0 -15

W981616BH

Publication Release Date: February 2000

- 17 - Revision A2

Mode Reqister Set Cycle

Burst Length

Addressing Mode

CAS Latency

(Test Mode)

Reserved

Write Mode

A10

"0"

Addressing Mode

Sequential

Interleave

Single Write Mode

Burst read and Burst write

Burst read and single write

A2 A1 A0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Burst Length

Sequential

Interleave

Reserved

Full Page

CAS Latency

Reserved

2
3

Reserved

A6 A5 A4

0 0 0

0 1 0
0 1 1
1 0 0

0 0 1

RSC

CMS

CMH

CMS

CMH

CMS

CMH

CMS

CMH

CLK

RAS

CAS

A0-A10

set data

command

Reserved

"0"

W981616BH

- 18 -

Interleaved Bank Read

(Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9

A10

CAS

RAS

RCD

RRD

Active

Read

Active

Read

Active

Read

Precharge

RAa

RBb

RAc

RBd

RAe

RAa

CAw

RBb

CBx

RAc

CAy

RBd

CBz

RAe

aw0

aw1

aw2

aw3

bx0

bx1

bx2

bx3

cy0

cy1

cy2

cy3

Bank #0

Bank #1

W981616BH

Publication Release Date: February 2000

- 19 - Revision A2

Interleaved Bank Read

(Burst Length = 4, CAS Latency = 3, Autoprecharge)

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9

A10

CAS

RAS

RCD

RRD

Active

Read

Active

Read

Active

Read

RAa

RAc

RBd

RAe

aw0

aw1

aw2

aw3

bx0

bx1

bx2

bx3

cy0

cy1

cy2

cy3

dz0

* AP is the internal precharge start timing

Bank #0

Bank #1

AP*

RAa

CAw

RBb

CBx

RAc

CAy

RBd

RAe

CBz

RBb

W981616BH

Publication Release Date: February 2000

- 21 - Revision A2

Interleaved Bank Read

(Burst Length = 8, CAS Latency = 3, Autoprecharge)

RAS

RCD

RRD

ax0

ax1

ax2

ax3

ax4

ax5

ax6

ax7

by0

by1

by4

by5

by6

CZ0

RAa

CAx

RBb

CBy

(CLK = 100 MHz)

RAc

CAz

* AP is the internal precharge start timing

Active

Read

Active

Read

CAC

CLK

CKE

DQM

A0-A9

A10

CAS

RAS

Bank #0

Bank #1

Read

AP*

W981616BH

Publication Release Date: February 2000

- 23 - Revision A2

Interleaved Bank Write

(Burst Length = 8, Autoprecharge)

Bank #0

Bank #1

RAS

RCD

RRD

RAa

CAx

RBb

CBy

RAb

ax0

ax1

ax4

ax5

ax6

ax7

by0

by1

by2

by3

by4

by5

by6

by7

CZ0

CZ1

CZ2

CAz

(CLK = 100 MHz)

* AP is the internal precharge start timing

CLK

CKE

DQM

A0-A9

A10

CAS

RAS

Active

Write

Active

AP*

Active

Write

AP*

W981616BH

Publication Release Date: February 2000

- 31 - Revision A2

PowerDown Mode

(CLK = 100 MHz)

RAa

CAa

RAa

CAx

RAa

ax0

ax1

ax2

ax3

CKS

Active Standby

Power Down mode

Precharge Standby
Power Down mode

Active

NOP

Precharge

NOPActive

Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.

CLK

CKE

DQM

A0-A9

A10

Read

RAS

CAS

W981616BH

- 32 -

Autoprecharge Timing

(Read Cycle)

Read

Act

Read

Act

Read

Act

(1) CAS Latency=2

Read

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least t

RAS

(min).

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

Note:

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Read

Act

Read

Act

Read

Act

Read

Act

(2) CAS Latency=3

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

W981616BH

Publication Release Date: February 2000

- 33 - Revision A2

Autoprecharge Timing

(Write Cycle)

Act

Write

Act

Write

Act

Write

(1) CAS Latency = 2

(2) CAS Latency = 3

Write

Act

When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS(min) .

represents the Write with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

Note:

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

W981616BH

- 34 -

Timing Chart of Write-to-Read Cycle

In the case of Burst Length = 4

Read

Write

( a ) Command

( b ) Command

DQM

(2) CAS Latency = 3

Read

Write

Read

Write

( a ) Command

DQM

( b ) Command

DQM

(1) CAS Latency = 2

Timing Chart of Burst Stop Cycle

(Burst Stop Command)

Read

BST

Read

BST

( a ) CAS latency =2

Command

( b ) CAS latency = 3

Command

(3) Read cycle

Write

BST

Command

(2) Write cycle

Note:

represents the Burst stop command

BST

W981616BH

Publication Release Date: February 2000

- 39 - Revision A2

PACKAGE DIMENSIONS

50L-TSOP (II) 400 mill

SEATING PLANE

0.88

0.031

0.035

0.002

0.012

MAX.

MIN.

NOM.

0.30

0.90

1.00

0.05

1.10

0.45

1.20

0.15

SYM.

DIMENSION(MM)

MAX.

MIN.

NOM.

0.80

0.031

0.016

0.40

0.50

0.60

0.020

0.024

0.395

10.03

10.16

10.29

0.400

0.405

0.820

20.95

20.82

21.08

0.825

0.830

0.039

0.043

0.018

0.047

0.006

DIMENSION(INCH)

0.10

0.004

0.80

0.031

0.004

0.20

0.10

0.008

0.15

0.006

0.455

11.76

11.56

11.96

0.463

0.471

0.10

0.004

Controlling Dimension: Millimeters

W981616BH

- 40 -

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

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