W981616BH
512K
2 BANKS
16 BITS SDRAM
Publication Release Date: December 25, 2001
- 1 - Revision A4
Table of Contents-
1. GENERAL DESCRIPTION ..................................................................................................................3
2. FEATURES ..........................................................................................................................................3
3. AVAILABLE PART NUMBER...............................................................................................................3
4. PIN CONFIGURATION ........................................................................................................................4
5. PIN DESCRIPTION..............................................................................................................................5
6. BLOCK DIAGRAM ...............................................................................................................................6
7. FUNCTIONAL DESCRIPTION ............................................................................................................7
Power-up and Initialization ................................................................................................................7
Programming Mode Register............................................................................................................7
Bank Activate Command ..................................................................................................................7
Read and Write Access Modes ........................................................................................................7
Burst Read Command ......................................................................................................................8
Burst Write Command ......................................................................................................................8
Read Interrupted by a Read..............................................................................................................8
Read Interrupted by a Write..............................................................................................................8
Write Interrupted by a Write..............................................................................................................8
Write Interrupted by a Read..............................................................................................................8
Burst Stop Command .......................................................................................................................8
Addressing Sequence of Sequential Mode.......................................................................................9
Addressing Sequence of Interleave Mode ........................................................................................9
Auto Precharge Command .............................................................................................................10
Precharge Command......................................................................................................................10
Self Refresh Command ..................................................................................................................10
Power-down Mode ..........................................................................................................................10
No Operation Command.................................................................................................................11
Deselect Command ........................................................................................................................11
Clock Suspend Mode......................................................................................................................11
8. TABLE OF OPERATING MODES .....................................................................................................12
9. ELECTRICAL CHARACTERISTICS ..................................................................................................13
Absolute Maximum Ratings ............................................................................................................13
Recommended DC Operating Conditions ......................................................................................13
Capacitance ....................................................................................................................................13
W981616BH
- 2 -
DC Characteristics ..........................................................................................................................14
AC Characteristics ..........................................................................................................................15
10. TIMING WAVEFORMS....................................................................................................................17
Command Input Timing ..................................................................................................................17
Read Timing ...................................................................................................................................18
Control Timing of Input/Output Data ...............................................................................................19
Mode Reqister Set Cycle ................................................................................................................20
11. OPERATING TIMING EXAMPLE ....................................................................................................21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) .............................22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) .............................24
Interleaved Bank Write (Burst Length = 8) .....................................................................................25
Interleaved Bank Write (Burst Length = 8, Auto Precharge) ..........................................................26
Page Mode Read (Burst Length = 4, CAS Latency = 3) .................................................................27
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) .......................................................28
Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ..........................................................29
Auto Precharge Write (Burst Length = 4) .......................................................................................30
Auto Refresh Cycle .........................................................................................................................31
Self Refresh Cycle ..........................................................................................................................32
Bust Read and Single Write (Burst Lenght = 4, CAS Latency = 3).................................................33
Power-down Mode ..........................................................................................................................34
Auto Precharge Timing (Read Cycle) .............................................................................................35
Auto Precharge Timing (Write Cycle) .............................................................................................36
Timing Chart of Write-to-Read Cycle (In the case of Burst Length = 4) .........................................37
Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................37
Timing Chart of Burst Stop Cycle (Prechare Command)................................................................38
CKE/DQM Input Timing (Write Cycle) ............................................................................................39
CKE/DQM Input Timing (Read Cycle) ............................................................................................40
Self Refresh/Power-down Mode Exit Timing ..................................................................................41
12. PACKAGE DIMENSIONS ................................................................................................................42
50L-TSOP (II) 400 mill ....................................................................................................................42
13. VERSION HISTORY ........................................................................................................................43
W981616BH
Publication Release Date: December 25, 2001
- 3 - Revision A4
1. GENERAL DESCRIPTION
W981616BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
2 banks
16 bits. Using pipelined architecture and 0.175
m process technology,
W981616BH delivers a data bandwidth of up to 400M bytes per second (-5). For different applications
the W981616BH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to
200MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For
handheld device application, we also provide a low power option, the grade of 7L, with Self Refresh
Current under 200 A
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981616BH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V
0.3V power supply
Up to 200 MHz clock frequency
524,288 words x 2 banks x 16 bits organization
Self Refresh current: standard and low power
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst read, Single Write Mode
Byte data controlled by UDQM and LDQM
Auto precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 50-pin, 400 mil TSOP II
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED (CL = 3 )
SELF REFRESH CURRENT(MAX.)
W981616BH-5
200 MHz
1 mA
W981616BH-6
166 MHz
1 mA
W981616BH-7
143 MHz
1 mA
W981616BH-7L
143 MHz
200
A
W981616BH
- 4 -
4. PIN CONFIGURATION
46
47
48
49
50
42
43
44
45
38
39
40
41
V
SS
1
2
3
4
5
DQ0
6
7
8
9
10
11
12
13
CS
NC
24
15
14
19
18
17
16
22
21
20
23
25
V
CC
DQ1
V Q
SS
DQ2
DQ3
V Q
CC
DQ4
DQ5
V Q
SS
DQ6
DQ7
V Q
CC
WE
CAS
RAS
LDQM
BA
A1
A2
A3
A0
A10
V
CC
26
27
28
36
37
32
33
34
35
29
30
31
DQ15
DQ14
V Q
SS
DQ13
DQ12
V Q
CC
DQ11
DQ10
V Q
SS
DQ9
DQ8
V Q
CC
UDQM
NC
CLK
CKE
A9
A6
A5
A4
A7
A8
V
SS
W981616BH
Publication Release Date: December 25, 2001
- 5 - Revision A4
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
20
-
24,
27
-
32
A0
-
A10
Address Multiplexed pins for row and column address.
Row address: A0
-
A10. Column address: A0
-
A7.
19
BA
Bank Select Select bank to activate during row address latch time,
or bank to read/write during column address latch time.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
DQ0
-
DQ15 Data Input/
Output
Multiplexed pins for data input and output.
18
CS
Chip Select Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
17
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the
operation to be executed.
16
CAS
Column
Address
Strobe
Referred to
RAS
15
WE
Write Enable Referred to
RAS
36, 14
UDQM/
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
35
CLK
Clock Inputs System clock used to sample inputs on the rising edge
of clock.
34
CKE
Clock Enable CKE controls the clock activation and deactivation.
When CKE is low, Power-down mode, Suspend mode,
or Self Refresh mode is entered.
1, 25
V
CC
Power
(+3.3V)
Power for input buffers and logic circuit inside DRAM.
26, 50
V
SS
Ground Ground for input buffers and logic circuit inside DRAM.
7, 13, 38, 44,
V
CC
Q
Power
(+3.3V) for
I/O buffer
Separated power from V
CC
, used for output buffers to
improve noise immunity.
4, 10, 41, 47
V
SS
Q
Ground for
I/O buffer
Separated ground from V
SS
, used for output buffers to
improve noise immunity.
33, 37
NC
No
Connection
No connection
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