W9816G6BB

512K

× 2 BANKS × 16 BITS SDRAM

Publication Release Date: January 2, 2003

- 1 -

Revision A1

Table of Contens-

1. GENERAL DESCRIPTION.................................................................................................................. 3

2. FEATURES ......................................................................................................................................... 3

3. PART NUMBER INFORMATION........................................................................................................ 3

4. BALL CONFIGURATION .................................................................................................................... 4

5. BALL DESCRIPTION .......................................................................................................................... 5

6. BLOCK DIAGRAM .............................................................................................................................. 6

7. FUNCTIONAL DESCRIPTION............................................................................................................ 7

Power Up and Initialization................................................................................................................ 7

Programming Mode Register ............................................................................................................ 7

Bank Activate Command................................................................................................................... 7

Read and Write Access Modes......................................................................................................... 7

Burst Read Command....................................................................................................................... 8

Burst Write Command....................................................................................................................... 8

Read Interrupted by a Read.............................................................................................................. 8

Read Interrupted by a Write .............................................................................................................. 8

Write Interrupted by a Write .............................................................................................................. 8

Write Interrupted by a Read .............................................................................................................. 8

Burst Stop Command........................................................................................................................ 8

Addressing Sequence of Sequential Mode....................................................................................... 9

Addressing Sequence of Interleave Mode ........................................................................................ 9

Auto Precharge Command.............................................................................................................. 10

Precharge Command ...................................................................................................................... 10

Self Refresh Command................................................................................................................... 10

Power Down Mode.......................................................................................................................... 10

No Operation Command ................................................................................................................. 11

Deselect Command......................................................................................................................... 11

Clock Suspend Mode ...................................................................................................................... 11

Table of Operating Modes............................................................................................................... 12

8. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 13

9. RECOMMENDED DC OPERATING CONDITIONS ......................................................................... 13

10. CAPACITANCE............................................................................................................................... 13

W9816G6BB

- 2 -

11. DC CHARACTERISTICS ................................................................................................................ 14

12. AC CHARACTERISTICS ................................................................................................................ 15

13. TIMING WAVEFORMS ................................................................................................................... 17

Command Input Timing................................................................................................................... 17

Read Timing .................................................................................................................................... 18

Control Timing of Input/Output Data ............................................................................................... 19

Mode Reqister Set Cycle ................................................................................................................ 20

Interleaved Bank Read.................................................................................................................... 21

Interleaved Bank Read.................................................................................................................... 22

Interleaved Bank Read.................................................................................................................... 23

Interleaved Bank Read.................................................................................................................... 24

Interleaved Bank Write.................................................................................................................... 25

Interleaved Bank Write.................................................................................................................... 26

Page Mode Read ............................................................................................................................ 27

Page Mode Read/Write................................................................................................................... 28

Auto Precharge Read...................................................................................................................... 29

Auto Precharge Write...................................................................................................................... 30

Auto Refresh Cycle ......................................................................................................................... 31

Self Refresh Cycle........................................................................................................................... 32

Bust Read and Single Write ............................................................................................................ 33

Power Down Mode.......................................................................................................................... 34

Auto Precharge Timing ................................................................................................................... 35

Auto Precharge Timing ................................................................................................................... 36

Timing Chart of Write-to-Read Cycle .............................................................................................. 37

Timing Chart of Burst Stop Cycle.................................................................................................... 37

Timing Chart of Burst Stop Cycle (Prechare Command)................................................................ 38

CKE/DQM Input Timing................................................................................................................... 39

CKE/DQM Input Timing................................................................................................................... 40

Self Refresh/ Power Down Mode Exit Timing ................................................................................. 41

14. PACKAGE DIMENSIONS ............................................................................................................... 42

BGA 60 Balls Pitch = 0.65 mm........................................................................................................ 42

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

1. GENERAL DESCRIPTION

W9816G6BB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words x 2 banks x 16 bits. Using pipelined architecture and 0.175

µm process technology,

W9816G6BB delivers a data bandwidth of up to 286M bytes per second (-7).

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6BB is ideal for main memory in
high performance applications.

2. FEATURES

2.7V

- 3.6V power supply

Up to 200 MHz clock frequency

524,288 words x 2 banks x 16 bits organization

Self Refresh Current: standard and low power

CAS latency: 2 and 3

Burst length: 1, 2, 4, 8, and full page

Burst read, single write mode

Byte data controlled by UDQM and LDQM

Auto-precharge and controlled precharge

4K refresh cycles/64 mS

Interface: LVTTL

Package: BGA 60 balls pitch = 0.65 mm using
PB free materials

3. PART NUMBER INFORMATION

PART NUMBER

SPEED (CL = 3)

SELF REFRESH CURRENT(MAX.)

W9816G6BB-7

143 MHz

1 mA

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

5. BALL DESCRIPTION

BALL-LOCATION

BALL

NAME

FUNCTION DESCRIPTION

N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7

- A10

Address

Multiplexed pins for row and column address.
Row address: A0

- A10. Column address: A0 - A7.

M1 BA

Bank

Address

Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.

A6, B7, C7, D7, D6,
E7, F7, G7, G1, F1,
E1, D2, D1, C1, B1,
A2,

DQ0

DQ15

Data Input/

Output

Multiplexed pins for data input and output.

Chip Select

Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.

RAS

Row Address

Strobe

Command input. When sampled at the rising edge of
the clock,

RAS

CAS

and

define the

operation to be executed.

CAS

Column

Address

Strobe

Referred to

RAS

Write Enable Referred to

RAS

J2/J6

UDQM/

LDQM

Input/Output

Mask

The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.

K2 CLK

Clock

Inputs

System clock used to sample inputs on the rising
edge of clock.

L1 CKE

Clock

Enable

CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.

A7, R7

Power

(+3.3V)

Power for input buffers and logic circuit inside
DRAM.

A1, R1

Ground

Ground for input buffers and logic circuit inside
DRAM.

B6, C2, E6, F2

DDQ

Power

(+3.3V) for

I/O buffer

Separated power from V

, used for output buffers

to improve noise immunity.

B2, C6, E2, F6

SSQ

Ground for

I/O buffer

Separated ground from V

, used for output buffers

to improve noise immunity.

G2, G6, H1, H2, H6,
H7, J1, K1, L2, L6,
M6, M7

Connection

No connection

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

7. FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all V

and V

DDQ

pins must be ramp up simultaneously to the

specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed V

+0.3V on any of the input pins or V

supplies. After power up, an initial pause of 200

µS

is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of

RAS

CAS

and

at the positive edge of the clock. The address input data

during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t

RSC

has

elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to

RAS

activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t

RCD

). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank-to-Bank delay time (t

RRD

). The maximum time that each bank can be held active is

specified as t

RAS

(max.).

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS

high and

CAS

low at the clock rising edge after minimum of t

RCD

delay.

pin voltage level

defines whether the access cycle is a read operation (

high), or a write operation (

low). The

address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.

W9816G6BB

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Burst Read Command

The Burst Read command is initiated by applying logic low level to

and

CAS

while holding

RAS

and

high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.

Burst Write Command

The Burst Write command is initiated by applying logic low level to

CAS

and

while

holding

RAS

high at the rising edge of the clock. The address inputs determine the starting column

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having

RAS

and

CAS

high with

and

low at the rising edge of

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

the clock. The data DQs go to a high impedance state after a delay, which is equal to the

CAS

Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

Data

Access Address

Burst Length

Data 0

BL = 2 (disturb address is A0)

Data 1

n + 1

No address carry from A0 to A1

Data 2

n + 2

BL = 4 (disturb addresses are A0 and A1)

Data 3

n + 3

No address carry from A1 to A2

Data 4

n + 4

Data 5

n + 5

BL = 8 (disturb addresses are A0, A1 and A2)

Data 6

n + 6

No address carry from A2 to A3

Data 7

n + 7

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

Data

Access Address

Bust Length

Data 0

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 2

Data 1

A8 A7 A6 A5 A4 A3 A2 A1

Data 2

A8 A7 A6 A5 A4 A3 A2

BL = 4

Data 3

A8 A7 A6 A5 A4 A3 A2

Data 4

A8 A7 A6 A5 A4 A3

A1 A0

BL = 8

Data 5

A8 A7 A6 A5 A4 A3

Data 6

A8 A7 A6 A5 A4 A3

Data 7

A8 A7 A6 A5 A4 A3

W9816G6BB

- 10 -

Auto Precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by

CAS

latency.

A Read or Write Command with auto precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (t

) has been satisfied. Issue of Auto-Precharge command is

illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto Precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write t

. The bank

undergoing auto precharge can not be reactivated until t

and t

are satisfied. This is referred to as

DAL

, Data-in to Active delay (t

DAL

= t

+ t

). When using the Auto Precharge Command, the interval

between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy t

RAS

(min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when

RAS

and

are low and

CAS

is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(t

Self Refresh Command

The Self Refresh Command is defined by having

RAS

CAS

and CKE held low with

high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after t

from the end of Self Refresh command.

If, during normal operation, Auto Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 Auto Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (t

REF

) of the

device.

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t

. The input buffers need to be

enabled with CKE held high for a period equal to t

CKS

(min) + t

(min).

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when

is low with

RAS

CAS

, and

held high at the rising edge of

the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when

is brought high, the

RAS

CAS

, and

signals become don't

cares.

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.

W9816G6BB

- 12 -

Table of Operating Modes

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (NOTE 1, 2)

COMMAND

DEVICE

STATE

CKEN-1 CKEN DQM

BA A10 A9-0

RAS CAS

Bank Active

Idle H X

Bank Precharge

Any H X

Precharge All

Any H X

Write

Active (3)

Write with Auto
Precharge

Active (3)

Read

Active (3)

Read with Auto
Precharge

Active (3)

Mode Register Set

Idle H X

No-Operation

Any H X

Burst Stop

Active (4)

Device Deselect

Any H X

Auto Refresh

Idle H H

Self Refresh Entry

Idle H L

Self Refresh Exit

Idle

(S.R)

L
L

H
H

X
X

X
H

X
X

Clock Suspend Mode
Entry

Active H L X

Power Down Mode
Entry

Idle

Active (5)

H
H

L
L

X
X

X
H

X
X

Clock Suspend Mode
Exit

Active L H

Power Down Mode Exit

Any

(Power

down)

L
L

H
H

X
X

X
H

X
X

Data Write/Output
Enable

Active H X L

Data Write/Output
Disable

Active H X H

Notes:
(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

8. ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL

RATING

UNIT

NOTES

Input, Output Voltage

, V

OUT

-0.3

- 4.6

V 1

Power Supply Voltage

, V

DDQ

-0.3

- 4.6

V 1

Operating Temperature

OPR

- 70

°C 1

Storage Temperature

STG

-55

- 150

°C 1

Soldering Temperature (10s)

SOLDER

260 °C 1

Power Dissipation

Short Circuit Output Current

OUT

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

9. RECOMMENDED DC OPERATING CONDITIONS

= 0 to 70°C)

PARAMETER SYM.

MIN.

TYP.

MAX.

UNIT

NOTES

Power Supply Voltage

2.7 3.3 3.6 V 2

Power Supply Voltage (for I/O Buffer)

DDQ

2.7 3.3 3.6

Input High Voltage

2.0 -

+0.3

Input Low Voltage

-0.3 - 0.8 V 2

Note

(max.) = V

DDQ

+1.2V for pulse width < 5 nS

(min.) = V

SSQ

-1.2V for pulse width < 5 nS

10. CAPACITANCE

= 3.3V, T

= 25

°C, f = 1MHz)

PARAMETER SYM.

MIN.

MAX.

UNIT

Input Capacitance (A0 to A10, BA,

RAS

CAS

, UDQM, LDQM, CKE)

- 4

Input Capacitance (CLK)

Input/Output Capacitance (DQ0 to DQ15)

- 6.5

Note: These parameters are periodically sampled and not 100% tested

W9816G6BB

- 14 -

11. DC CHARACTERISTICS

= 2.7

- 3.6V, T

= 0

° - 70°C)

PARAMETER SYMBOL

-7

MAX.

UNIT NOTES

Operating Current
t

= min., t

= min.

Active precharge command cycling
without burst operation

1 bank operation

CC1

50 3

CKE = V

CC2

25 3

Standby Current
t

= min., CS

= V

/L = V

(min.) /V

(max.)

Bank: inactive state

CKE = V

(Power down mode)

CC2P

1 3

CKE = V

CC2S

Standby Current
CLK = V

, CS

= V

/L = V

(min.) /V

(max.)

Bank: inactive state

CKE = V

(Power down mode)

CC2PS

1 mA

CKE = V

CC3

No Operating Current
t

= min., CS

= V

(min.)

Bank: active state (2 banks)

CKE = V

(Power Down mode)

CC3P

Burst Operating Current (t

= min.)

Read/ Write command cycling

CC4

100 3,

Auto Refresh Current (t

= min.)

Auto refresh command cycling

CC5

50 3

Standard

CC6

1.5

Self Refresh Current
(CKE = 0.2V)
Self refresh mode

Low Power

CC6L

200

µA

PARAMETER SYMBOL

MIN.

MAX.

UNIT

NOTES

Input Leakage Current

(0V

, all other pins not under test = 0V)

I(L)

-5 5

µA

Output Leakage Current

(Output disable , 0V

OUT

DDQ

)

O(L)

-5 5

µA

LVTTL OutputT

Level Voltage

OUT

= -2 mA)

2.4 - V

LVTTL Output

Level Voltage

OUT

= 2 mA)

- 0.4 V

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

12. AC CHARACTERISTICS

= 3.3V

±0.3V, V

= 0V, T

= 0 to 70

°C, Notes: 5, 6, 7, 8)

-7

PARAMETER SYM.

MIN. MAX.

UNIT

Ref/Active to Ref/Active Command Period

Active to Precharge Command Period

RAS

45 100000

Active to Read/Write Command Delay Time

RCD

Read/Write(a) to Read/Write(b)Command Period

CCD

Cycle

Precharge to Active(b) Command Period

Active(a) to Active(b) Command Period

RPD

CL* = 2

Write Recovery Time

CL* = 3

CL* = 2

1000

CLK Cycle Time

CL* = 3

7 1000

CLK High Level Width

CLK Low Level Width

CL* = 2

5.5

Access Time from CLK

CL* = 3

Output Data Hold Time

2.5

Output Data High Impedance Time

2.5 7

Output Data Low Impedance Time

Power Down Mode Entry Time

0 7

Transition Time of CLK (Rise and Fall)

0.5 10

Data-in-Set-up Time

1.5

Data-in Hold Time

Address Set-up Time

1.5

Address Hold Time

CKE Set-up Time

CKS

1.5

CKE Hold Time

CKH

Command Set-up Time

CMS

1.5

Command Hold Time

CMH

Refresh Time

REF

Mode Register Set Cycle Time

RSC

(L):For low power

W9816G6BB

- 16 -

Notes:

Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.

All voltages are referenced to V

SS.

These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values
of tCK and tRC.

These parameters depend on the output loading conditions. Specified values are obtained with output open.

Power up sequence is further described in the "Functional Description" section.

AC test conditions.

PARAMETER CONDITIONS

Output Reference Level

1.4V/1.4V

Output Load

See diagram below

Input Signal Levels

2.4V/0.4V

Transition Time (Rise and Fall) of Input Signal

2 nS

Input Reference Level

1.4V

50 ohms

1.4 V

Z = 50 ohms

output

AC TEST LOAD

30pF

Transition times are measured between V

and V

tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.

W9816G6BB

Publication Release Date: January 2, 2003

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Revision A1

Timing Waveforms, continued

Control Timing of Input/Output Data

CMH

CMS

CMH

CMS

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

CKH

CKS

CKH

CKS

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

CMH

CMS

CMH

CMS

OPEN

CKH

CKS

CKH

CKS

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

CLK

DQM

DQ0 -15

(Word Mask)

(Clock Mask)

CLK

CKE

DQ0 -15

CLK

Input Data

Output Data

(Output Enable)

(Clock Mask)

DQM

DQ0 -15

CKE

CLK

DQ0 -15

W9816G6BB

Publication Release Date: January 2, 2003

- 35 -

Revision A1

Timing Waveforms, continued

Auto Precharge Timing

(Read Cycle)

Read

Act

Read

Act

Read

Act

(1) CAS Latency=2

Read

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least t

RAS

(min).

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

Note:

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Read

Act

Read

Act

Read

Act

Read

Act

(2) CAS Latency=3

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

W9816G6BB

- 36 -

Timing Waveforms, continued

Auto Precharge Timing

(Write Cycle)

Act

Write

Act

Write

Act

Write

(1) CAS Latency = 2

(2) CAS Latency = 3

Write

Act

When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS

(min) .

represents the Write with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

Note:

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

W9816G6BB

Publication Release Date: January 2, 2003

- 37 -

Revision A1

Timing Waveforms, continued

Timing Chart of Write-to-Read Cycle

In the case of Burst Length = 4

Read

Write

( a ) Command

( b ) Command

DQM

(2) CAS Latency = 3

Read

Write

Read

Write

( a ) Command

DQM

( b ) Command

DQM

(1) CAS Latency = 2

Timing Chart of Burst Stop Cycle

(Burst Stop Command)

Read

BST

Read

BST

( a ) CAS latency =2

Command

( b ) CAS latency = 3

Command

(3) Read cycle

Write

BST

Command

(2) Write cycle

Note:

represents the Burst stop command

BST

W9816G6BB

Publication Release Date: January 2, 2003

- 43 -

Revision A1

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

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