W9864G2DB
512K
4 BANKS 32 BITS SDRAM
Publication Release Date: January 27, 2003
- 1 -
Revision A1
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. AVAILABLE PART NUMBER.............................................................................................................. 3
4. PIN CONFIGURATION ....................................................................................................................... 4
5. PIN DESCRIPTION............................................................................................................................. 5
6. BLOCK DIAGRAM .............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
Power Up and Initialization................................................................................................................ 7
Programming Mode Register ............................................................................................................ 7
Bank Activate Command................................................................................................................... 7
Read and Write Access Modes......................................................................................................... 7
Burst Read Command....................................................................................................................... 8
Burst Command ................................................................................................................................ 8
Read Interrupted by a Read.............................................................................................................. 8
Read Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Read .............................................................................................................. 8
Burst Stop Command........................................................................................................................ 8
Addressing Sequence of Sequential Mode....................................................................................... 9
Addressing Sequence of Interleave Mode ........................................................................................ 9
Auto-precharge Command.............................................................................................................. 10
Precharge Command ...................................................................................................................... 10
Self Refresh Command................................................................................................................... 10
Power Down Mode.......................................................................................................................... 10
No Operation Command ................................................................................................................. 11
Deselect Command......................................................................................................................... 11
Clock Suspend Mode ...................................................................................................................... 11
Table of Operating Modes............................................................................................................... 12
Simplified State Diagram................................................................................................................. 13
8. DC CHARACTERISTICS .................................................................................................................. 14
Absolute Maximum Rating .............................................................................................................. 14
Recommended DC Operating Conditions....................................................................................... 14
Capacitance .................................................................................................................................... 14
W9864G2DB
- 2 -
DC Characteristics .......................................................................................................................... 15
9. AC CHARACTERISTICS .................................................................................................................. 16
10. TIMING WAVEFORMS ................................................................................................................... 19
Command Input Timing................................................................................................................... 19
Read Timing .................................................................................................................................... 20
Control Timing of Input Data ........................................................................................................... 21
Control Timing of Output Data ........................................................................................................ 22
Mode Register Set Cycle ................................................................................................................ 23
11. OPERATING TIMING EXAMPLE.................................................................................................... 24
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................ 24
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) .............................. 25
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................ 26
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) .............................. 27
Interleaved Bank Write (Burst Length = 8)...................................................................................... 28
Interleaved Bank Write (Burst Length = 8, Autoprecharge)............................................................ 29
Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................................. 30
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ....................................................... 31
Autoprecharge Read (Burst Length = 4, CAS Latency = 3)............................................................ 32
Autoprecharge Write (Burst Length = 4) ......................................................................................... 33
Autorefresh Cycle............................................................................................................................ 34
Self-refresh Cycle............................................................................................................................ 35
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)................................................. 36
Power-down Mode .......................................................................................................................... 37
Auto-precharge Timing (Write Cycle).............................................................................................. 38
Auto-precharge Timing (Read Cycle) ............................................................................................. 39
Timing Chart of Read to Write Cycle............................................................................................... 40
Timing Chart of Write to Read Cycle............................................................................................... 41
Timing Chart of Burst Stop Cycle (Burst Stop Command).............................................................. 42
Timing Chart of Burst Stop Cycle (Precharge Command).............................................................. 43
CKE/DQM Input Timing (Write Cycle)............................................................................................. 44
CKE/DQM Input Timing (Read Cycle) ............................................................................................ 45
Self Refresh/Power Down Mode Exit Timing .................................................................................. 46
12. PACKAGE DIMENSIONS ............................................................................................................... 47
TFBGA 90 Balls Pitch = 0.8 mm ..................................................................................................... 47
13. VERSION HISTORY ....................................................................................................................... 48
W9864G2DB
Publication Release Date: January 27, 2003
- 3 -
Revision A1
1. GENERAL DESCRIPTION
W9864G2DB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
4 banks 32 bits. Using pipelined architecture and 0.175 m process technology,
W9864G2DB delivers a data bandwidth of up to 286M bytes per second (-7).
W9864G2DB -7.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G2DB is ideal for main memory in
high performance applications.
2. FEATURES
2.7V
- 3.6V power supply
524288 words
4 banks 32 bits organization
Self refresh current: Standard and low power
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/ 64 mS
Interface: LVTTL
Packaged in
TFBGA
90 balls pitch = 0.8 mm using PB free materials
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED (CL = 3)
SELF REFRESH CURRENT (MAX.)
W9864G2DB-7
143 MHz
1 mA
W9864G2DB
- 4 -
4. PIN CONFIGURATION
CKE
A8
A6
DQ23
A4
CLK
A9
A7
A5
WE#
CAS#
CS#
BS0
A10
A1
A3
DQM0
RAS#
BS1
A0
A2
1
2
6
5
7
9
8
4
3
C
B
A
P
N
G
D
E
M
H
L
F
K
R
J
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
NC
NC
NC/A11
NC/A12
NC
DQM2
DQ21
DQ19
DQ20
DQ22
DQ18
DQ17
DQ16
DQ7
DQ6
DQ5
DQ1
DQ3
DQ4
DQ0
DQ2
VSS
VSS
VSS
VSS DQM3
DQM1
DQ26 DQ24
DQ28
DQ27 DQ25
DQ29 DQ30
DQ31
DQ15
DQ13
DQ11
DQ12 DQ14
DQ10
DQ9
DQ8
NC
NC
Top View
W9864G2DB
Publication Release Date: January 27, 2003
- 5 -
Revision A1
5. PIN DESCRIPTION
BALL LOCATION
PIN NAME
FUNCTION
DESCRIPTION
G1
- G3, G7 - G9,
F7, F3, H1, H2, J3
A0
- A10
Address
Multiplexed pins for row and column address. Row
address: A0
- A10. Column address: A0 - A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
J7, H8
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
A1, A2, A8, A9, B1,
B9, C2, C3, C7, C8,
D2, D3, D7, D8, E2,
E8, L2, L8, M2, M3,
M7, M8, N2, N3, N7,
N8, P1, P9, R1, R2,
R8, R9
DQ0
-
DQ31
Data Input/
Output
Multiplexed pins for data output and input.
J8
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
J9
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
K7
CAS
Column Address
Strobe
Referred to RAS
K8
WE
Write Enable
Referred to RAS
K9, K1, F8, F2
DQM0
- 3
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with
zero latency.
J1 CLK
Clock
Inputs
System clock used to sample inputs on the rising edge of
clock.
J2 CKE
Clock
Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
A7, F9, L7, R7
V
DD
Power (+3.3V)
Power for input buffers and logic circuit inside DRAM.
A3, F1, L3, R3
V
SS
Ground
Ground for input buffers and logic circuit inside DRAM.
B2, B7, C9, D9, E1,
L1, M9, N9, P2,
V
DD
Q
Power (+3.3V)
for I/O Buffer
Separated power from V
DD
, to improve DQ noise
immunity.
B8, B3, C1, D1, E9,
L9, M1, N1, P8,
V
SS
Q
Ground for I/O
Buffer
Separated ground from V
SS
, to improve DQ noise
immunity.
E3, E7, H3, H7, H9,
K2, K3
NC
No Connection No connection
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