WM2613
Byte-wide Parallel Input, 12-bit Voltage Output DAC
Production Data, June 1999, Rev 1.0
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and conditions.
Master rev 1.0.doc June 17, 1999 14:12
1999 Wolfson Microelectronics Ltd
.
FEATURES
Dual 12-bit voltage output DAC
Dual supply 2.7V to 5.5V operation
DNL
0.4 LSB, INL
1.5 LSB
Programmable settling time 1
s or 3
s typical
8-bit micro controller compatible interface
Power down mode (10nA)
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2613CDT
0
to 70
C
20-pin TSSOP
WM2613IDT
-40
to 85
C
20-pin TSSOP
DESCRIPTION
The WM2613 is a 12-bit voltage output, resistor string, digital-to-
analogue converter. The DAC can be powered down under
software or hardware control, reducing power consumption to
10nA.
The device has an 8-bit microcontroller compatible parallel
interface. The eight data LSBs, the four data MSBs, and the three
control bits are written using three different addresses.
Excellent performance is delivered with a typical DNL of 0.4 LSBs.
The output stage is buffered by a x2 gain near rail-to-rail amplifier,
which features a Class A output stage (slow mode, class AB). The
settling time of the DAC is software programmable to allow the
designer to optimize speed versus power dissipation.
The device is available in a 20-pin TSSOP package. Commercial
temperature (0 to 70C) and Industrial temperature (-40 to 85C)
variants are supported.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
(13) OUT
3-BIT
CONTROL
LATCH
REFIN(12)
POWER-ON
RESET
NWE (17)
(14)
GND
DVDD
(10)
REFERENCE
INPUT BUFFER
WM2613
DAC
OUTPUT
BUFFER
NCS (18)
A[0-1] (8,7)
D[0-7]
(19,20, 1-6)
4-BIT DAC
MSW
HOLDING
LATCH
8-BIT DAC
LSW
HOLDING
LATCH
X1
POWERDOWN/
SPEED
CONTROL
X2
(16)
NLDAC
AVDD
(11)
PARALLEL
INTERFACE
AND
CONTROL
LOGIC
SPD (9)
NPD (15)
12-BIT DAC
LATCH
AVDD = DVDD = 5V, V
REF
= 2.048V, Speed = Fast mode, Load = 10k/100pF
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
DNL - LSB
WM2613
Production Data Rev 1.0
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
2
PIN CONFIGURATION
9
10
SPD
DVDD
12
11
REFIN
AVDD
20
13
14
15
16
17
18
19
D1
GND
NPD
NLDAC
NWE
NCS
D0
OUT
8
1
2
3
4
5
6
7
A0
D3
D4
D5
D6
D7
A1
D2
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
D2
Digital input
Data input.
2
D3
Digital input
Data input.
3
D4
Digital input
Data input.
4
D5
Digital input
Data input.
5
D6
Digital input
Data input.
6
D7
Digital input
Data input.
7
A1
Digital input
Address input.
8
A0
Digital input
Address input.
9
SPD
Digital input
Speed select. Digital input.
10
DVDD
Supply
Digital positive power supply.
11
AVDD
Supply
Analogue positive power supply.
12
REFIN
Analogue input
Voltage reference input.
13
OUT
Analogue output
DAC analogue voltage output.
14
GND
Supply
Ground.
15
NPD
Digital input
Power down. Active low digital input which powers down all analogue
circuits.
16
NLDAC
Digital input
Load DAC. Digital input active low. NLDAC must be taken low to update
the DAC latch from the holding latches.
17
NWE
Digital input
Write enable. Digital input active low.
18
NCS
Digital input
Chip select. Digital input active low.
19
D0
Digital input
Data input.
20
D1
Digital input
Data input.
Production Data
WM2613
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
Supply voltages, AVDD or DVDD to GND
7V
Supply voltage differences, AVDD to DVDD
-2.8V
2.8V
Reference input voltage
-0.3V
DVDD + 0.3V
Digital input voltage range to GND
-0.3V
AVDD + 0.3V
Operating temperature range, T
A
WM2613C
WM2613I
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
AVDD, DVDD
2.7
5.5
V
High-level digital input voltage
V
IH
DVDD = 2.7V to 5.5V
2
V
Low-level digital input voltage
V
IL
DVDD = 2.7V to 5.5V
0.8
V
Reference voltage to REFIN
V
REF
See Note
AVDD - 1.5
V
Load resistance
R
L
2
k
Load capacitance
C
L
100
pF
WM2613CDT
0
70
C
Operating free-air temperature
T
A
WM2613IDT
-40
85
C
Note: Reference voltages greater than AVDD/2 will cause saturation for large DAC codes.
WM2613
Production Data Rev 1.0
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
4
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. AVDD = DVDD = 5V
10%, V
REF
= 2.048V and AVDD = DVDD = 3V
10%, V
REF
= 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
12
bits
Integral non-linearity
INL
See Note 1
1.5
4
LSB
Differential non-linearity
DNL
See Note 2
0.4
1
LSB
Zero code error
ZCE
See Note 3
3
20
mV
Gain error
GE
See Note 4
0.25
0.5
% FSR
D.c power supply rejection ratio
d.c. PSRR
See Note 5
0.5
mV/V
Zero code error temperature
coefficient
See Note 6
3
ppm/
C
Gain error temperature coefficient
See Note 6
1
ppm/
C
DAC Output Specifications
Output voltage range
0
AVDD - 0.4
V
Output load regulation
2k
to 10k
load. See Note 7
0.1
0.3
%
Power Supplies
Active supply current
IDD
No load, VIH = DVDD, VIL = 0V
AVDD = DVDD = 5V,
V
REF
= 2.048V See Note 8
Slow
Fast
AVDD = DVDD = 3V,
V
REF
= 1.024V
Slow
Fast
0.5
1.6
0.4
1.4
1.3
3.0
1.1
2.7
mA
mA
mA
mA
Power down supply current
No load, all digital inputs 0V
or DVDD. See Note 9
0.01
10
A
Dynamic DAC Specifications
Slew rate
DAC code 128 to 4095,
10%-90% See Note 10
Slow
Fast
1.5
8
V/
s
V/
s
Settling time
DAC code 128 to 4095
Slow
Fast
3.5
1.0
s
s
Glitch energy
Code 2047 to code 2048
1
nV-s
Signal to noise ratio
SNR
f
S
= 480ksps,
f
OUT
= 1kHz BW = 20kHz,
TA = 25
C See Note 12
65
78
dB
Signal to noise and distortion ratio
SNRD
f
S
= 480ksps,
f
OUT
= 1kHz BW = 20kHz,
TA = 25
C See Note 12
58
69
dB
Total harmonic distortion
THD
f
S
= 480ksps,
f
OUT
= 1kHz BW = 20kHz,
TA = 25
C See Note 12
-68
-60
dB
Spurious free dynamic range
SPFDR
f
S
= 480ksps,
f
OUT
= 1kHz BW = 20kHz, T
A
=
25
C See Note 12
60
72
dB
Production Data
WM2613
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
5
Test Conditions:
R
L
= 10k
, C
L
= 100pF. AVDD = DVDD = 5V
10%, V
REF
= 2.048V and AVDD = DVDD = 3V
10%, V
REF
= 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Reference
Reference input resistance
RREFIN
10
M
Reference input capacitance
CREFIN
5
pF
Reference feedthrough
VREF = 1V
PP
at 1kHz
+ 1.024V d.c., DAC code 0
-60
dB
Reference input bandwidth
VREF = 0.2V
PP
+ 1.024V d.c.
DAC code 2048
Slow
Fast
1
1.6
MHz
MHz
Digital Inputs
High level input current
I
IH
Input voltage = DVDD
1
A
Low level input current
I
IL
Input voltage = 0V
-1
A
Input capacitance
C
I
8
pF
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the
effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is expressed as a percentage of the full scale output voltage with a 10k
load.
8. I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< DVDD - 0.7V and V
IL
> 0.7V supply current
will increase.
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
OUT
generated with
a sampling frequency f
S
.
PDF 
ZIP