WM2614

Quad 12-bit Serial Input Voltage Output DAC

Production Data, June 1999, Rev 1.0

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson

Microelectronics' terms and conditions.

2614Mastera.doc June 18, 1999 14:36

1999 Wolfson Microelectronics Ltd

FEATURES

Quad 12-bit DAC voltage output DAC

Dual 2.7V to 5.5V supply (separate digital and analogue

supplies)

DNL

±
±

0.4 LSB, INL

±
±

1.5 LSB

Low power consumption:

- 5.5mW, slow mode

-
-

5V supply

- 3.3mW, slow mode

-
-

3V supply

TMS320, (Q)SPI

, and Microwire

compatible serial

interface

Programmable settling time of 4

µ
µ

s or 12

µ
µ

s typical

APPLICATIONS

Battery powered test instruments

Digital offset and gain adjustment

Battery operated/remote industrial controls

Machine and motion control devices

Wireless telephone and communication systems

Speech synthesis

Arbitrary waveform generation

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2614CDT 0° to 70°C 16-pin TSSOP

WM2614IDT -40° to 85 °C 16-pin TSSOP

DESCRIPTION

The WM2614 is a quadruple 12-bit voltage output, resistor string,
digital-to-analogue converter. Each DAC can be individually
powered down under software control. A hardware controlled mode
is provided that powers down all DACs. Power down reduces
current consumption to 10nA.

The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2614 is programmed with a 16-bit serial word
comprising of a DAC address, individual DAC control bits and a
12-bit value.

The WM2614 has provision for two supplies: one supply for the
serial interface (DVDD, DGND) and one for the DACs, reference
buffers and output buffers (AVDD, AGND). This enables a typical
application where the device can be controlled via a
microprocessor operating on a 3V supply, with the DACs operating
on a 5V supply. Alternatively, the supplies can be tied together in a
single supply application.

Excellent performance is delivered with a typical DNL of 0.4 LSBs.
The settling time of the DAC is programmable to allow the designer
to optimize speed versus power dissipation. The output stage is
buffered by a x2 gain near rail-to-rail amplifier, which features a
Class AB output stage. DACs A and B can have a different
reference voltage to DACs C and D.

The device is available in a 16-pin TSSOP package.
Commercial temperature (0

to 70

C) and Industrial

temperature (-40

to 85

C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

(11) OUTD

(12) OUTC

(13) OUTB

(14) OUTA

14-BIT

DATA AND
CONTROL

HOLDING

LATCH

12-BIT

DAC

LATCH

16-BIT
SHIFT

REGISTER

AND

CONTROL

LOGIC

REFINAB (15)

POWER-ON

RESET

DIN (4)

FS (7)

SCLK (5)

NCS (6)

(9)

AGND

(8)

DGND

(3)

NLDAC

(2)

NPD

AVDD

(16)

DVDD

(1)

DAC A

DAC C

DAC D

POWERDOWN/

SPEED

CONTROL

WM2614

2-BIT

CONTROL

LATCH

REFINCD (10)

DAC B

DAC

OUTPUT
BUFFER

data

REFERENCE

INPUT BUFFER

AVDD = DVDD = 5V, V

REF

= 2.048V, Speed = Fast mode, Load = 10k/100pF

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2559 3071 3583 4095

DIGITAL CODE

DNL (LSB)

WM2614

Production Data Rev 1.0

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June

1999

PIN CONFIGURATION

REFINCD

OUTD

OUTC

OUTB

OUTA

AVDD

REFINAB

NCS

SCLK

DIN

NLDAC

DVDD

NPD

DGND

AGND

PIN DESCRIPTION

PIN NO

NAME

TYPE

DESCRIPTION

DVDD

Supply

Digital supply.

NPD

Digital input

Power down. Powers down all DACs overriding their individual power down settings
and all output stages. This pin is active low.

NLDAC

Digital input

Load DAC. Digital input active low. NLDAC must be taken low to update the DAC
latch from the holding latches.

DIN

Digital input

Serial data input.

SCLK

Digital input

Serial clock input.

NCS

Digital input

Chip select. This pin is active low.

Digital input

Frame synchronisation for serial output data.

DGND

Ground

Digital ground.

AGND

Ground

Analogue ground.

REFINCD

Analogue input

Voltage reference input for DACs C and D.

OUTD

Analogue output

DAC D output.

OUTC

Analogue output

DAC C output.

OUTB

Analogue output

DAC B output.

OUTA

Analogue output

DAC A output.

REFINAB

Analogue input

Voltage reference input for DACs A and B.

AVDD

Supply

Analogue supply.

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.

CONDITION

MIN

MAX

Supply voltages, DVDD to DGND, AVDD to AGND

Supply voltage differences, AVDD to DVDD

-2.8V

2.8V

Digital input voltage

-0.3V

DVDD + 0.3V

Reference input voltage

-0.3V

AVDD + 0.3V

Operating temperature range, T

WM2614CDT

WM2614IDT

-40

Storage temperature

-65

150

Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

260

WM2614

Production Data Rev 1.0

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June

1999

ELECTRICAL CHARACTERISTICS

Test Conditions:
R

= 10k

, C

= 100pF. AVDD = DVDD

= 5V

±
±

10%, V

REF

= 2.048V and AVDD = DVDD

= 3V

±
±

10%, V

REF

= 1.024V over

recommended operating free-air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Static DAC Specifications

Resolution

bits

Integral non-linearity

INL

See Note 1

±
±

1.5

±
±

LSB

Differential non-linearity

DNL

See Note 2

±
±

0.4

±
±

LSB

Zero code error

ZCE

See Note 3

±
±

Gain error

See Note 4

0.25

±
±

0.6

% FSR

D.c. power supply rejection ratio

d.c. PSRR

See Note 5

0.5

mV/V

Zero code error temperature coefficient

See Note 6

ppm/

Gain error temperature coefficient

See Note 6

ppm/

DAC Output Specifications

Output voltage range

AVDD - 0.1

Output load regulation

to 10k

load

See Note 7

0.1

0.25

Power Supplies

No load, V

= DVDD, V

= 0V

AVDD = 5V, V

REF

= 2.048V Slow

1.6

2.4

AVDD = 5V, V

REF

= 2.048V Fast

3.8

5.6

AVDD = 3V, V

REF

= 1.024V Slow

1.2

1.8

Active supply current

AVDD = 3V, V

REF

= 1.024V Fast

See Note 8

3.2

4.8

Power down supply current

No load,

all digital inputs 0V or DVDD

See Note 9

0.01

Dynamic DAC Specifications

Slew rate

DAC code 128 to 4095, 10%-90%

Slow

Fast

See Note 10

0.5

2.5

1.0

4.0

Settling time

DAC code 128 to 4095

Slow

Fast

See Note 11

12.0

4.0

Glitch energy

Code 2047 to 2048

nV-s

Signal to noise ratio

SNR

fs = 400ksps, f

OUT

= 1kHz,

BW = 20kHz,

See Note 12

Signal to noise and distortion ratio

SNRD

fs = 400ksps, f

OUT

= 1kHz,

BW = 20kHz,

See Note 12

Total harmonic distortion

THD

= 400ksps, f

OUT

= 1kHz,

BW = 20kHz,

See Note 12

-68

-56

Spurious free dynamic range

SPFDR

= 400ksps, f

OUT

= 1kHz,

BW = 20kHz,

See Note 12

Production

Data Rev 1.0

WM2614

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June

1999

Test Conditions:
R

= 10k

, C

= 100pF. AVDD = DVDD

= 5V

±
±

10%, V

REF

= 2.048V and AVDD = DVDD

= 3V

±
±

10%, V

REF

= 1.024V over

recommended operating free-air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference

Reference input resistance

REFIN

Reference input capacitance

REFIN

Reference feedthrough

REF

= 1V

at 1kHz

+ 1.024V dc, DAC code 0

-75

Reference input bandwidth

REF

= 0.2V

+ 1.024V dc

DAC code 2048

Slow

Fast

0.5

MHz

Digital Inputs

High level input current

Input voltage = DVDD

Low level input current

Input voltage = 0V

-1

Input capacitance

Notes:

Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full scale errors).

Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in
digital input code.

Zero code error is the voltage output when the DAC input code is zero.

Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed
on the zero code error and the gain error.

Zero code error and Gain error temperature coefficients are normalised to V

REF

Output load regulation is the difference between the output voltage at full scale with a 10k

load and 2k

load. It is expressed as a

percentage of the full scale output voltage with a 10k

load.

is measured while continuously writing code 2048 to the DAC. For V

< DVDD - 0.7V and V

> 0.7V supply current will increase.

Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10.

Slew rate results are for the lower value of the rising and falling edge slew rates.

11.

Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges.
Limits are ensured by design and characterisation, but are not production tested.

12.

SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

OUT

generated with a sampling frequency fs.

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