Document Outline
- WM2624
- Low Power 8-bit Serial Input DAC with Internal Reference
- Production Data, November 2000, Rev 1.0
- FEATURES
- DESCRIPTION
- APPLICATIONS
- ORDERING INFORMATION
- BLOCK DIAGRAM
- TYPICAL PERFORMANCE
- PIN CONFIGURATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- SERIAL INTERFACE
- TYPICAL PERFORMANCE GRAPHS
- DEVICE DESCRIPTION
- GENERAL FUNCTION
- SERIAL INTERFACE
- SOFTWARE CONFIGURATION OPTIONS
- APPLICATIONS INFORMATION
- LINEARITY, OFFSET, AND GAIN ERROR
- POWER SUPPLY DECOUPLING AND GROUNDING
- PACKAGE DIMENSIONS
WM2624
Low Power 8-bit Serial Input DAC
with Internal Reference
Production Data, November 2000, Rev 1.0
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and conditions.
2000 Wolfson Microelectronics Ltd
.
FEATURES
8-bit Voltage Output DAC
Single Supply from 2.7V to 5.5V
Very Low Supply Current:
-
1.5 mA in Slow Mode
-
2.3 mA in Fast Mode
DNL
0.2 LSB, INL
0.5 LSB (max)
Monotonic over Temperature
DSP Compatible Serial Interface
Programmable Settling Time of 1
s or 3.5
s Typical
Reference Output Buffer can Supply up to 1mA
APPLICATIONS
Digital Servo Control Loops
Industrial Process Control
Battery Powered Instruments and Controls
Machine and Motion Control Devices
Digital Offset and Gain Adjustment
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2624CD
0 to 70C
8-pin SOIC
WM2624ID
-40 to 85C
8-pin SOIC
DESCRIPTION
The WM2624 is an 8-bit voltage output, resistor string digital-to-
analogue converter. It can operate with supply voltages
between 2.7V and 5.5V and can be powered down under
software control. Power down reduces current consumption to
10nA.
The device has been designed for glueless interface to industry
standard microprocessors and DSPs. The WM2624 is
programmed with a 16-bit serial word including 4 control bits
and 8 data bits.
Excellent performance is delivered with a maximum DNL of
0.2LSBs. Monotonicity is guaranteed over the operating
temperature range. The settling time of the DAC is
programmable to allow for optimisation of speed versus power
dissipation. The output stage is buffered by a rail-to-rail amplifier
with a gain of two, which features a Class AB output stage.
The on-chip voltage reference is available to external circuitry
through the REF pin. It is buffered and can supply up to 1mA.
Alternatively, an external reference can be used. A high
impedance reference input buffer is included on the chip to
interface to external references, whose source impedance may
be high.
The WM2623 is available in an 8-pin SOIC package.
Commercial (0
to 70
C) and Industrial (-40
to 85
C)
temperature range variants are available.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
(7) OUT
8-BIT
DAC
LATCH
POWER-ON
RESET
DIN (1)
SCLK (2)
FS (4)
(5)
GND
VDD
(8)
POWERDOWN/
SPEED
CONTROL
2-BIT
CONTROL
LATCH
REFERENCE
INPUT BUFFER
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
data
X1
X2
DAC
OUTPUT
BUFFER
CSB (3)
2-BIT
REFERENCE
SELECT
LATCH
1.024V/2.048V
SELECTABLE
REFERENCE
X1
REFERENCE
OUTPUT BUFFER
WITH OUPUT
ENABLE
REF(6)
WM2624
VDD = 2.7V, V
REF
= 1.024V, Speed = Fast Mode
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0
32
64
96
128
160
192
224
256
DIGITAL CODE
DNL -
Digit
a
l Non-
Line
a
r
it
y
(
L
S
B
s
)
WM2624
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
2
PIN CONFIGURATION
1
2
3
4
CSB
DIN
SCLK
GND
REF
FS
VDD
OUT
5
6
7
8
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
DIN
Digital input
Serial data input
2
SCLK
Digital input
Serial clock input
3
CSB
Digital input
Chip select. This pin is active low.
4
FS
Digital input
Frame synchronisation for serial input data
5
GND
Supply
Ground
6
REF
Analogue in/out
Voltage reference
7
OUT
Analogue output
DAC analogue output
8
VDD
Supply
Positive power supply
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Supply voltage, VDD to GND
7V
Digital input voltage
-0.3V
VDD + 0.3V
Reference input voltage
-0.3V
VDD + 0.3V
Operating temperature range, T
A
WM2624CD
WM2624ID
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) from package body for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
V
IH
VDD = 2.7V to 5.5V
2
V
Low-level digital input voltage
V
IL
VDD = 2.7V to 5.5V
0.8
V
Reference voltage to REF pin
V
REF
See Note
GND
VDD - 1.5
V
Load resistance
R
L
2
10
k
Load capacitance
C
L
100
pF
Serial clock frequency
f
SCLK
20
MHz
WM2624CD
0
70
C
Operating free-air temperature
T
A
WM2624ID
-40
85
C
Note: Reference input voltages greater than VDD/2 will cause clipping for large DAC codes. The reference output buffer must
be disabled if an external reference is used.
Production Data
WM2624
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
3
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V 10%, V
REF
= 2.048V and VDD
= 3V 10%, V
REF
= 1.024V over recommended operating free-
air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
8
bits
Integral non-linearity
INL
See Note 1
0.3
0.5
LSB
Differential non-linearity
DNL
See Note 2
0.07
0.2
LSB
Zero code error
ZCE
See Note 3
10
mV
Gain error
GE
See Note 4
0.6
% FSR
D.C. power supply rejection ratio
PSRR
See Note 5
-65
dB
Zero code error temperature coefficient
See Note 6
10
ppm/
C
Gain error temperature coefficient
See Note 6
10
ppm/
C
DAC Output Specifications
Output voltage range
0
VDD
V
Output load regulation
2k
to 10k
load
See Note 7
0.1
0.25
% FS
Power Supplies
No load, DAC value = 128,
all digital inputs 0V or VDD
Active supply current
I
DD
Fast
Slow
2.3
1.5
3.3
1.9
mA
mA
Power down supply current
10
nA
Dynamic DAC Specifications
Slew rate
SR
DAC output 10% to 90%
Slow
Fast
See Note 8
1.5
8
V/
s
V/
s
Settling time
t
s
DAC output 10% to 90%
Slow
Fast
See Note 9
3.5
1
7
3
s
s
Glitch energy
DIN = 0 to 1, f
CLK
= 100kHz
5
nV-s
Signal to noise ratio
SNR
53
57
dB
Signal to noise and distortion ratio
SNRD
47
48
dB
Total harmonic distortion
THD
-50
-48
dB
Spurious free dynamic range
SFDR
f
s
= 480KSPS,
f
OUT
= 1kHz,
Load = 10k
/ 100pF
See Note 10
50
62
dB
Reference Output (Internal Reference)
Low reference voltage
V
REFL
1.003
1.024
1.045
V
High reference voltage
V
REFH
V
DD
> 4.75V
2.027
2.048
2.069
V
Output Source/Sink Current
I
REF
1
mA
Load capacitance
100
pF
Reference Input (External Reference)
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
5
pF
Reference feedthrough
V
REF
= 1V
PP
at 1kHz
+ 1.024V DC, DAC code 0
-80
dB
Reference input bandwidth
V
REF
= 0.2V
PP
+ 1.024V DC
DAC code 128
Slow
Fast
0.525
1.3
MHz
MHz
WM2624
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
4
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V 10%, V
REF
= 2.048V and VDD
= 3V 10%, V
REF
= 1.024V over recommended operating free-
air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
A
Low level input current
I
IL
Input voltage = 0V
1
A
Input capacitance
C
I
8
pF
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as
the digital input code.
3.
Zero code error is the voltage output when the DAC input code is zero.
4.
Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6.
Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7.
Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is
expressed as a percentage of the full scale output voltage with a 10k
load.
8.
Slew rate results are for the lower value of the rising and falling edge slew rates
9.
Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
10. SNR, SNRD, THD and SPFDR are measured on a synthesised sine wave at frequency f
OUT
generated with a sampling
frequency fs
.
Production Data
WM2624
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
5
SERIAL INTERFACE
t
SUC16FS
t
SUFS
SCLK
DIN
NCS
FS
1
2
3
4
5
15
16
D0
D1
D12
D13
D14
D15
t
WL
t
WH
t
SUD
t
HD
t
SUCSFS
t
WHFS
t
SUC16CS
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSFS
Setup time CSB low before falling FS edge.
10
ns
t
SUFS
Setup time FS low before first falling SCLK edge.
8
ns
t
SUC16FS
Setup time, 16
th
falling SCLK edge after FS low on
which data bit D0 is sampled before rising edge of FS.
10
ns
t
SUC16CS
Setup time, 16
th
rising SCLK edge (first after data bit
D0 sampled) before CSB rising edge. If FS is used
instead of the 16
th
rising edge to update the DAC, this
setup time is between the FS rising edge and the CSB
rising edge.
10
ns
t
WH
Pulse duration, SCLK high.
25
ns
t
WL
Pulse duration, SCLK low.
25
ns
t
SUD
Setup time, data ready before SCLK falling edge.
8
ns
t
HD
Hold time, data held valid after SCLK falling edge.
5
ns
t
WHFS
Pulse duration, FS high.
25
ns
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