Document Outline
- WM2629
- Octal 8-bit, Serial Input, Voltage Output DAC with Power Down Differential Non- Linearity
- Production Data, April 2001, Rev 1.0
- FEATURES
- DESCRIPTION
- APPLICATIONS
- ORDERING INFORMATION
- BLOCK DIAGRAM
- TYPICAL PERFORMANCE
- PIN CONFIGURATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- SERIAL INTERFACE
- TYPICAL PERFORMANCE GRAPHS
- DEVICE DESCRIPTION
- GENERAL FUNCTION
- SERIAL INTERFACE
- SOFTWARE CONFIGURATION OPTIONS
- APPLICATIONS INFORMATION
- LINEARITY, OFFSET, AND GAIN ERROR
- POWER SUPPLY DECOUPLING AND GROUNDING
- PACKAGE DIMENSIONS
WM2629
Octal 8-bit, Serial Input, Voltage Output DAC
with Power Down
Production Data, April 2001, Rev 1.0
WOLFSON MICROELECTRONICS LTD
Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
www.wolfsonmicro.com
Production Data datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and Conditions.
2001 Wolfson Microelectronics Ltd
.
FEATURES
Eight 8-bit DACs in one package
Dual supply 2.7V to 5.5V operation
DNL
0.1 LSBs, INL
0.3 LSBs typical
Programmable settling time / power
(1.0
s typical in fast mode)
Microcontroller compatible serial interface
Power down mode ( < 0.1
A)
Monotonic over temperature
Data output for daisy chaining
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated / remote industrial controls
Programmable loop controllers
CNC machine tools
Machine and motion control devices
Wireless telephone and communication systems
Robotics
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2629CDT
0
to 70
C
20-pin TSSOP
WM2629IDT
-40
to 85
C
20-pin TSSOP
DESCRIPTION
The WM2629 is an octal, 8-bit, resistor string digital-to-analogue
converter. The eight individual DACs contained in the IC can be
switched in pairs between fast and slow (low power) operation
modes, or powered down, under software control. Alternatively,
the whole device can be powered down, reducing current
consumption to less than 0.1
A.
The DAC outputs are buffered by a rail-to-rail amplifier with a
gain of two, which is configurable as Class A (fast mode) or
Class AB (for low-power mode).
The WM2629 has been designed to interface directly to industry
standard microprocessors and DSPs, and can operate on two
separate analogue and digital power supplies. It is programmed
with a 16-bit serial word comprising 4 address bits and up to 12
DAC or control register data bits. All eight DACs can be
simultaneously forced to a preset value using a preset input pin.
A daisy-chain data output makes it possible to control several of
Wolfson's octal DACs from the same interface, without
increasing the number of control lines.
The device is available in a 20-pin TSSOP package.
Commercial temperature (0 to 70C) and Industrial
temperature (-40 to 85C) variants are supported.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
LATCH
POWER/SPEED
CONTROL
RESISTOR
STRING
(12) OUT A
DAC A
DIN (2)
SCLK (3)
FS (4)
PREB (5)
DOUT (19)
DACs B, C, D, E, F, G, H
as DAC A
(6-9, 13-15)
OUT B to H
VREF/2
SERIAL
INTERFACE
AND
CONTROL
LOGIC
MODE (17)
AVDD
(11)
DVDD
(20)
AGND
(10)
DGND
(1)
LOADB
(18)
REF
(16)
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0
32
64
96
128
160
192
224
256
DIGITAL CODE
D
i
f
f
er
ent
i
al
N
on-
Li
near
i
t
y (
L
S
B
s)
WM2629
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
2
PIN CONFIGURATION
9
10
OUTH
AGND
12
11
OUTA
AVDD
20
13
14
15
16
17
18
19
DVDD
OUTC
OUTD
REF
MODE
LOADB
DOUT
OUTB
8
1
2
3
4
5
6
7
OUTG
DIN
SCLK
FS
PREB
OUTE
OUTF
DGND
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
DGND
Supply
Digital Ground
2
DIN
Digital input
Digital serial data input
3
SCLK
Digital input
Serial clock input
4
FS
Digital input
Frame sync input
5
PREB
Digital input
Preset input
6
OUTE
Analogue output
DAC Output E
7
OUTF
Analogue output
DAC Output F
8
OUTG
Analogue output
DAC Output G
9
OUTH
Analogue output
DAC Output H
10
AGND
Supply
Analogue Ground
11
AVDD
Supply
Analogue positive power supply
12
OUTA
Analogue output
DAC Output A
13
OUTB
Analogue output
DAC Output B
14
OUTC
Analogue output
DAC Output C
15
OUTD
Analogue output
DAC Output D
16
REF
Analogue I/O
Voltage reference input / output
17
MODE
Digital input
Input mode
18
LOADB
Digital input
Load DAC
19
DOUT
Digital output
Serial data output
20
DVDD
Supply
Digital positive power supply
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Digital supply voltages, AVDD or DVDD to GND
7V
Reference voltage
-0.3V
AVDD + 0.3V
Digital input voltage range to GND
-0.3V
DVDD + 0.3V
Operating temperature range, T
A
WM2629CDT
WM2629IDT
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Soldering temperature, 1.6mm (1/16 inch) from package body for 10
seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
AVDD,
DVDD
2.7
5.5
V
High-level digital input voltage
V
IH
2
V
Low-level digital input voltage
V
IL
0.8
V
AVDD = 5V
GND
4.096
AVDD
Reference voltage to REF
V
REF
AVDD = 3V
GND
2.048
AVDD
V
Output Load Resistance
R
L
2
k
Load capacitance
C
L
100
pF
WM2629CDT
0
70
C
Operating free-air temperature
T
A
WM2629IDT
-40
85
C
WM2629
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
4
ELECTRICAL CHARACTERISTICS
Test Characteristics:
Over recommended operating conditions (unless noted otherwise).
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
8
bits
Integral non-linearity
INL
Code 6 to 255 (see Note 1)
0.3
1
LSB
Differential non-linearity
DNL
Code 6 to 255 (see Note 2)
0.1
1
LSB
Zero code error
ZCE
See Note 3
30
mV
Gain error
GE
See Note 4
0.6
% FSR
DC power supply rejection ratio
PSRR
See Note 5
-60
dB
Zero code error temperature
coefficient
See Note 6
30
V/
C
Gain error temperature coefficient
See Note 6
10
ppm/
C
DAC Output Specifications
Output voltage range
10k
Load
0
AVDD-0.4
V
Output load regulation
2k
to 10k
load
See Note 7
0.3
% Full
Scale
Power Supplies
Active supply current
IDD
No load, V
IH
=DVDD, V
IL
=0V
AVDD = DVDD = 5V,
V
REF
= 2.048V
Slow
Fast
See Note 8
6
16
8
21
mA
mA
Power down supply current
No load, all inputs 0V
or DVDD
0.1
A
Dynamic DAC Specifications
Slew rate
DAC code 10%-90%
Load = 10k
, 100pF
Fast
Slow
See Note 9
4
1
10
3
V/
s
V/
s
Settling time
DAC code 10%-90%
Load = 10k
, 100pF
Fast
Slow
See Note 10
1
3
3
7
s
s
Glitch energy
Code 127 to code 128
4
nV-s
Channel Crosstalk
10kHz sine wave, 4V pk-pk
-90
dB
Reference Input
Reference input resistance
R
REF
100
k
Reference input capacitance
C
REF
5
pF
Reference feedthrough
V
REF
=2V
PP
at 1kHz
+ 2.048V DC, DAC code 0
-84
dB
Reference input bandwidth
V
REF
= 0.4V
PP
+ 2.048V DC,
DAC code 128
Slow
Fast
1.9
2.2
MHz
MHz
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
5
Test Characteristics:
Over recommended operating conditions (unless noted otherwise).
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High level input current
I
IH
Input voltage = DVDD
1
A
Low level input current
I
IL
Input voltage = 0V
-1
A
Input capacitance
C
I
8
pF
Digital Output
High level digital output voltage
V
OH
Load = 10k
2.6
V
Low level digital output voltage
V
OL
Load = 10k
0.4
V
Output voltage rise time
Load = 10k
, 20pF, includes
propagation delay
7
20
ns
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding
the effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is expressed as a percentage of the full scale output voltage with a 10k
load.
8. I
DD
is measured while continuously writing code 128 to the DAC. For V
IH
< DVDD - 0.7V and V
IL
> 0.7V
supply current will increase.
9. Slew rate results are for the lower value of the rising and falling edge slew rates.
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
WM2629
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
6
SERIAL INTERFACE
X
1
2
3
4
16
X
X
D15
D14
D13
t
WL
D1
D0
X
SCLK
DIN
X
D15 *
D14 *
D13 *
D12 *
D1 *
D0 *
X
DOUT
2
t
WH
t
SUD
t
HD
No high to low transitions
t
SUC16-FS
t
WHFS
t
SUFSCLK
FS
(
C MODE)
FS
(DSP MODE)
t
WLFS
* DIN data from previous word
(delayed by 16 clock cycles)
Figure 1 Timing Diagram
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
t
SUFSCLK
Setup time, FS pin low before first falling edge of SCLK
8
ns
t
C16-FS
Setup time, 16
th
falling clock edge after FS low to rising edge of FS
(only used in microcontroller mode)
10
ns
t
WLOADB
Pulse duration, LOADB low
10
ns
t
WH
Pulse duration, SCLK high
16
ns
t
WL
Pulse duration, SCLK low
16
ns
t
SUD
Setup time, data ready before SCLK falling edge
8
ns
t
HD
Hold time, data held valid after SCLK falling edge
5
ns
t
WHFS
Pulse duration, FS high
10
ns
t
WLFS
Pulse duration, FS low
10
ns
t
s
DAC Output settling time
see Dynamic DAC Specifications
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
7
TYPICAL PERFORMANCE GRAPHS
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0
32
64
96
128
160
192
224
256
DIGITAL CODE
I
n
tegral
Non-Li
neari
t
y (LS
B
s)
Figure 2 Integral Non-Linearity
VDD = 3V
V
REF
= 1.024V
Input Code = 0
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
Sink Current (mA)
O
u
tp
u
t
V
o
l
t
ag
e (V
)
Slow
Fast
VDD = 5V
V
REF
= 2.048V
Input Code = 0
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Sink Current (mA)
O
u
tput Vol
t
age (V)
Slow
Fast
Figure 3 Output Load Regulation (Sink) AVDD = 3V
Figure 4 Output Load Regulation (Sink) AVDD = 5V
VDD=3V
V
REF
=1.024V
Input Code = 4095
2
2.02
2.04
2.06
2.08
2.1
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
Sourcing Current (mA)
DACA (
V
ol
t
s
)
Slow
Fast
VDD=5V
V
REF
=2.048V
Input Code = 4095
4.05
4.07
4.09
4.11
4.13
4.15
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
Sourcing Current (mA)
DACA (
V
ol
t
s
)
Slow
Fast
Figure 5 Output Load Regulation (Source) AVDD = 3V
Figure 6 Output Load Regulation (Source) AVDD = 5V
WM2629
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
8
DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2629 is an octal 8-bit, voltage output DAC. It contains a serial interface, control logic for
speed and power down, a programmable voltage reference, and eight digital to analogue converters.
Each converter uses a resistor string network buffered with an op amp to convert 8-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
Output voltage =
( )
256
2
CODE
V
REF
INPUT
OUTPUT
1111
1111
( )
256
255
2
REF
V
:
:
1000
0001
( )
256
129
2
REF
V
1000
0000
( )
REF
REF
V
V
=
256
128
2
0111
1111
( )
256
127
2
REF
V
:
:
0000
0001
( )
256
1
2
REF
V
0000
0000
0V
Table 1 Binary Code Table
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2k
load with a 100pF load capacitance.
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
9
SERIAL INTERFACE
INTERFACE MODES
The control interface can operate in two different modes:
In the microcontroller mode, FS needs to be held low until all 16 data bits have been
transferred. If FS is driven high before the 16
th
falling clock edge, the data transfer is cancelled.
The DAC is updated after a rising edge on FS.
In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16
th
falling clock
edge.
SCLK
FS
X
DIN
D15
D14
D1
D0
X
E15
E14
E1
E0
X
F15
F14
X
Figure 7 Interface Timing in Microcontroller Mode
E1
SCLK
FS
X
DIN
D15
D14
D1
D0
E15
E14
E0
X
X
F15
F14
X
Figure 8 Interface Timing in DSP Mode
The operating mode is selected using pin 17 (MODE).
MODE PIN (17)
INTERFACE MODE
HIGH
Microcontroller
LOW or unconnected
DSP mode
Table 2 Interface Mode Selection
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the interface timing. The maximum serial clock rate is:
MHz
t
t
f
WL
WH
SCLK
31
1
min
min
max
=
+
=
Since a data word contains 16 bits, the sample rate is limited to
(
)
MHz
t
t
f
WL
WH
s
95
.
1
16
1
min
min
max
=
+
=
However, the DAC settling time to 8 bits accuracy limits the response time of the analogue output for
large input step transitions.
WM2629
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
10
DAISY CHAINING MULTIPLE DEVICES
The DOUT output (pin 19) provides the data sampled on DIN with a delay of 16 clock cycles. This
signal can be used to control another WM2629 or similar device in a daisy-chain type circuit.
DI
N
SC
LK
LO
ADB
FS
DI
N
SC
L
K
LOA
D
B
FS
DO
U
T
OCTAL DAC #1
DI
N
SC
L
K
LOA
D
B
FS
DO
U
T
OCTAL DAC #2
DI
N
SC
L
K
LOA
D
B
FS
DO
U
T
OCTAL DAC #3
Figure 9 Daisy Chaining
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
The WM2629 is controlled with a 16-bit code consisting of four address bits, A0-A3, and up to 12
data bits.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
Data
Table 3 Input Data Format
Using the four address bits, 16 different registers can be addressed.
A3
A2
A1
A0
REGISTER
0
0
0
0
DAC A Code
0
0
0
1
DAC B Code
0
0
1
0
DAC C Code
0
0
1
1
DAC D Code
0
1
0
0
DAC E Code
0
1
0
1
DAC F Code
0
1
1
0
DAC G Code
0
1
1
1
DAC H Code
1
0
0
0
Control Register 0
1
0
0
1
Control Register 1
1
0
1
0
Preset all DACs
1
0
1
1
RESERVED
1
1
0
0
DAC A and complement B
1
1
0
1
DAC C and complement D
1
1
1
0
DAC E and complement F
1
1
1
1
DAC G and complement H
Table 4 Register Map
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
11
DAC A TO H CODE REGISTERS
Addresses 0 to 7 are the DAC registers. Bits D11 (MSB) to D4 (LSB) from these registers are
transferred to the respective DAC when the LOADB input (pin 18) is low. Bits D3 to D1 are unused
and must be set to 0. For instantaneous updating, LOADB can be held low permanently.
CONTROL REGISTER 0
Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power
Down and Data Input Format.
BIT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
X
X
X
X
X
X
PD
DO
X
X
IM
Default
X
X
X
X
X
X
X
0
0
0
0
0
Table 5 Control Register 0 Map
BIT
DESCRIPTION
0
1
PD
Full device Power Down
Normal
Power Down
DO
DOUT Enable
Disabled
Enabled
IM
Input Mode
Straight Binary
Two's Complement
X
Reserved
Table 6 Control Register 0 Functionality
CONTROL REGISTER 1
Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling
time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of
the device. The settling time in fast mode is typically 1
s. In slow mode, the settling time is typically
3
s and power consumption is reduced.
BIT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
X
X
X
P
GH
P
EF
P
CD
P
AB
S
GH
S
EF
S
CD
S
AB
Default
X
X
X
X
0
0
0
0
0
0
0
0
Table 7 Control Register 1 Map
BIT
DESCRIPTION
0
1
P
XY
Power Down DACs X and Y
Normal
Power Down
S
XY
Speed Setting for DACs X and Y
Slow
Fast
Table 8 Control Register 1 Functionality
DAC PRESET REGISTER
The Preset register (address 10) makes it possible to update all eight DACs at the same time. The
value stored in this register becomes the digital input to all the DACs when the asynchronous PREB
input (pin 5) is driven low. If no data has previously been written to the preset register, all DACs are
set to zero scale.
TWO-CHANNEL REGISTERS
The two-channel registers (addresses 12 to 15) provide a `differential output' function where writing
data to one DAC will automatically write the complement to the other DAC in the pair. For example,
writing a value of 255 to address 12 will set DAC A to full scale and DAC B to zero scale.
WM2629
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
12
APPLICATIONS INFORMATION
LINEARITY, OFFSET, AND GAIN ERROR
Amplifiers operating from a single supply can have positive or negative voltage offsets. With a
positive offset, the output voltage changes on the first code transition. However, if the offset is
negative, the output voltage may not change with the first code, depending on the magnitude of the
offset voltage. This is because with the most negative supply rail being ground, any attempt to drive
the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at
zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the
transfer function shown in Figure 10.
DAC code
Negative
Offset
Output
Voltage
0 V
Figure 10 Effect of Negative Offset
This offset error, not the linearity error, produces the breakpoint. The transfer function would follow
the dotted line if the output buffer could drive below the ground rail.
DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs
at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer function,
single supply operation does not allow for adjustment when the offset is negative. In such cases, the
linearity is therefore measured between full-scale and the lowest code that produces a positive (non-
zero) output voltage.
POWER SUPPLY DECOUPLING AND GROUNDING
Printed circuit boards with separate analogue and digital ground planes deliver the best system
performance. The two ground planes should be connected together at the low impedance power
supply source. Ground currents should be managed so as to minimise voltage drops across the
ground planes.
A 0.1
F decoupling capacitor should be connected between the positive supply and ground pins of
the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate
the system analogue supply from the digital supply.
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
13
PACKAGE DIMENSIONS
c
L
GAUGE
PLANE
0.25
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM008.D
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
1.20
A
1
0.05
-----
0.15
A
2
0.80
1.00
1.05
b
0.19
-----
0.30
c
0.09
-----
0.20
D
6.40
6.50
6.60
e
0.65 BSC
E
6.4 BSC
E
1
4.30
4.40
4.50
L
0.45
0.60
0.75
0
o
-----
8
o
REF:
JEDEC.95, MO-153
A
A2
A1
SEATING PLANE
11
20
E1
E
e
b
10
1
D
-C-
0.1 C
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