WM2637
Dual 10-Bit Serial Input Voltage Output DAC
with Internal Reference
Production Data, Rev 1.0, July 1999
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data contains final specifications
current on publication date. Supply of products
conforms to Wolfson Microelectronics' Terms
and Conditions.
Last printed 15/07/99 15:56
1999 Wolfson Microelectronics Ltd
.
FEATURES
Dual 10-bit voltage output DAC
Single 2.7V to 5.5V supply
DNL
0.1 LSBs, INL
0.4 LSBs
Internal programmable voltage reference
Low power consumption:
5.5 mW, slow mode - 5V supply
3.3 mW, slow mode - 3V supply
TMS320, (Q) SPI
TM
, and Microwire
TM
compatible serial
interface
Programmable settling time of 1
s or 3.5
s typical
Power down mode 10nA
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2637CD
0 to 70C
8-pin SOIC
WM2637ID
-40 to 85C
8-pin SOIC
DESCRIPTION
The WM2637 is a dual 10-bit voltage output, resistor string, digital-
to-analogue converter. A software controlled power down mode is
provided that reduces current consumption to 10nA.
The WM2637 features an internal programmable voltage reference
simplifying overall system design. A reference voltage may also be
supplied externally.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2637 is programmed with a 16-bit serial word
comprising of a latch address, mode DAC control bits and DAC or
control data.
Excellent performance is delivered with a typical DNL of 0.1 LSBs.
The programmable settling time allows the designer to optimize
speed versus power consumption. The output stage is buffered by
a x2 gain near rail-to-rail amplifier.
The device is available in an 8-pin SOIC package ideal for space-
critical applications. Commercial temperature (0
to 70
C) and
industrial temperature (-40
to 85
C) variants are supported.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
(7) OUTB
(4) OUTA
10-BIT
DAC B
HOLDING
LATCH
10-BIT
DAC A
LATCH
REF(6)
POWER-ON
RESET
DIN (1)
SCLK (2)
NCS (3)
(5)
AGND
POWERDOWN/
SPEED
CONTROL
10-BIT
DAC B
LATCH
DAC
OUTPUT
BUFFER
2-BIT
CONTROL
LATCH
X1
X2
X2
DAC
OUTPUT
BUFFER
REFERENCE
INPUT
BUFFER
REFERENCE
INPUT BUFFER
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
2-BIT
REFERENCE
SELECT
LATCH
1.024V/2.048V
SELECTABLE
REFERENCE
X1
VDD
(8)
c
X1
REFERENCE
OUTPUT BUFFER
WITH OUPUT
ENABLE
WM2637
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0
256
512
767
1023
DIGITAL CODE
DNL - LSB
5V = VDD, V
REF
= External, Speed = Slow mode, Load = 10k/100pF
WM2637
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
2
PIN CONFIGURATION
1
2
3
4
NCS
DIN
SCLK
AGND
REF
OUT A
VDD
OUT B
5
6
7
8
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
DIN
Digital input
Serial data input.
2
SCLK
Digital input
Serial clock input.
3
NCS
Digital input
Chip select. This pin is active low.
4
OUTA
Analogue output
DAC A analogue output.
5
AGND
Supply
Analogue ground.
6
REF
Analogue I/O
Reference voltage input/output.
7
OUTB
Analogue output
DAC B analogue output
8
VDD
Supply
Positive power supply.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
Supply voltage, VDD to AGND
7V
Digital input voltage
-0.3V
VDD + 0.3V
Reference input voltage
-0.3V
VDD + 0.3V
Operating temperature range, T
A
WM2637CD
WM2637ID
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
V
IH
VDD = 5V
2
V
Low-level digital input voltage
V
IL
VDD = 5V
0.8
V
Reference voltage to REF
V
REF
VDD - 1.5
V
Load resistance
R
L
2
k
Load capacitance
C
L
100
Serial Clock Rate
F
SCLK
20
WM2637CD
0
70
C
Operating free-air temperature
T
A
WM2637ID
-40
85
C
WM2637
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
3
Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
10
bits
Integral non-linearity
INL
See Note 1
0.4
1.0
LSB
Differential non-linearity
DNL
See Note 2
0.1
0.5
LSB
Zero code error
ZCE
See Note 3
24
mV
Gain error
GE
See Note 4
0.6
% FSR
D.c. power supply rejection ratio
DC PSRR
See Note 5
0.5
mV/V
Zero code error temperature coefficient
See Note 6
10
ppm/
C
Gain error temperature coefficient
See Note 6
10
ppm/
C
DAC Output Specifications
Output voltage range
0
VDD - 0.1
V
Output load regulation
2k
to 10k
load
See Note 7
0.1
0.25
%
Power Supplies
Active supply current
I
DD
No load, V
IH
= VDD, V
IL
= 0V
VDD = 5V, V
REF
= 2.048V, Internal
Slow
Fast
VDD = 5V, V
REF
= 2.048V, External
Slow
Fast
VDD = 3V, V
REF
= 1.024V, Internal
Slow
Fast
VDD = 3V, V
REF
= 1.024V, External
Slow
Fast
See Note 8
2.0
4.2
1.7
3.8
1.7
3.7
1.4
3.4
2.5
5.0
2.1
4.6
2.2
4.6
1.8
4.2
mA
mA
mA
mA
mA
mA
mA
mA
Power down supply current
No load,
all digital inputs 0V or VDD
See Note 9
0.01
10
A
Dynamic DAC Specifications
Slew rate
DAC code 32 to 1023, 10%-90%
Slow
Fast
See Note 10
1.5
8.0
V/
s
V/
s
Settling time
DAC code 32 to 1023
Slow
Fast
See Note 11
3.5
1.0
s
s
Glitch energy
Code 511 to 512
10
nV-s
Signal to noise ratio
SNR
fs = 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
53
56
dB
Signal to noise and distortion ratio
SNRD
fs = 400ksps, f
OUT
= 1kHz,
BW = 20kHz
50
54
dB
WM2637
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
4
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Note 12
Total harmonic distortion
THD
fs
= 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
-61
-50
dB
Spurious free dynamic range
SPFDR
fs
= 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
51
62
dB
Reference Configured As Input
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
55
pF
Reference feedthrough
V
REF
= 1VPP at 1kHz
+ 1.024V dc, DAC code 0
-60
dB
Reference input bandwidth
V
REF
= 0.2VPP + 1.024V dc
DAC code 1024
Slow
Fast
1.0
1.0
MHz
MHz
Reference Configured As Output
Low reference voltage
V
REFOUTL
1.003
1.024
1.045
V
High reference voltage
V
REFOUTH
VDD > 4.75V
2.027
2.048
2.069
V
Output source current
I
REFSRC
1
mA
Output sink current
I
REFSNK
-1
mA
Load Capacitance
100
pF
PSRR
-48
dB
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
A
Low level input current
I
IL
Input voltage = 0V
-1
A
Input capacitance
C
I
8
pF
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change
in digital input code.
3.
Zero code error is the voltage output when the DAC input code is zero.
4.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7.
Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is
expressed as a percentage of the full scale output voltage with a 10k
load.
8. I
DD
is measured while continuously writing code 1512 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply current will
increase.
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10.
Slew rate results are for the lower value of the rising and falling edge slew rates
11.
Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
OUT
generated with a sampling
frequency fs
.
WM2637
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
5
SERIAL INTERFACE
NCS
SCLK
DIN
D15
D14
D13
D12
D11
D0
t
SUCSS
t
WCL
t
WCH
t
SUCS1
t
SUCS2
t
DCS1
t
HDCLK
t
SUDCLK
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-
air temperature range (unless noted otherwise)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSS
Setup time NCS low before SCLK low
10
ns
t
SUCS1
Setup time, rising edge of SCLK to rising edge of NCS,
external end of write
10
ns
t
SUCS2
Setup time, rising edge of SCLK to falling edge of NCS,
start of next write cycle
5
ns
t
WCL
Pulse duration, SCLK high
25
ns
t
WCH
Pulse duration, SCLK low
25
ns
t
SUDCLK
Setup time, data ready before SCLK falling edge
10
ns
t
HDCLK
Hold time, data held valid after SCLK falling edge
5
ns
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