WM8195
14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
WOLFSON MICROELECTRONICS LTD
w :: www.wolfsonmicro.com
Advanced Information September 2002, Rev 2.0
Copyright
2002 Wolfson Microelectronics Ltd.
DESCRIPTION
The WM8195 is a 14-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12M SPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset Adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 14-bit
analogue-to-digital converter. The digital output data is
available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed
format, with no missing codes.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. Alternatively an external reference level may be
applied. ADC references are generated internally, ensuring
optimum performance from the device.
Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the WM8195 typically
only consumes 210mW when operating from a single 5V
supply and less than 20
A when in power down mode.
FEATURES
14-bit ADC
No missing codes guaranteed
12MSPS conversion rate
Low power 210mW typical
5V single supply or 5V/3.3V dual supply operation
Single or 3 channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
14-bit parallel or 8, 7 or 4-bit wide multiplexed data output
formats
Internally generated voltage references
48-pin TQFP package
Serial or parallel control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
BLOCK DIAGRAM
M
U
X
RINP
DATA
I/O
PORT
SEN/STB
VSMP
MCLK
VRLC/VBIAS
SDI/DNA
SCK/RNW
TIMING CONTROL
CL
RLC/ACYC
RLC
V
S
R
S
BINP
GINP
VRX
VREF/BIAS
OEB
M
U
X
VRB
RLC
RLC
CDS
CDS
CDS
R
G
B
M
U
X
R
G
B
+
PGA
I/P SIGNAL
POLARITY
ADJUST
8
8
PGA
8
8
PGA
8
8
4
+
+
+
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
14-
BIT
ADC
AVDD1-2
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
+
+
I/P SIGNAL
POLARITY
ADJUST
I/P SIGNAL
POLARITY
ADJUST
DVDD1-3
OP[8]
OP[9]
OP[10]
OP[11]
OP[12]
OP[13]/SDO
NRESET
DGND1-5
AGND1-6
VRT
w
WM8195
OFFSET
DAC
OFFSET
DAC
OFFSET
DAC
M
U
X
RLC
DAC
WM8195
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AI Rev 2.0 September 2002
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PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8195CFT
0 to 70
C
48-pin TQFP
1mm thick body
VR
T
A
V
DD1
A
V
DD2
A
G
ND5
A
G
ND6
VR
B
O
P
[11]
O
P
[12]
O
P
[13]/SDO
DG
ND5
NC
N
R
ESET
37
47 46 45 44 43 42 41 40 39 38
48
DV
DD2
DG
ND1
OP[
1
]
NC
NC
OP[
0
]
OP[
2
]
VSMP
S
D
I/DNA
SC
K/R
N
W
R
L
C
/
AC
YC
MCLK
VRX
AGND3
GINP
AGND2
BINP
AGND1
VRLC/VBIAS
RINP
AGND4
DVDD1
OEB
SEN/STB
DGND4
DGND3
OP[7]
OP[8]
OP[9]
OP[10]
DVDD3
DGND2
OP[3]
OP[4]
OP[5]
OP[6]
25
31
30
29
28
27
26
36
35
34
33
32
1
9
8
7
6
5
4
3
2
12
11
10
24
23
16 17 18 19 20 21 22
13 14 15
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
VRX
Analogue output
Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
2
VRLC/VBIAS
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
3
AGND1
Supply
Analogue ground (0V).
4
BINP
Analogue input
Blue channel input video.
5
AGND2
Supply
Analogue ground (0V).
6
GINP
Analogue input
Green channel input video.
7
AGND3
Supply
Analogue ground (0V).
8
RINP
Analogue input
Red channel input video.
9
AGND4
Supply
Analogue ground (0V).
10
DVDD1
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
11
OEB
Digital input
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Serial interface: enable pulse, active high
Parallel interface: strobe, active low
12
SEN/STB
Digital input
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
13
SDI/DNA
Digital input
Serial interface: serial input data signal
Parallel interface:
High = data, Low = address
14
SCK/RNW
Digital input
Serial interface: serial clock signal
Parallel interface:
High: OP[13:6] is output bus.
Low: OP[13:6] is input bus (Hi-Z).
15
VSMP
Digital input
Video sample synchronisation pulse.
16
RLC/ACYC
Digital input
RLC (active high) selects reset level
clamp on a pixel-by-pixel basis tie high
if used on every pixel.
ACYC autocycles between R, G, B
inputs when in Line-by-Line mode.
17
MCLK
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
18
DGND1
Supply
Digital ground (0V).
19
NC
No connection.
20
NC
No connection.
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PIN
NAME
TYPE
DESCRIPTION
21
OP[0]
Digital output
22
OP[1]
Digital output
23
OP[2]
Digital output
Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes:
Hi-Z: when OEB = 1.
14-bit output: 14-bit data is output on OP[13:0].
8-bit multiplexed output: data is output on OP[13:6] at 2
ADC conversion rate.
7-bit multiplexed output: data is output on OP[13:6] at 2
ADC conversion rate.
4-bit multiplexed output: data is output on OP[13:10] at 4
ADC conversion rate.
See Output Formats section in Device Description for further details.
Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0,
and SEN/STB = 0.
Output 8-bit: register read back data is output in parallel on OP[13:6] when
SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.
24
DVDD2
Supply
Digital I/O supply (3.3V/5V).
25
DGND2
Supply
Digital ground (0V).
26
OP[3]
Digital output
27
OP[4]
Digital output
28
OP[5]
Digital output
29
OP[6]
Digital I/O
See pins 21 to 23 for details.
30
DGND3
Supply
Digital ground (0V).
31
OP[7]
Digital I/O
32
OP[8]
Digital I/O
33
OP[9]
Digital I/O
34
OP[10]
Digital I/O
See pins 21 to 23 for details.
35
DVDD3
Supply
Digital I/O supply (3.3V/5V).
36
DGND4
Supply
Digital ground (0V).
37
OP[11]
Digital I/O
38
OP[12]
Digital I/O
39
OP[13]/SDO
Digital I/O
See pins 21 to 23 for details.
If the device has been configured to use the serial interface, pin OP[13]/SDO may
be used to output register read-back data when OEB = 0 and SEN has been
pulsed high.
See Serial Interface sections in Device Description for further details.
40
DGND5
Supply
Digital ground (0V).
41
NC
No connection.
42
NRESET
Digital input
Reset input, active low. This signal forces a reset of all internal registers and selects
whether the serial or parallel control interface is used. See pin SEN/STB.
43
AVDD1
Supply
Analogue supply (5V).
44
AVDD2
Supply
Analogue supply (5V).
45
AGND5
Supply
Analogue ground (0V).
46
AGND6
Supply
Analogue ground (0V).
47
VRB
Analogue output
Lower reference voltage. This pin must be capacitively decoupled to AGND.
48
VRT
Analogue output
Lower reference voltage. This pin must be capacitively decoupled to AGND.
WM8195
Advanced Information
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AI Rev 2.0 September 2002
4
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Analogue supply voltages: AVDD1, 2
GND - 0.3V
GND + 7V
Digital supply voltages: DVDD1
-
3
GND - 0.3V
GND + 7V
Digital grounds: DGND1
-
5
GND - 0.3V
GND + 0.3V
Analogue grounds: AGND1
-
6
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD2 + 0.3V
Analogue inputs (RINP, GINP, BINP)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
Operating temperature range: T
A
0
C
+70
C
Storage temperature
-65
C
+150
C
Package body temperature (soldering, 10 seconds)
+240
C
Package body temperature (soldering, 2 minutes)
+183
C
Notes:
1.
GND denotes the voltage of any ground pin.
2.
AGND1
-
6 and DGND1
-
5 pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
Operating temperature range
T
A
0
70
C
Analogue supply voltage
AVDD1, 2
4.75
5.0
5.25
V
Digital core supply voltage
DVDD1
4.75
5.0
5.25
V
5V I/O
DVDD2, 3
4.75
5.0
5.25
V
Digital I/O supply voltage
3.3V I/O
DVDD2, 3
2.97
3.3
3.63
V
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WM8195
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AI Rev 2.0 September 2002
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions)
NOMISSING CODES GUARANTEED
Conversion rate
12
MSPS
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.4
4.08
Vp-p
Vp-p
Input signal limits (see Note 2)
V
IN
0
AVDD
V
Full-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
mV
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
mV
Differential non-linearity
DNL
1.25
LSB
Integral non-linearity
INL
8
LSB
Channel to channel gain matching
1
%
Total output noise
Min Gain
Max Gain
1
3
LSB rms
LSB rms
References
Upper reference voltage
VRT
2.85
V
Lower reference voltage
VRB
1.35
V
Input return bias voltage
VRX
1.65
V
Diff. reference voltage (VRT-VRB)
V
RTB
1.4
1.5
1.6
V
Output resistance VRT, VRB, VRX
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
50
VRLC short-circuit current
5
mA
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
A
RLCDAC resolution
4
bits
RLCDAC step size, RLCDAC = 0
V
RLCSTEP
0.25
V/step
RLCDAC step size, RLCDAC = 1
V
RLCSTEP
0.17
V/step
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
V
RLCBOT
0.39
V
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
V
RLCBOT
0.26
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
V
RLCTOP
4.16
V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
V
RLCTOP
2.81
V
VRLC deviation
-50
+50
mV
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
Differential non-linearity
DNL
0.1
0.5
LSB
Integral non-linearity
INL
0.25
1
LSB
Step size
2.04
mV/step
Output voltage
Code 00(hex)
Code FF(hex)
-260
+260
mV
mV
Notes:
1.
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
WM8195
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AI Rev 2.0 September 2002
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Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Programmable Gain Amplifier
Resolution
8
bits
Gain
]
0
:
7
[
PGA
283
208
-
V/V
Max gain, each channel
G
MAX
7.4
V/V
Min gain, each channel
G
MIN
0.74
V/V
Gain error, each channel
1
%
Analogue to Digital Converter
Resolution
14
bits
Speed
12
MSPS
Full-scale input range
(2*(VRT-VRB))
3
V
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
V
IH
0.8
DVDD2/3
V
Low level input voltage
V
IL
0.2
DVDD2/3
V
High level input current
I
IH
1
A
Low level input current
I
IL
1
A
Input capacitance
C
I
5
pF
Digital Outputs
High level output voltage
V
OH
I
OH
= 1mA
DVDD2/3 - 0.5
V
Low level output voltage
V
OL
I
OL
= 1mA
0.5
V
High impedance output current
I
OZ
1
A
Digital IOPins
Applied high level input voltage
V
IH
0.8
DVDD2/3
V
Applied low level input voltage
V
IL
0.2
DVDD2/3
V
High level output voltage
V
OH
I
OH
= 1mA
DVDD2/3 - 0.5
V
Low level output voltage
V
OL
I
OL
= 1mA
0.5
V
Low level input current
I
IL
1
A
High level input current
I
IH
1
A
Input capacitance
C
I
5
pF
High impedance output current
I
OZ
1
A
Supply Currents
Total supply current
-
active
(Three channel mode)
MCLK = 24MHz
42
60
mA
Total supply current
-
active
(Single channel mode)
LINEBYLINE = 1
MCLK = 24MHz
35
mA
Total analogue supply current
-
active (Three channel mode)
I
AVDD
MCLK = 24MHz
37
mA
Total analogue supply current
-
active (One channel mode)
I
AVDD
LINEBYLINE = 1
MCLK = 24MHz
30
mA
Digital core supply current,
DVDD1
-
active (Note1)
MCLK = 24MHz
3
mA
Digital I/O supply current, DVDD2
-
active (Note1)
MCLK = 24MHz
2
mA
Supply current
-
full power down
mode
20
60
A
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WM8195
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AI Rev 2.0 September 2002
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INPUT VIDEOSAMPLING
MCLK
VSMP
INPUT
VIDEO
t
PER
t
MCLKH
t
MCLKL
t
VSMPSU
t
VSMPH
t
VSU
t
VH
t
RSU
t
RH
Figure 1 Input Video Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
t
PER
41.6
ns
MCLK high period
t
MCLKH
18.8
ns
MCLK low period
t
MCLKL
18.8
ns
VSMP set-up time
t
VSMPSU
6
ns
VSMP hold time
t
VSMPH
3
ns
Video level set-up time
t
VSU
10
ns
Video level hold time
t
VH
3
ns
Reset level set-up time
t
RSU
10
ns
Reset level hold time
t
RH
3
ns
Notes:
1.
t
VSU
and t
RSU
denote the set-up time required after the input video signal has settled.
2.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
OP[13:0]
t
PD
Figure 2 Output Data Timing
WM8195
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AI Rev 2.0 September 2002
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OEB
OP[13:0]
t
PZE
Hi-Z
t
PEZ
Hi-Z
Figure 3 Output Data Enable Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output propagation delay
t
PD
I
OH
= 1mA, I
OL
= 1mA
40
ns
Output enable time
t
PZE
20
ns
Output disable time
t
PEZ
15
ns
MCLK
RLC/ACYC
PGA/OFFSET
MUX OUTPUT
t
ACYCSU
t
ACYCH
t
ACYCSU
t
ACYCH
Figure 4 Auto Cycle Timing
Test Conditions
AVDD = DVDD1 = 4.75 to 5.25V, DVDD2 = 2.97 to 3.63V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 32MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Auto Cycle set-up time
t
ACYCSU
6
ns
Auto Cycle hold time
t
ACYCH
3
ns
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WM8195
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AI Rev 2.0 September 2002
9
SERIAL INTERFACE
Figure 5 Serial Interface Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SCK period
t
SPER
41.6
ns
SCK high
t
SCKH
18.8
ns
SCK low
t
SCKL
18.8
ns
SDI set-up time
t
SSU
6
ns
SDI hold time
t
SH
6
ns
SCK to SEN set-up time
t
SCE
12
ns
SEN to SCK set-up time
t
SEC
12
ns
SEN pulse width
t
SEW
25
ns
SEN low to SDO = Register data
t
SERD
30
ns
SCK low to SDO = Register data
t
SCRD
30
ns
SCK low to SDO = ADC data
t
SCADC
30
ns
Note:
Parameters are measured at 50% of the rising/falling edge.
SCK
SDI
SEN
SDO
t
SPER
t
SCKL
t
SCKH
t
SSU
t
SH
t
SCE
t
SEW
t
SEC
t
SERD
t
SCRD
MSB
LSB
t
SCRDZ
ADC DATA
ADC
DATA
REGISTER DATA
WM8195
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AI Rev 2.0 September 2002
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PARALLEL INTERFACE
STB
OP[13:6]
DNA
RNW
ADC DATA OUT
ADC DATA OUT
REG. DATA OUT
ADC DATA OUT
Hi-Z
Hi-Z
t
ASU
t
STB
t
AH
t
DSU
t
DH
t
STDO
t
STAO
t
ADLS
t
ADLH
t
ADHS
t
ADHH
t
OPD
ADDRESS IN
DATA IN
t
OPZ
Figure 6 Parallel Interface Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RNW low to OP[13:6] Hi-Z
t
OPZ
10
ns
Address set-up time to STB low
t
ASU
0
ns
DNA low set-up time to STB low
t
ADLS
5
ns
Strobe low time
t
STB
30
ns
Address hold time from STB high
t
AH
5
ns
DNA low hold time from STB high
t
ADLH
5
ns
Data set-up time to STB low
t
DSU
0
ns
DNA high set-up time to STB low
t
ADHS
5
ns
Data hold time from STB high
t
DH
5
ns
Data high hold time from STB high
t
ADHH
5
ns
RNW high to OP[13:6] output
t
OPD
30
ns
Data output propogation delay from
STB low
t
STDO
30
ns
ADC data out propogation delay
from STB high
t
STAO
30
ns
Note:
Parameters are measured at 50% of the rising/falling edge.
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DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1.
The WM8195 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then
processes the sampled video signal with respect to the video reset level or an internally/externally
generated reference level using either one or three processing channels.
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), a 8-bit programmable offset DAC and an 8-bit
Programmable Gain Amplifier (PGA).
The ADC then converts each resulting analogue signal to a 14-bit digital word. The digital output from
the ADC is presented on a 14-bit wide bus, with optional 8+6-bit, 7+7-bit or 4+4+4+2-bit multiplexed
formats.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial or parallel interface.
INPUT SAMPLING
The WM8195 can sample and process one to three inputs through one or three processing channels
as follows:
Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for
each pixel and a separate channel processes each input. The signals are then multiplexed into the
ADC, which converts all three inputs within the pixel period.
Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the
corresponding channel, and converted by the ADC. The choice of input and channel can be changed
via the control interface, e.g. on a line-by-line basis if required.
Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into
the red channel for processing before being converted by the ADC. The input selected can be
switched in turn (RINP
GINP
BINP
RINP...) together with the PGA and offset DAC control
registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling
sequences can be generated via the control registers. This mode causes the blue and green
channels to be powered down. Refer to the Line-by-Line Operation section for more details.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8195 lies within its input range (0V to AVDD) the CCD
output signal is usually level shifted by coupling through a capacitor, C
IN.
The RLC circuit clamps the
WM8195 side of this capacitor to a suitable voltage during the CCD reset period.
A typical input configuration is shown in Figure 7 A clamp pulse, CL, is generated from MCLK and
VSMP by the Timing Control Block. When CL is active the voltage on the WM8195 side of C
IN
, at
RINP, is forced to the VRLC/VBIAS voltage (V
VRLC
) by switch 1. When the CL pulse turns off, the
voltage at RINP initially remains at V
VRLC
but any subsequent variation in sensor voltage (from reset
to video level) will couple through C
IN
to RINP.
RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to
the CDS/Non-CDS Processing section.
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TIMING CONTROL
S/H
4-BIT
RLC DAC
CL
+
+
-
TOOFFSET DAC
RLC
CDS
FROM CONTROL
INTERFACE
S/H
V
S
R
S
FROM CONTROL
INTERFACE
MCLK
VSMP
RLC/ACYC
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
CDS
C
IN
RINP
VRLC/
VBIAS
2
1
EXTERNAL VRLC
VRLCEXT
Figure 7 Reset Level Clamping and CDS Circuitry
If auto-cycling is not required, RLC can be selected pixel-by-pixel by pin RLC/ACYC. Figure 8
illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period.
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 9).
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.
Figure 8 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 7) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
s
/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 9.
MCLK
VSMP
ACYC/RLC
or RLCINT
CL
(CDSREF = 01)
INPUT VIDEO
1
X
X
0
X
X
0
RGB
RGB
No RLC on this Pixel
RLC on this Pixel
Programmable Delay
RGB
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13
MCLK
VSMP
VS
R
S
/CL (CDSREF = 00)
R
S
/CL (CDSREF = 01)
R
S
/CL (CDSREF = 10)
R
S
/CL (CDSREF = 11)
Figure 9 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by R
s
at the same time as V
s
samples the video level in
this mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].
The gain characteristic of the WM8195 PGA is shown in Figure 10. Figure 11 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (3V).
0
1
2
3
4
5
6
7
8
0
64
128
192
256
Gain register value (PGA[7:0])
PGA
G
a
i
n
(
V/
V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
64
128
192
256
Gain register value (PGA[7:0])
P
e
a
k
input
v
o
lta
g
e
t
o
m
a
t
c
h
ADC
Full
-
scale
I
nput
Range
Figure 10 PGA Gain Characteristic
Figure 11 Peak Input Voltage to Match ADC Full-scale Range
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order
(Red
Green
Blue
Red...) by pulsing the ACYC/RLC pin, or controlled via the FME,
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
WM8195
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ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (3V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 12 represents the processing of the video signal through the WM8195.
V
RESET
V
VRLC
V
3
CDS = 1
CDS = 0
RLCEXT=1
260mV*(DAC[7:0]-127.5)/127.5
analog
-
X
+
+
V
RLCSTEP
*RLCV[3:0] + V
RLCBOT
OP[13:0]
D
1
digital
ADC BLOCK
PGA
BLOCK
OFFSET DAC
BLOCK
INPUT
SAMPLING
BLOCK
D
2
CDS, RLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS = 1 for CDS, 0 for non-CDS
V
IN
is RINP or GINP or BINP
V
RESET
is V
IN
sampled during reset clamp
V
VRLC
is voltage applied to VRLC pin
V
IN
x (16383/V
FS
)
+0
if PGAFS[1:0]=11
+16383 if PGAFS[1:0]=10
+8191 if PGAFS[1:0]=0x
PGA gain
A = 208/(283-PGA[7:0])
OUTPUT
INVERT
BLOCK
D2 = D1 if INVOP = 0
D2 = 16383-D1 if INVOP = 1
Offset
DAC
RLC
DAC
+
V
2
V
1
RLCEXT=0
Figure 12 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V
1
. For CDS, this is the
difference between the input video level V
IN
and the input reset level V
RESET
. For non-CDS this is the
difference between the input video level V
IN
and the voltage on the VRLC/VBIAS pin, V
VRLC
,
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V
2
.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V
3
.
The ADC BLOCK then converts the analogue signal, V
3
, to a 14-bit unsigned digital output, D
1
.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D
2.
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CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8195.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (CDS operation) the previously sampled reset level, V
RESET
, is subtracted from the input
video.
V
1
=
V
IN
- V
RESET
...................................................................
Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V
1
=
V
IN
- V
VRLC
....................................................................
Eqn. 2
If RLCEXT = 1, V
VRLC
is an externally applied voltage on pin VRLC/VBIAS.
If RLCEXT = 0, V
VRLC
is the output from the internal RLC DAC.
V
VRLC
=
(V
RLCSTEP
RLCV[3:0]) + V
RLCBOT
.................................
Eqn. 3
V
RLCSTEP
is the step size of the RLC DAC and V
RLCBOT
is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V
1
is added to the offset DAC output.
V
2
=
V
1
+ {260mV
(DAC[7:0]-127.5) } / 127.5 .....................
Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
V
3
=
V
2
208/(283- PGA[7:0]) ..............................................
Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 14-bit unsigned number, with input range configured by
PGAFS[1:0].
D
1
[13:0] = INT{ (V
3
/V
FS
)
16383} + 8191
PGAFS[1:0] = 00 or 01 ......
Eqn. 6
D
1
[13:0] = INT{ (V
3
/V
FS
)
16383}
PGAFS[1:0] = 11 ...............
Eqn. 7
D
1
[13:0] = INT{ (V
3
/V
FS
)
16383} + 16383 PGAFS[1:0] = 10 ...............
Eqn. 8
where the ADC full-scale range, V
FS
= 3V.
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D
2
[13:0] = D
1
[13:0]
(INVOP = 0) ......................
Eqn. 9
D
2
[13:0] = 16383 D
1
[13:0]
(INVOP = 1) ......................
Eqn. 10
WM8195
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OUTPUT FORMATS
The digital data output from the ADC is available to the user in either 14-bit parallel or 8/7/4-bit wide
multiplexed formats by setting control bits MUXOP[1:0]. Latency of valid output data with respect to
VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the
Operating Mode Timing Diagrams section.
Figure 13 shows the output data formats for Modes 1 2 and 4 6. Figure 14 shows the output data
formats for Mode 3. Table 1 summarises the output data obtained for each format.
MCLK
4+4+4+2-BIT
OUTPUT
A
A
B
D
A
B
C
14-BIT PARALLEL
OUTPUT
8+6 AND 7+7-BIT
OUTPUT
MCLK
4+4+4+2-BIT
OUTPUT
A
A
B
14-BIT PARALLEL
OUTPUT
8+6 AND 7+7-BIT
OUTPUT
A B
C D
A B
Figure 13 Output Data Formats
(Modes 1
-
-
-
-
2, 4
-
-
-
-
6)
Figure 14 Output Data Formats
(Mode 3)
OUTPUT
FORMAT
MUXOP[1:0]
OUTPUT
PINS
OUTPUT
14-bit parallel
00
OP[13:0]
A = d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3,
d2, d1, d0
8+6-bit
multiplexed
01
OP[13:6]
A = d13, d12, d11, d10, d9, d8, d7, d6
B = d5, d4, d3, d2, d1, d0, CC, OVRNG
7+7-bit
10
OP[13:6]
A = d13, d12, d11, d10, d9, d8, d7, CC
B = d6, d5, d4, d3, d2, d1, d0, OVRNG
4+4+4+2-bit
(nibble)
11
OP[13:10]
A = d13, d12, d11, d10
B = d9, d8, d7, d6
C = d5, d4, d3, d2
D = d1, d0, CC, OVRNG
Table 1 Details of Output Data Shown in Figure 13 and Figure 14.
FLAGS
The following flags are output during multiplexed modes:
CC can be used in colour modes 1 and 5 to identify the green channel output, from which the blue
and red data can be identified.
INPUT
CC
RINP
0
GINP
1
BINP
0
Table 2 Input Sampled Flags CC[1:0]
OVRNG indicates that the current output data was produced by an input signal that exceeded the
input range limit of the device. 1 = out of range, 0 = within range.
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17
CONTROL INTERFACE
The internal control registers are programmable via the serial or parallel digital control interface. The
register contents can be read back via the parallel interface on pins OP[13:6], or via the serial
interface on pin OP[13]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table
6).
SERIAL INTERFACE: REGISTER WRITE
Figure 15 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.
When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SEN
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Address
Data Word
Figure 15 Serial Interface Register Write
Using the serial interface, a software reset is carried out by writing to Address "000100" with any
value of data (i.e. Data Word = XXXXXXXX).
SERIAL INTERFACE: REGISTER READ-BACK
Figure 16 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge
of SCK). Note that pin SDO is shared with an output pin, OP[13], therefore OEB should always be
held low when register read-back data is expected on this pin. The next word may be read in to SDI
while the previous word is still being output on SDO.
SCK
SEN
SDI
a5
1
a3 a2 a1 a0
x
x
x
x
x
x
x
x
Address
Data Word
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
SDO/
OP[13]
OEB
Figure 16 Serial Interface Register Read-back
WM8195
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PARALLEL INTERFACE: REGISTER WRITE
Figure 17 shows register write in parallel mode. The parallel interface uses bits OP[13:6] of the
output bus and the STB, DNA and RNW pins. Pin RNW must be low during a write operation. The
DNA pin defines whether the data byte is address (low) or data (high). The 6-bit address (a5, 0, a3,
a2, a1, a0) is input into OP[11:6], LSB into OP[6], (OP[12] and OP[13] are ignored) when DNA is low,
then the 8-bit data word is input into OP[13:6], LSB into OP[6], when DNA is high. The data bus
OP[13:6] for both address and data is clocked in on the falling edge of STB. Note all valid registers
have address bit a4 equal to 0.
STB
DNA
RNW
OP[13:6]
Address
Data
Hi-Z
Hi-Z
Driven by AFE
Driven Externally
Normal Output Data
Driven by AFE
Normal Output Data
Figure 17 Parallel Interface Register Write
Using the parallel interface, a software reset is carried out by writing "000100" to OP[13:8] when
RNW and DNA are low. Any value of data can be written for this address when DNA changes to high
(i.e. Data = XXXXXXXX on OP[15:8]).
PARALLEL INTERFACE: REGISTER READ-BACK
Figure 18 shows register read-back in parallel mode. Read-back is initiated by writing the 6-bit
address (a5, 1, a3, a2, a1, a0) into OP[11:6] by pulsing the STB pin low. Note that a4 = 1 and pins
RNW and DNA are low. When RNW and DNA are high and STB is strobed again, the contents (d7,
d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on
OP[13:6], LSB on pin OP[6]. Until STB is pulsed low, the current contents of the ADC (shown as
Normal Output Data) will be present on OP[13:6]. Note that the register data becomes available on
the output data pins so OEB should be held low when read-back data is expected.
STB
DNA
RNW
OP[13:6]
Address
Hi-Z
Driven by AFE
Driven Externally
Hi-Z
Normal Output Data
Read Data
Driven by AFE
Normal Output Data
Figure 18 Parallel Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock
(VSMP) of up to 12MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 5.
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AI Rev 2.0 September 2002
19
PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8195. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8195 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.
Figure 19 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the
normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising
MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
MCLK
VSMP
(VDEL = 000) INTVSMP
POSNNEG = 1
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
POSNNEG = 0
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
INPUT
PINS
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
Figure 19 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS.
WM8195
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AI Rev 2.0 September 2002
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POWER SUPPLY
The WM8195 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit and SELPD bit low. Alternatively, when control bit SELPD is
high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the
user to optimise power dissipation in certain modes, or to define an intermediate standby mode to
allow a quicker recovery into a fully active state. In Line-by-Line operation, the green and blue
channel PGAs are automatically powered down.
All the internal registers maintain their previously programmed value in power down modes and the
control interface inputs remain active. Table 3 summarises the power down control bit functions.
EN
SELDPD
0
0
Device completely powers down.
1
0
Device completely powers up.
X
1
Blocks with respective SELDIS[3:0] bit high are disabled.
Table 3 Power Down Control
LINE-BY-LINE OPERATION
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8195 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8195
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 20 shows the signal path when operating in colour line-by-line mode.
RINP
SEN/STB
VSMP
MCLK
VRLC/VBIAS
SDI/DNA
SCK/RNW
RLC/ACYC
RLC
BINP
GINP
INPUT
MUX
OFFSET
MUX
RLC
R
G
B
R
G
B
PGA
I/P SIGNAL
POLARITY
ADJUST
8
RLC
DAC
+
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
OP[13:0]
+
14-
BIT
ADC
DATA
I/O
PORT
8
OFFSET
DAC
PGA
MUX
TIMING CONTROL
CL
V
S
R
S
4
CDS
RLC
NRESET
Figure 20 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
See Figure 4 for detailed timing information. The multiplexers change on the first MCLK rising edge
after RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to
be reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three
multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the
desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA
and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible.
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21
FME
ACYCNRLC
NAME
DESCRIPTION
0
0
Internal,
no force mux
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
0
1
Auto-cycling,
no force mux
Input mux, offset and gain registers auto-cycled, RINP
GINP
BINP
RINP... on RLC/ACYC pulse.
1
0
Internal,
force mux
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers selected from internal register
bits INTM1, INTM0.
1
1
Auto-cycling,
force mux
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RED
GREEN
BLUE
RED... on RLC/ACYC pulse.
Table 4 Colour Selection Description in Line-by-Line Mode
WM8195
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22
OPERATING MODES
Table 5 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
SENSOR
INTERFACE
DESCRIPTION
TIMING
REQUIRE-
MENTS
REGISTER
CONTENTS
WITH CDS
REGISTER
CONTENTS
WITHOUT
CDS
1
Colour
Pixel-by-Pixel
Yes
4MSPS
x 3 chans
The 3 input channels
are sampled in
parallel. The signal is
then gain and offset
adjusted before being
multiplexed into a
single data stream
and converted by the
ADC, giving an output
data rate of 12MSPS
max.
MCLK max
= 24MHz
MCLK:
VSMP
ratio is 6:1
SetReg1:
03(hex)
SetReg1:
01(hex)
2
Monochrome/
Colour
Line-by-Line
Yes
4MSPS
x 1 chan
As mode 1 except:
Only one input
channel at a time
is continuously
sampled.
MCLK max
= 24MHz
MCLK:
VSMP
ratio is 6:1
SetReg1:
07(hex)
SetReg1:
05(hex)
3
Fast
Monochrome/
Colour
Line-by-Line
Yes
8MSPS
x 1 chan
Identical to mode 2
MCLK max
= 24MHz
MCLK:
VSMP
ratio is 3:1
Identical to
mode 2 plus
SetReg3:
bits 5:4 must
be set to
0(hex)
Identical to
mode 2
4
Maximum
speed
Monochrome/
Colour
Line-by-Line
No
12MSPS
x 1 chan
Identical to mode 2
MCLK max
= 24MHz
MCLK:
VSMP
ratio is 2:1
CDS not
possible
SetReg1:
45(hex)
5
Slow Colour
Pixel-by-Pixel
Yes
3MSPS
x 3 chans
Identical to mode 1
MCLK max
= 24MHz
MCLK:
VSMP
ratio is
2n:1, n
4
Identical to
mode 1
Identical to
mode 1
6
Slow
Monochrome/
Colour
Line-by-Line
Yes
3MSPS
x 1 chan
Identical to mode 2
MCLK max
= 24MHz
MCLK:
VSMP
ratio is
2n:1, n
4
Identical to
mode 2
Identical to
mode 2
Table 5 WM8195 Operating Modes
Notes:
1.
In Monochrome mode, Setup Register 3 bits 7:6 determine which input is to be sampled.
2.
For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection
Description in Line-by-Line Mode.
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WM8195
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AI Rev 2.0 September 2002
23
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 14-bit parallel format output and MCLK, VSMP and input video
requirements for operation of the most commonly used modes as shown in Table 5. The diagrams
are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown
as R, G and B respectively. X denotes invalid data.
MCLK
VSMP
INPUT VIDEO
OP[13:0] (DEL = 00)
OP[13:0] (DEL = 01)
OP[13:0] (DEL = 10)
OP[13:0] (DEL = 11)
16.5 MCLK PERIODS
G
B
R
G
B
R
G
R
B
R
B
G
R
R
G
B
R
G
B
R
B
G
B
G
R
B
R
B
R
G
B
R
G
B
G
R
G
R
B
G
B
R
G
B
R
G
B
R
G
R
B
R
B
G
R
G
B
G
G
B
Figure 21 Mode 1 Operation
16.5 MCLK PERIODS
MCLK
VSMP
INPUT VIDEO
OP[13:0] (DEL = 00)
OP[13:0] (DEL = 01)
OP[13:0] (DEL = 10)
OP[13:0] (DEL = 11)
X
X
R
X
X
R
X
R
X
R
X
X
R
R
X
X
R
X
X
R
X
X
X
X
R
X
X
R
X
X
R
X
X
X
R
X
R
X
X
X
X
R
X
X
R
X
R
X
R
X
X
R
Figure 22 Mode 2 Operation
MCLK
VSMP
OP[13:0] (DEL = 00)
INPUT VIDEO
OP[13:0] (DEL = 01)
OP[13:0] (DEL = 10)
OP[13:0] (DEL = 11)
23.5 MCLK PERIODS
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Figure 23 Mode 3 Operation
WM8195
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AI Rev 2.0 September 2002
24
MCLK
VSMP
INPUT VIDEO
OP[13:0] (DEL = 00)
OP[13:0] (DEL = 01)
OP[13:0] (DEL = 10)
OP[13:0] (DEL = 11)
16.5 MCLK PERIODS
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Figure 24 Mode 4 Operation
MCLK
VSMP
INPUT VIDEO
OP[13:0] (DEL = 00)
OP[13:0] (DEL = 01)
OP[13:0] (DEL = 10)
OP[13:0] (DEL = 11)
16.5 MCLK PERIODS
G
B
R
B
G
R
G
B
R
X
X
X
R
G
X
G
R
X
R
G
X
B
B
B
X
R
B
R
X
B
X
R
B
G
G
G
B
X
G
X
B
G
B
X
G
R
R
R
B
X
G
B
R
X
R
G
B
X
R
G
Figure 25 Mode 5 Operation (MCLK:VSMP Ratio = 8:1)
MCLK
VSMP
INPUT VIDEO
OP[13:0] (DEL = 00)
OP[13:0] (DEL = 01)
OP[13:0] (DEL = 10)
OP[13:0] (DEL = 11)
16.5 MCLK PERIODS
R
R
R
X
X
X
X
X
X
X
X
X
X
X
X
X
R
X
X
R
X
X
R
X
X
X
X
X
X
R
X
X
R
X
X
R
X
X
X
R
X
X
R
X
X
R
X
X
R
X
X
X
Figure 26 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)
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WM8195
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AI Rev 2.0 September 2002
25
DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the
WM8195. The register map is programmed by writing the required codes to the appropriate
addresses via the serial or parallel interface.
BIT
ADDRESS
<a5:a0>
DESCRIPTION
DEF
(hex)
RW
b7
b6
b5
b4
b3
b2
b1
b0
000001
Setup Reg 1
03
RW
MODE4
PGAFS[1]
PGAFS[0]
SELPD
MONO
CDS
EN
000010
Setup Reg 2
20
RW
DEL[1]
DEL[0]
RLCDACRNG
0
VRLCEXT
INVOP
MUXOP[1]
MUXOP[0]
000011
Setup Reg 3
1F
RW
CHAN[1]
CHAN[0]
CDSREF [1]
CDSREF [0]
RLCV[3]
RLCV[2]
RLCV[1]
RLCV[0]
000100
Software Reset
00
W
000101
Auto-cycle Reset
00
W
000110
Setup Reg 4
00
RW
FM[1]
FM[0]
INTM[1]
INTM[0]
RLCINT
FME
ACYCNRLC
LINEBYLINE
000111
Revision Number
41
R
001000
Setup Reg 5
00
RW
0
0
0
POSNNEG
VDEL[2]
VDEL[1]
VDEL[0]
VSMPDET
001001
Setup Reg 6
00
RW
0
0
0
0
SELDIS[3]
SELDIS[2]
SELDIS[1]
SELDIS[0]
001010
Reserved
00
RW
0
0
0
0
0
0
0
0
001011
Reserved
00
RW
0
0
0
0
0
0
0
0
001100
Reserved
00
RW
0
0
0
0
0
0
0
0
100000
DAC Value (Red)
80
RW
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
100001
DAC Value
(Green)
80
RW
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
100010
DAC Value (Blue)
80
RW
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
100011
DAC Value (RGB)
80
W
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
101000
PGA Gain (Red)
00
RW
PGA[7]
PGA[6]
PGA[5]
PGA[4]
PGA[3]
PGA[2]
PGA[1]
PGA[0]
101001
PGA Gain
(Green)
00
RW
PGA[7]
PGA[6]
PGA[5]
PGA[4]
PGA[3]
PGA[2]
PGA[1]
PGA[0]
101010
PGA Gain (Blue)
00
RW
PGA[7]
PGA[6]
PGA[5]
PGA[4]
PGA[3]
PGA[2]
PGA[1]
PGA[0]
101011
PGA Gain (RGB)
00
W
PGA[7]
PGA[6]
PGA[5]
PGA[4]
PGA[3]
PGA[2]
PGA[1]
PGA[0]
Table 6 Register Map
WM8195
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AI Rev 2.0 September 2002
26
REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 7.
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
0
EN
1
When SELPD = 1 this bit has no effect.
When SELPD = 0 this bit controls the global power down:
0 = complete power down, 1 = fully active.
1
CDS
1
Select correlated double sampling mode: 0 = single ended mode,
1 = CDS mode.
2
MONO
0
Mono/colour select: 0 = colour, 1 = monochrome operation.
3
SELPD
0
Selective power down: 0 = no individual control,
1 = individual blocks can be disabled (controlled by SELDIS[3:0]).
Offsets PGA output to optimise the ADC range for different polarity sensor
output signals. Zero differential PGA input signal gives:
5:4
PGAFS[1:0]
00
00 = Zero output
(use for bipolar video)
01 = Zero output
10 = Full-scale positive output
(use for negative going video)
11 = Full-scale negative output
(use for positive going video)
Setup
Register 1
6
M
ODE4
0
Required when operating in MODE4: 0 = other modes, 1 = MODE4.
Determines the output data format.
1:0
MUXOP[1:0]
00
00 = 14-bit parallel
01 = 8-bit multiplexed (8+6 bits)
10 = 7-bit multiplexed mode (7+7 bits)
11 = 4-bit multiplexed mode (4+4+4+2 bits)
2
INVOP
0
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative going video gives positive going output data.
3
VRLCEXT
0
When set powers down the RLCDAC, changing its output to Hi-Z, allowing
VRLC/VBIAS to be externally driven.
5
RLCDACRNG
1
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to AVDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
Sets the output latency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC clock
period = 3 MCLK periods.
Setup
Register 2
7:6
DEL[1:0]
00
00 = Minimum latency
01 = Delay by one ADC clock
period
10 = Delay by two ADC clock periods
11 = Delay by three ADC clock periods
3:0
RLCV[3:0]
1111
Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal
reference voltage or Reset Level Clamp voltage. See Electrical Characteristics
section for ranges.
CDS mode reset timing adjust.
5:4
CDSREF[1:0]
01
00 = Advance 1 MCLK period
01 = Normal
10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods
Monochrome mode channel select.
Setup
Register 3
7:6
CHAN[1:0]
00
00 = Red channel select
01 = Green channel select
10 = Blue channel select
11 = Reserved
Software
Reset
Any write to Software Reset causes all cells to be reset. It is recommended
that a software reset be performed after a power-up before any other register
writes.
Auto-cycle
Reset
Any write to Auto-cycle Reset causes the auto-cycle counter to reset
to RINP. This function is only required when LINEBYLINE = 1.
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AI Rev 2.0 September 2002
27
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
0
LINEBYLINE
0
Selects line by line operation 0 = normal operation,
1 = line by line operation.
When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to
00 internally, ensuring that the correct internal timing signals are produced.
Green and Blue PGAs are also disabled to save power.
1
ACYCNRLC
0
When LINEBYLINE = 0 this bit has no effect.
When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input
pin and the input multiplexer and offset/gain register controls.
0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input
and gain/offset multiplexers,
1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin.
See Table 4, Colour Selection Description in Line-by-Line Mode for colour
selection mode details.
When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset
level clamping. The RLCINT bit may be used instead.
2
FM E
0
When LINEBYLINE = 0 this bit has no effect.
When LINEBYLINE = 1 this bit controls the input force mux mode:
0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected
by FM[1:0] separately from gain and offset multiplexers.
See Table 4 for details.
3
RLCINT
0
When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine
whether Reset Level Clamping is used.
0 = RLC disabled, 1 = RLC enabled.
5:4
INTM[1:0]
00
Colour selection bits used in internal modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 4 for details.
Setup
Register 4
7:6
FM[1:0]
00
Colour selection bits used in input force mux modes.
00 = RINP, 01 = GINP, 10 = BINP and 11 = Reserved.
See Table 4 for details.
0
VSMPDET
0
0 = Normal operation, signal on VSMP input pin is applied directly to Timing
Control block.
1 = Programmable VSMP detect circuit is enabled. An internal synchronisation
pulse is generated from signal applied to VSMP input pin and is applied to
Timing Control block.
3:1
VDEL[2:0]
000
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the detected
edge of the signal applied to the VSMP pin. The internally generated pulse is
delayed by VDEL MCLK periods from the detected edge.
See Figure 19, Internal VSMP Pulses Generated for details.
Setup
Register 5
4
POSNNEG
0
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 19 for further details.
Setup
Register 6
3:0
SELDIS[3:0]
0000
Selective power disable register - activated when SELPD = 1.
Each bit disables respective cell when 1, enabled when 0.
SELDIS[0] = Red CDS, PGA
SELDIS[1] = Green CDS, PGA
SELDIS[2] = Blue CDS, PGA
SELDIS[3] = ADC
WM8195
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AI Rev 2.0 September 2002
28
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
Offset DAC
(Red)
7:0
DAC[7:0]
0
Red channel offset DAC value.
Offset DAC
(Green)
7:0
DAC[7:0]
0
Green channel offset DAC value
Offset DAC
(Blue)
7:0
DAC[7:0]
0
Blue channel offset DAC value
Offset DAC
(RGB)
7:0
DAC[7:0]
0
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
PGA gain
(Red)
7:0
PGA[7:0]
0
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = 208/(283-PGA[7:0])
PGA gain
(Green)
7:0
PGA[7:0]
0
Determines the gain of the green channel PGA according to the equation:
Green channel PGA gain = 208/(283-PGA[7:0])
PGA gain
(Blue)
7:0
PGA[7:0]
0
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = 208/(283-PGA[7:0])
PGA gain
(RGB)
7:0
PGA[7:0]
0
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
Table 7 Register Control Bits
Advanced Information
WM8195
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AI Rev 2.0 September 2002
29
RECOMMENDED EXTERNAL COMPONENTS
10
24
8
6
4
17
15
16
12
14
13
DVDD1
DVDD2
AGND1
RINP
GINP
BINP
MCLK
VSMP
RLC/ACYC
SEN/STB
SDI/DNA
SCK/RNW
18
2
48
1
47
31
29
28
27
26
23
22
21
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
VRLC/VBIAS
VRX
VRT
VRB
C
2
C
1
C
7
C
9
C
5
C
6
C
8
C
10
Video
Inputs
Timing
Signals
Interface
Controls
Output
Data
Bus
AGND
AGND
AGND
3
DGND1
AGND2
5
WM8195
25
DGND2
30
DGND3
36
DGND4
40
DGND5
AGND3
7
AGND4
9
AGND5
45
AGND6
46
32
OP[8]
33
OP[9]
34
OP[10]
37
OP[11]
38
OP[12]
39
OP[13]/SDO
AVDD1
AVDD
43
C
4
AGND
35
DVDD3
C
3
DGND
DVDD1
AVDD2
44
42
NRESET
11
OEB
1.
2.
3.
C1-10 should be fitted as close to WM8195 as possible.
NOTES:
AGND1-6 and DGND1-5 should be connected as close to WM8195 as possible.
DVDD1-3 should be connected as close to WM8195 as possible.
DVDD2, 3
C
11
DVDD1
+
C
12
DVDD2, 3
+
C
13
AVDD1, 2
+
AGND
Figure 27 External Components Diagram
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
100nF
De-coupling for DVDD1.
C2
100nF
De-coupling for DVDD2.
C3
100nF
De-coupling for DVDD3.
C4
100nF
De-coupling for AVDD1 and AVDD2.
C5
10nF
High frequency de-coupling between VRT and VRB.
C6
1
F
Low frequency de-coupling between VRT and VRB (non-polarised).
C7
100nF
De-coupling for VRB.
C8
100nF
De-coupling for VRX.
C9
100nF
De-coupling for VRT.
C10
100nF
De-coupling for VRLC.
C11
1
F
Reservoir capacitor for DVDD1.
C12
1
F
Reservoir capacitor for DVDD2 and DVDD3.
C13
1
F
Reservoir capacitor for AVDD1 and AVDD2.
Table 8 External Components Descriptions
WM8195
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AI Rev 2.0 September 2002
30
PACKAGE DIMENSIONS
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM004.C
FT: 48 PIN TQFP (7 x 7 x 1.0 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
1.20
A
1
0.05
-----
0.15
A
2
0.95
1.00
1.05
b
0.17
0.22
0.27
c
0.09
-----
0.20
D
9.00 BSC
D
1
7.00 BSC
E
9.00 BSC
E
1
7.00 BSC
e
0.50 BSC
L
0.45
0.60
0.75
0
o
3.5
o
7
o
Tolerances of Form and Position
ccc
0.08
REF:
JEDEC.95, MS-026
25
36
e
b
12
1
D1
D
E1
E
13
24
37
48
A
A2
A1
SEATING PLANE
ccc C
-C-
c
L
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WM8195
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AI Rev 2.0 September 2002
31
IMPORTANT NOTICE
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WMterms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WMwarrants performance of its products to the specifications applicable at the time of sale in accordance with WM's
standard warranty. Testing and other quality control techniques are utilised to the extent WMdeems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards.
WMassumes no liability for applications assistance or customer product design. WMdoes not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WMcovering or relating to any combination, machine, or process in which such products or services might
be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's
approval, license, warranty or endorsement thereof.
Reproduction of information from the WMweb site or datasheets is permissable only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WMproduct or service, is an unfair and deceptive
business practice, and WMis not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WMfor that
product or service voids all express and any implied warranties for the associated WMproduct or service, is an unfair and
deceptive business practice, and WMis not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email ::
sales@wolfsonmicro.com
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