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Электронный компонент: WM8197

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WM8197
16-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
WOLFSON MICROELECTRONICS LTD
w :: www.wolfsonmicro.com
Advanced Information September 2002, Rev 2.0
Copyright
2002 Wolfson Microelectronics Ltd.
DESCRIPTION
The WM8197 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12M SPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset Adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 16-bit
analogue-to-digital converter. The digital output data is
available in 16-bit parallel or 8 or 4-bit wide multiplexed
format, with no missing codes.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. Alternatively an external reference level may be
applied. ADC references are generated internally, ensuring
optimum performance from the device.
Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the WM8197 typically
only consumes 210mW when operating from a single 5V
supply and less than 20
A when in power down mode.
FEATURES
16-bit ADC
12MSPS conversion rate
Low power 210mW typical
5V single supply or 5V/3.3V dual supply operation
Single or 3 channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
16-bit parallel or 8 or 4-bit wide multiplexed data output
formats
Internally generated voltage references
48-pin TQFP package
Serial or parallel control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
BLOCK DIAGRAM
M
U
X
RINP
SEN/STB
VSMP
MCLK
VRLC/VBIAS
SDI/DNA
SCK/RNW
TIMING CONTROL
CL
RLC/ACYC
RLC
V
S
R
S
BINP
GINP
VRX
VREF/BIAS
M
U
X
VRB
RLC
RLC
CDS
CDS
CDS
R
G
B
M
U
X
R
G
B
+
PGA
I/P SIGNAL
POLARITY
ADJUST
8
8
PGA
8
8
PGA
8
8
4
+
+
+
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
16-
BIT
ADC
AVDD1-2
+
+
I/P SIGNAL
POLARITY
ADJUST
I/P SIGNAL
POLARITY
ADJUST
DVDD1-3
NRESET
DGND1-5
AGND1-6
DATA
I/O
PORT
OEB
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]
OP[10]
OP[11]
OP[12]
OP[13]
OP[14]
OP[15]/SDO
VRT
w
WM8197
OFFSET
DAC
OFFSET
DAC
OFFSET
DAC
RLC
DAC
M
U
X
WM8197
Advanced Information
w
AI Rev 2.0 September 2002
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8197CFT
0 to 70
C
48-pin TQFP
1mm thick body
VR
T
AVD
D
1
AVD
D
2
AG
N
D
5
AG
N
D
6
VR
B
OP
[
1
3
]
OP
[
1
4
]
O
P
[1
5
]/S
D
O
DG
ND5
NC
N
R
ES
ET
37
47 46 45 44 43 42 41 40 39 38
48
DV
D
D
2
DG
ND
1
OP[
3
]
OP[
0
]
OP[
1
]
OP[
2
]
OP[
4
]
VSMP
SD
I
/
D
N
A
SC
K/
R
N
W
RL
C/
A
C
Y
C
MCL
K
VRX
AGND3
GINP
AGND2
BINP
AGND1
VRLC/VBIAS
RINP
AGND4
DVDD1
OEB
SEN/STB
DGND4
DGND3
OP[9]
OP[10]
OP[11]
OP[12]
DVDD3
DGND2
OP[5]
OP[6]
OP[7]
OP[8]
25
31
30
29
28
27
26
36
35
34
33
32
1
9
8
7
6
5
4
3
2
12
11
10
24
23
16 17 18 19 20 21 22
13 14 15
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
VRX
Analogue output
Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
2
VRLC/VBIAS
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
3
AGND1
Supply
Analogue ground (0V).
4
BINP
Analogue input
Blue channel input video.
5
AGND2
Supply
Analogue ground (0V).
6
GINP
Analogue input
Green channel input video.
7
AGND3
Supply
Analogue ground (0V).
8
RINP
Analogue input
Red channel input video.
9
AGND4
Supply
Analogue ground (0V).
10
DVDD1
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
11
OEB
Digital input
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Serial interface: enable pulse, active high
Parallel interface: strobe, active low
12
SEN/STB
Digital input
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
13
SDI/DNA
Digital input
Serial interface: serial input data signal
Parallel interface:
High = data, Low = address
14
SCK/RNW
Digital input
Serial interface: serial clock signal
Parallel interface:
High: OP[15:8] is output bus.
Low: OP[15:8] is input bus (Hi-Z).
15
VSMP
Digital input
Video sample synchronisation pulse.
16
RLC/ACYC
Digital input
RLC (active high) selects reset level
clamp on a pixel-by-pixel basis tie high
if used on every pixel.
ACYC autocycles between R, G, B
inputs when in Line-by-Line mode.
17
MCLK
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
18
DGND1
Supply
Digital ground (0V).
Advanced Information
WM8197
w
AI Rev 2.0 September 2002
3
PIN
NAME
TYPE
DESCRIPTION
19
OP[0]
20
OP[1]
21
OP[2]
Digital output
22
OP[3]
Digital output
23
OP[4]
Digital output
Pins OP[15:0] form a Hi-Z digital bi-directional bus. There are several modes:
Hi-Z: when OEB = 1.
16-bit output: 16-bit data is output on OP[15:0].
8-bit multiplexed output: data is output on OP[15:8] at 2
ADC conversion rate.
7-bit multiplexed output: data is output on OP[15:8] at 2
ADC conversion rate.
4-bit multiplexed output: data is output on OP[15:12] at 4
ADC conversion rate.
See Output Formats section in Device Description for further details.
Input 8-bit: control data is input on OP[15:8] in parallel mode when SCK/RNW = 0,
and SEN/STB = 0.
Output 8-bit: register read back data is output in parallel on OP[15:8] when
SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.
24
DVDD2
Supply
Digital I/O supply (3.3V/5V).
25
DGND2
Supply
Digital ground (0V).
26
OP[5]
Digital output
27
OP[6]
Digital output
28
OP[7]
Digital output
29
OP[8]
Digital I/O
See pins 21 to 23 for details.
30
DGND3
Supply
Digital ground (0V).
31
OP[9]
Digital I/O
32
OP[10]
Digital I/O
33
OP[11]
Digital I/O
34
OP[12]
Digital I/O
See pins 21 to 23 for details.
35
DVDD3
Supply
Digital I/O supply (3.3V/5V).
36
DGND4
Supply
Digital ground (0V).
37
OP[13]
Digital I/O
38
OP[14]
Digital I/O
39
OP[15]/SDO
Digital I/O
See pins 21 to 23 for details.
If the device has been configured to use the serial interface, pin OP[15]/SDO may
be used to output register read-back data when OEB = 0 and SEN has been
pulsed high.
See Serial Interface sections in Device Description for further details.
40
DGND5
Supply
Digital ground (0V).
41
NC
No connection.
42
NRESET
Digital input
Reset input, active low. This signal forces a reset of all internal registers and selects
whether the serial or parallel control interface is used. See pin SEN/STB.
43
AVDD1
Supply
Analogue supply (5V).
44
AVDD2
Supply
Analogue supply (5V).
45
AGND5
Supply
Analogue ground (0V).
46
AGND6
Supply
Analogue ground (0V).
47
VRB
Analogue output
Lower reference voltage. This pin must be capacitively decoupled to AGND.
48
VRT
Analogue output
Lower reference voltage. This pin must be capacitively decoupled to AGND.
WM8197
Advanced Information
w
AI Rev 2.0 September 2002
4
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Analogue supply voltages: AVDD1, 2
GND - 0.3V
GND + 7V
Digital supply voltages: DVDD1
-
3
GND - 0.3V
GND + 7V
Digital grounds: DGND1
-
5
GND - 0.3V
GND + 0.3V
Analogue grounds: AGND1
-
6
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD2 + 0.3V
Analogue inputs (RINP, GINP, BINP)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
Operating temperature range: T
A
0
C
+70
C
Storage temperature
-65
C
+150
C
Package body temperature (soldering, 10 sec)
+240
C
Package body temperature (soldering, 2 mins)
+183
C
Notes:
1.
GND denotes the voltage of any ground pin.
2.
AGND1
-
6 and DGND1
-
5 pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
Operating temperature range
T
A
0
70
C
Analogue supply voltage
AVDD1, 2
4.75
5.0
5.25
V
Digital core supply voltage
DVDD1
4.75
5.0
5.25
V
5V I/O
DVDD2, 3
4.75
5.0
5.25
V
Digital I/O supply voltage
3.3V I/O
DVDD2, 3
2.97
3.3
3.63
V
Advanced Information
WM8197
w
AI Rev 2.0 September 2002
5
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 24MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion rate
12
MSPS
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.4
4.08
Vp-p
Vp-p
Input signal limits (see Note 2)
V
IN
0
AVDD
V
Full-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
mV
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
mV
Differential non-linearity
DNL
1.25
LSB
Integral non-linearity
INL
20
LSB
Channel to channel gain matching
1
%
Total output noise
Min Gain
Max Gain
3.9
11
LSB rms
LSB rms
References
Upper reference voltage
VRT
2.85
V
Lower reference voltage
VRB
1.35
V
Input return bias voltage
VRX
1.65
V
Diff. reference voltage (VRT-VRB)
V
RTB
1.4
1.5
1.6
V
Output resistance VRT, VRB, VRX
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
50
VRLC short-circuit current
5
mA
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
A
RLCDAC resolution
4
bits
RLCDAC step size, RLCDAC = 0
V
RLCSTEP
0.25
V/step
RLCDAC step size, RLCDAC = 1
V
RLCSTEP
0.17
V/step
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
V
RLCBOT
0.39
V
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
V
RLCBOT
0.26
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
V
RLCTOP
4.16
V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
V
RLCTOP
2.81
V
VRLC deviation
-50
+50
mV
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
Differential non-linearity
DNL
0.1
0.5
LSB
Integral non-linearity
INL
0.25
1
LSB
Step size
2.04
mV/step
Output voltage
Code 00(hex)
Code FF(hex)
-260
+260
mV
mV
Notes:
1.
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.