Document Outline
- WM8739 / WM8739L
- DESCRIPTION
- FEATURES
- APPLICATIONS
- BLOCK DIAGRAM
- PIN CONFIGURATION (SSOP)
- ORDERING INFORMATION (SSOP)
- PIN DESCRIPTION (SSOP PACKAGE)
- PIN CONFIGURATION (QFN)
- ORDERING INFORMATION (QFN)
- PIN DESCRIPTION (QFN PACKAGE)
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS WM8739
- RECOMMENDED OPERATING CONDITIONS WM8739L
- ELECTRICAL CHARACTERISTICS WM8739
- ELECTRICAL CHARACTERISTICS WM8739L
- POWER CONSUMPTION WM8739
- POWER CONSUMPTION - WM8739L
- DIGITAL AUDIO INTERFACE TIMING
- DEVICE DESCRIPTION
- INTRODUCTION
- LINE INPUTS
- ADC
- ADC FILTERS
- CLOCKING SCHEMES
- CRYSTAL OSCILLATOR
- DIGITAL AUDIO INTERFACES
- MASTER AND SLAVE MODE OPERATION
- AUDIO DATA SAMPLING RATES
- ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
- SOFTWARE CONTROL INTERFACE
- POWER DOWN MODES
- REGISTER MAP
- DIGITAL FILTER CHARACTERISTICS
- TERMINOLOGY
- ADC FILTER RESPONSES
- ADC HIGH PASS FILTER
- RECOMMENDED EXTERNAL COMPONENTS
- PACKAGE DIMENSIONS (SSOP)
- PACKAGE DIMENSIONS (QFN)
- IMPORTANT NOTICE
WM8739 / WM8739L
Stereo Audio ADC
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Production Data, December 2002, Rev 3.1
Copyright
2002 Wolfson Microelectronics plc
DESCRIPTION
The WM8739 is a stereo audio ADC. The WM8739 is
designed specifically for portable MP3 audio and speech
players and recorders. The WM8739 is also ideal for MD,
CD-RWmachines and DAT recorders.
Stereo line-level audio inputs are provided, along with a
mute and volume function, and master or slave mode
clocking schemes. The device also has a programmable
high pass filter to remove residual DC offsets.
Stereo 24-bit multi-bit sigma delta ADCs are used with
oversampling digital interpolation and digital filters. Digital
audio output word lengths from 16-32 bits and sampling
rates from 8KHz to 96KHz are supported.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including
volume controls, mutes, de-emphasis and extensive power
management facilities. The device is available in a 20-pin
SSOP package or a 28-lead, 5
5mm QFN package.
FEATURES
90dB SNR (`A' weighted @ 48kHz) ADC
Low Power
-
Recording: 37mW(WM8739) / 12mW(WM8739L)
-
Standby and Powerdown modes down to 1
A
Low Supply Voltages
-
1.8 3.6V Analogue Supply (`L' version)
-
2.7 3.6V Analogue Supply (standard version)
-
1.42 3.6V Digital Supply (both versions)
Selectable Sample Rate: 8KHz 96KHz
Selectable ADC High Pass Filter
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes
-
I
2
S, Left, Right Justified or DSP
-
16/20/24/32 bit Word Lengths
-
Master or Slave Clocking Mode
20-Pin SSOP or 5x5mm QFN Package Options
APPLICATIONS
CD, Minidisc and DAT Recorders
General Purpose Audio Digitisation
BLOCK DIAGRAM
VOL/
MUTE
VOL/
MUTE
ADC
ADC
DIGITAL
FILTERS
CONTROL INTERFACE
CS
B
SD
I
N
SC
L
K
RLINEIN
LLINEIN
VMID
DBV
D
D
DG
ND
AVDD
AGND
+12 to -34.5dB,
1.5dB Steps
+12 to -34.5dB,
1.5dB Steps
DC
V
D
D
ADCLRC
ADCDAT
DIV2
X
T
I/M
CL
K
XT
O
MO
D
E
DI
G
T
A
L
AU
DI
O
I
N
T
E
R
F
ACE
BCLK
OSC
W
WM8739
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
2
PIN CONFIGURATION (SSOP)
ORDERING INFORMATION (SSOP)
DEVICE
AVDD RANGE
PACKAGE
XWM8739EDS
2.7 to 3.6V
20-pin SSOP
XWM8739EDS/R
2.7 to 3.6V
20-pin SSOP
(tape and reel)
WM8739LEDS
1.8 to 3.6V
20-pin SSOP
WM8739LEDS/R
1.8 to 3.6V
20-pin SSOP
(tape and reel)
SDIN
SCLK
XTI/MCLK
XTO
DCVDD
DGND
DBVDD
BCLK
DNC
DNC
CSB
MODE
LLINEIN
RLINEIN
VMID
AGND
AVDD
NC
ADCLRC
ADCDAT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Note:
Reel quantity = 2,000
PIN DESCRIPTION (SSOP PACKAGE)
PIN
NAME
TYPE
DESCRIPTION
1
SDIN
Digital Input
3-Wire MPU Data Input / 2-Wire MPU Data Input
2
SCLK
Digital Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
3
XTI/MCLK
Digital Input
Crystal Input or Master Clock Input (MCLK)
4
XTO
Digital Output
Crystal Output
5
DCVDD
Supply
Digital Core VDD
6
DGND
Ground
Digital GND
7
DBVDD
Supply
Digital Buffers VDD
8
BCLK
Digital Input/Output
Digital Audio Port Clock
9
DNC
Test pin
Do not connect (leave this pin floating)
10
DNC
Test pin
Do not connect (leave this pin floating)
11
ADCDAT
Digital Output
ADC Digital Audio Data Output
12
ADCLRC
Digital Input/Output
ADC Sample Rate Clock
13
NC
No Internal Connection
14
AVDD
Supply
Analogue VDD
15
AGND
Ground
Analogue GND
16
VMID
Analogue Output
Mid-rail reference decoupling point
17
RLINEIN
Analogue Input
Right Channel Line Input (AC coupled)
18
LLINEIN
Analogue Input
Left Channel Line Input (AC coupled)
19
MODE
Digital Input
Control Interface Selection, Pull up (on power up only)
20
CSB
Digital Input
3-Wire MPU Chip Select/ 2-Wire MPU interface address selection
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
3
PIN CONFIGURATION (QFN)
ORDERING INFORMATION (QFN)
DEVICE
AVDD RANGE
PACKAGE
WM8739EFL
2.7 to 3.6V
28-pin QFN
(5x5x0.9 mm)
WM8739EFL/R
2.7 to 3.6V
28-pin QFN
(5x5x0.9 mm)
(tape and reel)
WM8739LEFL
1.8 to 3.6V
28-pin QFN
(5x5x0.9 mm)
WM8739LEFL/R
1.8 to 3.6V
28-pin QFN
(5x5x0.9 mm)
(tape and reel)
NC
NC
NC
ADCLRC
ADCDAT
DNC
DNC
X
T
I/MCLK
XT
O
DCVD
D
DGN
D
DB
VD
D
NC
BC
L
K
28
27
26
25
24
23
22
NC
RLINEIN
LLINEIN
MODE
CSB
SDIN
SCLK
1
2
3
4
5
6
7
8
10
9
11
14
13
12
21 20
19
18 17
16 15
NC
VM
I
D
AG
N
D
AV
D
D
NC
NC
NC
Note:
Reel quantity = 3,500
PIN DESCRIPTION (QFN PACKAGE)
PIN
NAME
TYPE
DESCRIPTION
1
XTI/MCLK
Digital Input
Crystal Input or Master Clock Input (MCLK)
2
XTO
Digital Output
Crystal Output
3
DCVDD
Supply
Digital Core VDD
4
DGND
Ground
Digital GND
5
DBVDD
Supply
Digital Buffers VDD
6
NC
No Internal Connection
7
BCLK
Digital Input/Output
Digital Audio Port Clock
8, 9
DNC
Test pin
Do not connect (leave this pin floating)
10
ADCDAT
Digital Output
ADC Digital Audio Data Output
11
ADCLRC
Digital Input/Output
ADC Sample Rate Clock
12 - 17
NC
No Internal Connection
18
AVDD
Supply
Analogue VDD
19
AGND
Ground
Analogue GND
20
VMID
Analogue Output
Mid-rail reference decoupling point
21, 22
NC
No Internal Connection
23
RLINEIN
Analogue Input
Right Channel Line Input (AC coupled)
24
LLINEIN
Analogue Input
Left Channel Line Input (AC coupled)
25
MODE
Digital Input
Control Interface Selection, Pull up (on power up only)
26
CSB
Digital Input
3-Wire MPU Chip Select/ 2-Wire MPU interface address selection
27
SDIN
Digital Input
3-Wire MPU Data Input / 2-Wire MPU Data Input
28
SCLK
Digital Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
4
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling
and storage of this device.
The WM8739 and WM8739L (in both SSOP and QFN packages) have been classified as MSL1, which has an unlimited floor life at
<30
C / 85% RH.
CONDITION
MIN
MAX
Digital supply voltage
-0.3V
+3.63V
Analogue supply voltage
-0.3V
+3.63
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Master Clock Frequency
18.432MHz
Operating temperature range, T
A
-25
C
+85
C
Storage temperature prior to soldering
30
C max / 85% RH max
Storage temperature after soldering
-65
C
+150
C
Package body temperature (soldering 10 seconds)
+260
C
Package body temperature (soldering 2 minutes)
+183
C
Notes
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
The digital supply core voltage must always be less than or equal to the analogue supply voltage or digital supply buffer
voltage.
3.
The digital supply buffer voltage must always be less than or equal to the analogue supply voltage.
RECOMMENDED OPERATING CONDITIONS WM8739
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
DCVDD
1.42
3.3
3.6
V
Digital supply range (Buffer)
DBVDD
2.7
3.3
3.6
V
Analogue supply range
AVDD
2.7
3.3
3.6
V
Ground
DGND,AGND
0
V
RECOMMENDED OPERATING CONDITIONS WM8739L
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
DCVDD
1.42
3.3
3.6
V
Digital supply range (Buffer)
DBVDD
1.8
3.3
3.6
V
Analogue supply range
AVDD
1.8
3.3
3.6
V
Ground
DGND,AGND
0
V
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
5
ELECTRICAL CHARACTERISTICS WM8739
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOWlevel
V
IL
0.3 x VDD
V
Input HIGH level
V
IH
0.7 x VDD
V
Output LOW
V
OL
0.1 x VDD
V
Output HIGH
V
OH
0.9 x VDD
V
Analogue Reference Levels
Reference voltage
V
VMID
AVDD/2
V
Potential divider resistance
R
VMID
50K
Ohms
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
V
th
0.9
V
Hysteresis
V
IH
0.3
V
DCVDD Threshold Off -> On
V
OL
0.6
V
Input to ADC
Input Signal Level (0dB)
V
INLINE
1.0
AVDD/3.3
Vrms
A-weighted, 0dB gain,
fs = 48kHz
85
90
A-weighted, 0dB gain,
fs = 96kHz
90
Signal to Noise Ratio (Note 1,2)
SNR
A-weighted, 0dB gain,
fs = 48kHz,
AVDD = 2.7V
88
dB
Dynamic Range (Note 2)
DR
A-weighted, -60dB full
scale input
85
90
dB
Total Harmonic Distortion
THD
-1dB input, 0dB gain
-84
0.006
-74
0.02
dB
%
1kHz, 100mVpp
50
Power Supply Rejection Ratio
PSRR
20Hz to 20kHz
100mVpp
45
dB
ADC channel separation
1kHz input
90
dB
Programmable Gain
1kHz input
Rsource < 50 Ohms
-34.5
0
+12
dB
Programmable Gain Step Size
Guaranteed Monotonic
1.5
dB
Mute attenuation
0dB, 1kHz input
80
dB
0dB gain
20k
30k
Input Resistance
R
INLINE
12dB gain
10k
15k
Ohms
Input Capacitance
C
INLINE
10
pF
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
6
ELECTRICAL CHARACTERISTICS WM8739L
All Characteristics not repeated here are the same as for the WM8739.
Test Conditions
AVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input to ADC
A-weighted, 0dB gain
@ fs = 48kHz
75
85
Signal to Noise Ratio (Note 1,2)
SNR
A-weighted, 0dB gain
@ fs = 96kHz
85
dB
Dynamic Range
DR
A-weighted, -60dB full
scale input
80
88
dB
Total Harmonic Distortion
THD
-1dB input, 0dB gain
-76
-60
dB
Notes
1.
Ratio of output level with 1kHz full scale input, to the output level with all zero's into the digital input over a 20Hz to
20kHz bandwidth using an Audio analyser.
2.
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such
a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3.
VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with
a zero signal applied. (No `Auto-zero' or Automute function is employed in achieving these results).
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the r.m.s. values, of (Noise + Distortion)/Signal.
4.
Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
7
POWER CONSUMPTION WM8739
CURRENT CONSUMPTION
TYPICAL
MODE
DESCRIPTION
POW
E
R
O
F
F
OSC
P
D
ADCP
D
LI
NE
I
N
P
D
AVDD
(3.3V)
DCVDD
(1.5V)
DBVDD
(3.3V)
UNIT
Record
Oscillator enabled
0
0
0
0
9.2
2.6
0.8
mA
Using external clock
0
1
0
0
9.2
2.6
0.07
mA
Standby
External clock still
running
0
1
1
1
16
77
65
A
Clock stopped
0
1
1
1
16
0.3
0.2
A
Power Down
External clock still
running
1
1
1
1
0.2
77
65
A
Clock stopped
1
1
1
1
0.3
0.3
0.3
A
POWER CONSUMPTION WM8739L
CURRENT CONSUMPTION
TYPICAL
MODE
DESCRIPTION
POW
E
R
O
F
F
OSC
P
D
ADCP
D
LI
N
E
I
N
P
D
AVDD
(1.8V)
DCVDD
(1.5V)
DBVDD
(1.8V)
UNIT
Record
Oscillator enabled
0
0
0
0
3.9
2.4
0.8
mA
Standby
Clock stopped
0
1
1
1
8
-
-
A
Power Down
Clock stopped
1
1
1
1
1
-
-
A
Table 1 Powerdown Mode Current Consumption Examples
Notes
1.
T
A
= +25
o
C, fs = 48kHz, XTI/MCLK = 256fs (12.288MHz).
2.
All figures are quiescent, with no signal.
3.
The data presented here was measured with the audio interface in master mode whenever the internal clock oscillator
was used, and in slave mode whenever an external clock was used (i.e. MS = 1 when OSCPD = 0 and vice versa).
However, it is also possible to use the WM8739/L with MS = OSCPD = 0 or MS = OSCPD = 1.
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
8
DIGITAL AUDIO INTERFACE TIMING
XTI/MCLK
t
XTIL
t
XTIH
t
XTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
XTI/MCLK System clock pulse width
high
T
XTIH
20
ns
XTI/MCLK System clock pulse width
low
T
XTIL
20
ns
XTI/MCLK System clock cycle time
T
XTIY
50
ns
BCLK
ADCDAT
ADCLRC
WM8739
ADC
DSP
ENCODER
Figure 2 Master Mode Connection
BCLK
(Output)
ADCDAT
ADCLRC
(Output)
t
DL
t
DDA
Figure 3 Digital Audio Data Timing Master Mode
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
9
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC propagation delay
from BCLK falling edge
t
DL
0
10
ns
ADCDAT propagation delay
from BCLK falling edge
t
DDA
0
10
ns
BCLK
ADCDAT
ADCLRC
WM8739
ADC
DSP
ENCODER
Figure 4 Slave Mode Connection
BCLK
ADCLRC
t
BCH
t
BCL
t
BCY
ADCDAT
t
LRSU
t
LRH
t
DD
Figure 5 Digital Audio Data Timing Slave Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
50
ns
BCLK pulse width high
t
BCH
20
ns
BCLK pulse width low
t
BCL
20
ns
ADCLRC set-up time to
BCLK rising edge
t
LRSU
10
ns
ADCLRC hold time from
BCLK rising edge
t
LRH
10
ns
ADCDAT propagation delay
from BCLK falling edge
t
DD
0
10
ns
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
10
MPU INTERFACE TIMING
CSB
SCLK
SDIN
t
CSL
t
DHO
t
DSU
t
CSH
t
SCY
t
SCH
t
SCL
t
SCS
LSB
t
CSS
Figure 6 Program Register Input Timing 3-Wire MPU Serial Control Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
t
SCS
500
ns
SCLK pulse cycle time
t
SCY
80
ns
SCLK pulse width low
t
SCL
20
ns
SCLK pulse width high
t
SCH
20
ns
SDIN to SCLK set-up time
t
DSU
20
ns
SCLK to SDIN hold time
t
DHO
20
ns
CSB pulse width low
t
CSL
20
ns
CSB pulse width high
t
CSH
20
ns
CSB rising to SCLK rising
t
CSS
20
ns
SDIN
SCLK
t
3
t
1
t
6
t
2
t
7
t
5
t
4
t
3
t
8
t
9
Figure 7 Program Register Input Timing 2-Wire MPU Serial Control Mode
WM8739 / WM8739L
Production Data
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PD Rev 3.1 December 2002
11
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
SCLK Low Pulse-Width
t
1
600
ns
SCLK High Pulse-Width
t
2
1.3
us
Hold Time (Start Condition)
t
3
600
ns
Setup Time (Start Condition)
t
4
600
ns
Data Setup Time
t
5
100
ns
SDIN, SCLK Rise Time
t
6
300
ns
SDIN, SCLK Fall Time
t
7
300
ns
Setup Time (Stop Condition)
t
8
600
ns
Data Hold Time
t
9
900
ns
WM8739 / WM8739L
Production Data
w
PD Rev 3.1 December 2002
12
DEVICE DESCRIPTION
INTRODUCTION
The WM8739 is a low power analogue to digital converter (ADC) designed for audio recording. Its
features, performance and low power consumption make it ideal for recordable CD players, MP3
players and portable mini-disc players.
The device includes programmable level line inputs, a crystal oscillator, configurable digital audio
interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner
for a range of industry standard microprocessors, controllers and DSPs.
The WM8739 has low noise line inputs with programmable +12dB to 34.5dB logarithmic volume
adjustments and mute.
The ADC is of a high quality using a multi-bit high-order oversampling architecture delivering
optimum performance with low power consumption. The output from the ADC is available on the
digital audio interface. The ADC includes a digital high pass filter to remove unwanted dc
components from the audio signal.
The design of the WM8739 has given much attention to power consumption without compromising
performance. It includes the ability to power off parts of the circuitry under software control, including
a standby and power off mode.
The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz.
There are two unique schemes featured within the programmable sample rates of the WM8739:
Normal industry standard 256/384 fs sampling mode may be used. A special USB sampling mode is
also included, whereby all audio sampling rates can be generated from a 12.00MHZ USB clock. The
WM8739's unique sample rate converter thus allows the user to generate the required sampling rate
clocks from the 12MHz USB clock. The digital filters used for recording are optimised for each
sampling rate used.
The digitised output is available in a number of audio data formats I
2
S, DSP Mode (a burst mode in
which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First,
right justified. The digital audio interface can operate in both master or slave modes.
The WM8739 can generate the system master clock using an on-chip crystal oscillator, or
alternatively it can accept an external master clock from the audio system. All features are software
controlled using either a 2 or 3-wire MPU interface.
LINE INPUTS
The WM8739 provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are
high impedance and low capacitance, thus ideally suited to receiving line level signals from external
Hi-Fi and other audio equipment.
Both line inputs include independent programmable volume level adjustments and mutes. The
scheme is illustrated in Figure 8. Passive RF and active Anti-Alias filters are also incorporated within
the line inputs. These prevent high frequencies aliasing into the audio band or otherwise degrading
performance.
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12.5K
VMID
LINEIN
To
ADC
Figure 8 Line Input Schematic
LINE INPUT SCHEMATIC
The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to 34.5dB in
1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any
voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full
scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left
Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both
channels are simultaneously updated. Use of INBOTH reduces the required number of software
writes required. The line inputs can be muted in the analogue domain under software control. The
software control registers are shown below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
4:0
LINVOL[0:4]
10111
( 0dB )
Left Channel Line Input Volume Control
11111 = +12dB
. . 1.5dB steps down to
00000 = -34.5dB
7
LINMUTE
1
Left Channel Line Input Mute
1 = Enable Mute
0 = Disable Mute
0000000
Left Line In
8
LRINBOTH
0
Left to Right Channel Line Input Volume
and Mute Data Load Control
1 = Enable Simultaneous Load of
LINVOL[0:4] and LINMUTE to
RINVOL[0:4] and RINMUTE
0 = Disable Simultaneous Load
4:0
RINVOL[0:4]
10111
( 0dB )
Right Channel Line Input Volume Control
11111 = +12dB
. . 1.5dB steps down to
00000 = -34.5dB
7
RINMUTE
1
Left Channel Line Input Mute
1 = Enable Mute
0 = Disable Mute
0000001
Right Line In
8
RLINBOTH
0
Right to Left Channel Line Input Volume
and Mute Data Load Control
1 = Enable Simultaneous Load of
RINVOL[0:4] and RINMUTE to
LINVOL[0:4] and LINMUTE
0 = Disable Simultaneous Load
Table 2 Line Input Software Control
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The line inputs are biased internally through the operational amplifier to VMID. Whenever the line
inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID
using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when
re-activating the inputs.
The external components required to complete the line input application are shown in the Figure 9.
AGND
AGND
R1
R2
C1
C2
AGND
LINEIN
Figure 9 Line Input Application Drawing
For interfacing to a typical CD system, it is recommended that the input is scaled to ensure that there
is no clipping at the input. R1 = 5K, R2= 5K, C1=47pF, C2=470nF (10V ceramic type).
R1 and R2 form a resistive divider to attenuate the 2 Vrms output from a CD player to a 1 Vrms level,
so avoiding overloading the inputs. R2 also provides a discharge path for C2, thus preventing the
input to C2 charging to an excessive voltage which may otherwise damage any equipment connected
that is not suitably protected against high voltages. C1 forms an RF low pass filter for increasing the
rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove
the DC path between the WM8739 and the driving audio equipment. C2 together with the input
impedance of the WM8739 form a high pass filter.
ADC
The WM8739 uses a multi-bit
oversampled sigma-delta ADC. A single channel of the ADC is
illustrated in the Figure 10.
ANALOG
INTEGRATOR
FROM LINE
INPUT
MULTI
BITS
TO ADC DIGITAL FILTERS
Figure 10 Multi-Bit Oversampling Sigma Delta ADC Schematic
The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
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The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will
possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with
AVDD.
The device employs a pair of ADCs. The two channels cannot be selected independently.
The digital data from the ADC is fed for signal processing to the ADC Filters.
ADC FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 11
illustrates the digital filter path.
FROM ADC
DIGITAL
HPF
DIGITAL
FILTER
TO DIGITAL
AUDIO
INTERFACE
DIGITAL
DECIMATOR
HPFEN
Figure 11 ADC Digital Filter
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass
filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is
enabled the dc offset is continuously calculated and subtracted from the input signal. By setting
HPOR the last calculated dc offset value is stored when the high-pass filter is disabled and will
continue to be subtracted from the input signal. If the dc offset changed, the stored and subtracted
value will not change unless the high-pass filter is enabled. The software control is shown in Table 3.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
ADCHPD
0
ADC High Pass Filter Enable (Digital)
1 = Disable High Pass Filter
0 = Enable High Pass Filter
0000101
Audio Path Control
4
HPOR
0
Store dc offset when High Pass Filter
disabled
1 = store offset
0 = clear offset
Table 3 ADC Software Control
There are several types of ADC filter, the frequency and phase responses of which are shown in
Digital Filter Characteristics. The filter types are automatically configured depending on the sample
rate chosen. Refer to the sample rate section for more details.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system's
Master Clock. To allow WM8739 to be used in a centrally clocked system, the WM8739 is capable of
either generating this `system' clock itself or receiving it from an external source as will be discussed.
For applications where it is desirable that the WM8739 is the system clock source, then clock
generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input
and XTO output pins (see CRYSTAL OSCILLATOR section).
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For applications where a component other than the WM8739 will generate the reference clock, the
external system can be applied directly through the XTI/MCLK input pin with no software
configuration necessary. Note that in this situation, the oscillator circuit of the WM8739 can be safely
powered down to conserve power (see POWER DOWN section)
CRYSTAL OSCILLATOR
The WM8739 includes a crystal oscillator circuit that allows the audio system's reference clock to be
generated on the device. The crystal oscillator is a low radiation type, designed for low EMC. A
typical application circuit is shown in Figure 12.
XTI/MCLK
XTO
DGND
DGND
Cp
Cp
Figure 12 Crystal Oscillator Application Circuit
For crystals with a 30pF fundamental load capacitance, a value of 5pF for Cp is recommended.
The WM8739 crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a
requirement for a high quality audio ADC, regardless of the converter architecture. The WM8739
architecture is less susceptible than most converter techniques but still requires clocks with less than
approximately 1ns of jitter to maintain performance. In applications where there is more than one
source for the master clock, it is recommended that the clock is generated by the WM8739 to
minimise such problems.
CORE CLOCK
The WM8739 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 4 below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
Sampling
Control
6
CLKIDIV2
0
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Table 4 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
DIGITAL AUDIO INTERFACES
WM8739 may be operated in either one of the 4 offered audio interface modes. These are:
Right justified
Left justified
I
2
S
DSP mode
All four of these modes are MSB first.
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The digital audio interface takes the data from the internal ADC digital filters and places it on
ADCDAT and ADCLRC. ADCDAT is the formatted digital audio data stream output from the ADC
digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that
controls whether Left or Right channel data is present on the ADCDAT line. ADCDAT and ADCLRC
are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. ADCDAT is always an output.
BCLK and ADCLRC maybe an input or an output
depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE
OPERATION section.
There are four digital audio interface formats accommodated by the WM8739. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a
ADCLRC transition.
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
ADCDAT
1/fs
n
3
2
1
n-2
n-1
LSB
MSB
n
3
2
1
n-2
n-1
LSB
MSB
Figure 13 Left Justified Mode
I
2
S mode is where the MSB is available on the 2nd rising edge of BCLK following an ADCLRC
transition.
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
ADCDAT
1/fs
n
3
2
1
n-2
n-1
LSB
MSB
n
3
2
1
n-2
n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 14 I
2
S Mode
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding an ADCLRC
transition, yet MSB is still transmitted first.
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LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
ADCDAT
1/fs
n
3
2
1
n-2
n-1
LSB
MSB
n
3
2
1
n-2
n-1
LSB
MSB
Figure 15 Right Justified Mode
DSP mode is where the left channel MSB is available on either the 1
st
or 2
nd
rising edge of BCLK
(selectable by LRP) following a ADCLRC transition high. Right channel data immediately follows left
channel data.
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
ADCDAT
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
1 B CLK
Input Word Length (IWL)
Note: Input word length is defined by the IWL register, LRP = 1
1/fs
Figure 16 DSP Mode
The ADC digital audio interface modes are software configurable as indicated in Figure 16. Note that
dynamically changing the software format may results in erroneous operation of the interfaces and is
therefore not recommended.
The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software
control table below. The data is signed 2's complement. The ADC digital filters process data using 24
bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data.
If the ADC is programmed to output 32 bits then it packs the LSBs with zeros.
ADCDAT is always an output. It powers up and returns from standby `low'.
ADCLRC and BCLK can be either outputs or inputs depending on whether the device is configured
as a master or slave. If the device is a master then the ADCLRC and BCLK signals are outputs that
default low. If the device is a slave then the ADCLRC and BCLK are inputs.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
1:0
FORMAT[1:0]
10
Audio Data Format Select
11 = DSP Mode, frame sync + 2 data
packed words
10 = I
2
S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
3:2
IWL[1:0]
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after LRC rising edge
0 = MSB is available on 1st BCLK
rising edge after LRC rising edge
0000111
Digital Audio
Interface Format
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Table 5 Digital Audio Interface Control
Note:
Right justified 32 bit mode is not supported, but if selected, will put the WM8739 into 24 bit right
justified mode.
MASTER AND SLAVE MODE OPERATION
The WM8739 can be configured as either a master or slave mode device. As a master mode device
the WM8739 controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8739 responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 6.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
Digital Audio
Interface
Format
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Table 6 Programming Master/Slave Modes
As a master mode device the WM8739 controls the sequencing of data transfer (ADCDAT) and
output of clocks (BCLK, ADCLRC) over the digital audio interface. It uses the timing generated from
either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This
is illustrated in Figure 17. ADCDAT is always an output from the WM8739 independent of master or
slave mode.
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BCLK
ADCDAT
ADCLRC
WM8739
ADC
DSP
ENCODER
Figure 17 Master Mode
As a slave device the WM8739 sequences the data transfer (ADCDAT) over the digital audio
interface in response to the external applied clocks (BCLK, ADCLRC). This is illustrated Figure 18.
BCLK
ADCDAT
ADCLRC
WM8739
ADC
DSP
ENCODER
Figure 18 Slave Mode
AUDIO DATA SAMPLING RATES
The WM8739 provides for two modes of operation (normal and USB) to generate the required ADC
sampling rate. Normal and USB modes are programmed under software control according to the
table below.
In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal
frequency and the sample rate control register setting. The WM8739 can support sample rates from
8ks/s up to 96ks/s.
In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample
rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus)
clock is at 12MHz and the WM8739 can be directly used within such systems. WM8739 can
generate all the normal audio sample rates from this one Master Clock frequency, removing the need
for different master clocks or PLL circuits.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
USB/
NORMAL
0
Mode Select
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
1
BOSR
0
Base Over-Sampling Rate
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
0001000
Sampling
Control
5:2
SR[3:0]
0000
ADC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Table 7 Sample Rate Control
NORMAL MODE SAMPLE RATES
In normal mode MCLK/crystal oscillator is set up according to the desired sample rate of the ADC.
For ADC sampling rates of 8, 32, 48 or 96KHz, MCLK frequencies of either 12.288MHz (256fs) or
18.432MHz (384fs) can be used. For ADC sampling rates of 8, 44.1 or 88.2KHz from MCLK
frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.
The table below should be used to set up the device to work with the various sample rate
combinations. For example if the user wishes to use the WM8739 in normal mode with the ADC
sample rate at 48KHz, then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0,
SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and
SR0 = 0 with a 18.432MHz MCLK. The ADC will then operate with a Digital Filter of type 1, refer to
Digital Filter Characteristics section for an explanation of the different filter types.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
12.288
0
0
0
0
0
48
18.432
1
0
0
0
0
1
12.288
0
0
0
1
0
8
18.432
1
0
0
1
0
1
12.288
0
0
1
1
0
32
18.432
1
0
1
1
0
1
12.288
0
0
1
1
1
96
18.432
1
0
1
1
1
2
11.2896
0
1
0
0
0
44.1
16.9344
1
1
0
0
0
1
11.2896
0
1
0
1
0
8 (Note 1)
16.9344
1
1
0
1
0
1
11.2896
0
1
1
1
1
88.2
16.9344
1
1
1
1
1
2
Table 8 Normal Mode Sample Rate Look-up Table
Notes:
1.
8k not exact, actual = 8.018kHz
2.
All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8739 digital signal
processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the
actual audio data rate produced by the ADC.
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Example scenarios are:
1.
with a requirement that the ADC data rate is 8kHz, then choosing MCLK = 12.288MHz the
device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC
output data rate will then be exactly 8kHz (derived from 12.288MHz/256 x1/6)
2.
with a requirement that ADC data rate is 8kHz, then choosing MCLK = 16.9344MHz the device
is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1 = 0, SR0 = 1. The ADC will no
longer output data at exactly 8.000KHz, instead it will be 8.018kHz (derived from
16.9344MHz/384 x 2/11). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio
data and (importantly) the user must ensure that the data across the digital interface is correctly
synchronised at the 8.018kHz rate.
The exact sample rates achieved are defined by the relationships in Table 9.
ACTUAL SAMPLING RATE
BOSR=0
(256fs)
BOSR=1
(384fs)
TARGET
SAMPLING
RATE
MCLK=12.288
MCLK=11.2896
MCLK=18.432
MCLK=16.9344
kHz
kHz
kHz
kHz
kHz
8
8.018
8
8.018
8
12.288MHz/256 x 1/6
11.2896MHz/256 x 2/11
18.432MHz/384 x 1/6
16.9344MHz/384 x 2/11
32
32
32
12.288MHz/256 x 2/3
not available
18.432MHz/384x 2/3
not available
44.1
44.1
44.1
not available
11.2896MHz/256
not available
16.9344MHz /384
48
48
48
12.288MHz/256
not available
18.432MHz/384
not available
88.2
88.2
88.2
not available
11.2896MHz/384 x 2
not available
16.9344MHz /384 x 2
96
96
96
12.288MHz/256 x 2
not available
18.432MHz/384 x 2
not available
Table 9 Normal Mode Actual Sample Rates
128/192fs NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the
WM8739 is also capable of being clocked from a 128/192fs MCLK for application over limited
sampling rates as shown in the table below.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
6.144
0
0
1
1
1
48
9.216
1
0
1
1
1
2
5.6448
0
1
1
1
1
44.1
8.4672
1
1
1
1
1
2
Table 10 128/192fs Normal Mode Sample Rate Look-up Table
512/768fs NORMAL MODE
512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to
the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the
device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 4 for
software control.
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USBMODE SAMPLE RATES
In USB mode the MCLK/crystal oscillator input is 12MHz only.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
48
12.000
0
0
0
0
0
0
44.1 (Note 2)
12.000
1
1
0
0
0
1
8
12.000
0
0
0
1
0
0
8 (Note 1)
12.000
1
1
0
1
0
1
32
12.000
0
0
1
1
0
0
96
12.000
0
0
1
1
1
3
88.2 (Note 3)
12.000
1
1
1
1
1
2
Table 11 USBMode Sample Rate Look-up Table
Notes:
1.
8k not exact, actual = 8.021kHz
2.
44.1k not exact, actual = 44.118kHz
3.
88.2k not exact, actual = 88.235kHz
4.
All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The table above can be used to set up the device to work with various sample rate combinations. For
example if the user wishes to use the WM8739 in USB mode with the ADC sample rate at 48kHz,
then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0.
The ADC will then operate with a Digital Filter of type 0, refer to Digital Filter Characteristics section
for an explanation of the different filter types.
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8739 digital signal
processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode,
with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over-
sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate
produced by the ADC.
Example scenarios are:
1.
with a requirement that the ADC data sampling rate is 8KHz the device is programmed with
BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC will then be exactly 8kHz
(derived from 12MHz/250 x 1/6).
2.
with a requirement that ADC data rate is 8KHz the device is programmed with BOSR = 1
(272fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not output data at exactly 8kHz,
instead it will be 8.021kHz (derived from 12MHz/272 x 2/11). A slight (sub 0.5%) pitch shift will
therefore result in the 8kHz audio data and (more importantly) the user must ensure that the
data across the digital interface is correctly synchronised at the 8.021kHz rate.
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The exact sample rates supported for all combinations are defined by the relationships in Table 12
below.
ACTUAL SAMPLING RATE
TARGET
SAMPLING
RATE
BOSR=0
( 250fs)
BOSR=1
(272fs)
kHz
kHz
kHz
8
8.021
8
12MHz/(250 x 48/8)
12MHz/(272 x 11/2)
32
32
12MHz/(250 x 48/32)
not available
44.117
44.1
not available
12MHz/272
48
48
12MHz/250
not available
88.235
88.2
not available
12MHz/136
96
96
12MHz/125
not available
Table 12 USBMode Actual Sample Rates
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface the Audio
Interface is disabled (tristate).
Once the Audio Interface and the Sampling Control has been
programmed it is activated by setting the ACTIVE bit under Software Control.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001001
Active Control
0
ACTIVE
0
Activate Interface
1 = Active
0 = Inactive
Table 13 Activating DSP and Digital Audio Interface
It is recommended that between changing any content of Digital Audio Interface or Sampling Control
Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire or 2-wire MPU interface.
Selection of interface format is achieved by setting the state of the MODE pin.
In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and
CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is
used for the serial clock. In 2-wire mode, the state of the CSB pin allows the user to select one of two
addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire mode. This is achieved
by setting the state of the MODE pin.
MODE
INTERFACE FORMAT
0
2 wire
1
3 wire
Table 14 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
The WM8739 can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is used to latch in the program data. The 3-wire
interface protocol is shown in Figure 19.
WM8739 / WM8739L
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CSB
SCLK
SDIN
B15
B6
B7
B8
B9
B10
B11
B12
B13
B14
B1
B2
B3
B4
B5
B0
Figure 19 3-Wire Serial Interface
Notes:
1.
B[15:9] are Control Address Bits
2.
B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8739 supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8739 has one of two slave addresses that are selected by setting the state of pin 20, (CSB).
SDIN
SCLK
ACK
R ADDR
ACK
DATA B15-8
STOP
START
DATA B7-0
R/W
ACK
Figure 20 2-Wire Serial Interface
Notes:
1.
B[15:9] are Control Address Bits
2.
B[8:0] are Control Data Bits
CSBSTATE
(DEFAULT = LOW)
ADDRESS
0
0011010
1
0011011
Table 15 2-Wire MPU Interface Address Selection
To control the WM8739 on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/Wbit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see Table 15). If the correct address is received and the R/W
bit is `0', indicating a write, then the WM8739 will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8739 is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
Once the WM8739 has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8739 will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8739 will then
acknowledge again by pulling SDIN low.
A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a
start or stop condition is detected out of sequence at any point in the data transfer then the device
will jump to the idle condition.
WM8739 / WM8739L
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After receiving a complete address and data sequence the WM8739 returns to the idle state and
waits for another start condition. Each write to a register requires the complete sequence of start
condition, device address and R/Wbit followed by the 16 register address and data bits.
POWER DOWN MODES
The WM8739 contains power conservation modes in which various circuit blocks may be safely
powered down in order to conserve power. This is software programmable as shown in the table
below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
LINEINPD
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
2
ADCPD
1
ADC Power Down
1 = Enable Power Down
0 = Disable Power Down
5
OSCPD
0
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
0000110
Power Down
Control
7
POWEROFF
1
Power Off Device
1 = Device Power Off
0 = Device Power On
Table 16 Power Conservation Modes Software Control
Unused register bits 1,3,4,6 should be set to `1' when writing to this register. The power down control
can be used to either a) permanently disable functions when not required in certain applications or b)
to dynamically power up and down functions depending on the operating mode, e.g.: during playback
or record. Please follow the special instructions below if dynamic implementations are being used.
OSCPD: Powers off the on board crystal oscillator. The MCLK input will function independently of the
Oscillator being powered down.
The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry
under software control as shown in Table 17.
POW
E
R
O
F
F
OSC
P
D
ADCP
D
LI
NE
I
N
P
D
DESCRIPTION
0
0
1
1
STANDBY, but with Crystal
Oscillator
0
1
1
1
STANDBY, Crystal oscillator
not-available.
Table 17 Standby Mode
In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue
circuitry remain active. The active analogue includes the analogue VMID reference so that the
analogue line inputs remain biased to VMID. This reduces any audible effects caused by DC glitches
when entering or leaving STANDBY mode.
WM8739 / WM8739L
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27
The device can be powered off by writing to the POWEROFF bit of the Power Down register. In
POWEROFF mode the Control Interface and a small portion of the digital remain active. The
analogue VMID reference is disabled. As in STANDBY mode the crystal oscillator pin can be
independently controlled. Refer to Table 18.
PO
WE
R
O
F
F
OS
C
P
D
AD
CP
D
LINE
INP
D
DESCRIPTION
1
0
X
X
POWEROFF, but with Crystal
Oscillator OSC available
1
1
X
X
POWEROFF, Crystal
oscillator not-available
Table 18 Power Off Mode
DEVICE RESETTING
The WM8739 contains a power on reset circuit that resets the internal state of the device to a known
condition. The power on reset is applied as DCVDD powers on and released only after the voltage
level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on
threshold voltage then the power on reset is re-applied. The threshold voltages and associated
hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001111
Reset Register
8:0
RESET
not reset
Reset Register
Writing 00000000 to register resets
device
Table 19 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 20).
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28
REGISTER MAP
The complete register map is shown in Table 20. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
B
15
B
14
B
13
B
12
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
R0 (00h)
0
0
0
0
0
0
0
LRIN
BOTH
LIN
MUTE
0
0
LINVOL
R1 (02h)
0
0
0
0
0
0
1
RLIN
BOTH
RIN
MUTE
0
0
RINVOL
R5 (0Ah)
0
0
0
0
1
0
1
0
0
0
0
HPOR
0
0
0
ADC
HPD
R6 (0Ch)
0
0
0
0
1
1
0
0
PWR
OFF
1
OSCPD
1
1
ADCPD
1
LINEIN
PD
R7 (0Eh)
0
0
0
0
1
1
1
0
0
MS
0
LRP
IW
L
FORMAT
R8 (10h)
0
0
0
1
0
0
0
0
0
CLKI
DIV2
SR
BOSR
USB/
NORM
R9 (12h)
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
ACTIVE
R15(1Eh)
0
0
0
1
1
1
1
RESET
ADDRESS
DATA
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
4:0
LINVOL[0:4]
10111
( 0dB )
Left Channel Line Input Volume Control
11111 = +12dB . . 1.5dB steps down to
00000 = -34.5dB
7
LINMUTE
1
Left Channel Line Input Mute
1 = Enable Mute
0 = Disable Mute
0000000
Left Line In
8
LRINBOTH
0
Left to Right Channel Line Input Volume
and Mute Data Load Control
1 = Enable Simultaneous Load of
LINVOL[0:4] and LINMUTE to
RINVOL[0:4] and RINMUTE
0 = Disable Simultaneous Load
4:0
RINVOL[0:4]
10111
( 0dB )
Right Channel Line Input Volume
Control
11111 = +12dB . .1.5dB steps down to
00000 = -34.5dB
7
RINMUTE
1
Left Channel Line Input Mute
1 = Enable Mute
0 = Disable Mute
0000001
Right Line In
8
RLINBOTH
0
Right to Left Channel Line Input Volume
and Mute Data Load Control
1 = Enable Simultaneous Load of
RINVOL[0:4] and RINMUTE to
LINVOL[0:4] and LINMUTE
0 = Disable Simultaneous Load
WM8739 / WM8739L
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PD Rev 3.1 December 2002
29
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
ADCHPD
0
ADC High Pass Filter Enable (Digital)
1 = Disable High Pass Filter
0 = Enable High Pass Filter
0000101
Digital Audio Path
Control
4
HPOR
0
Store dc offset when High Pass Filter
disabled
1 = store offset
0 = clear offset
0
LINEINPD
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
2
ADCPD
1
ADC Power Down
1 = Enable Power Down
0 = Disable Power Down
5
OSCPD
0
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
0000110
Power Down
Control
7
POWEROFF
1
POWEROFF mode
1 = Enable POWEROFF
0 = Disable POW EROFF
1:0
FORMAT[1:0]
10
Audio Data Format Select
11 = DSP Mode, frame sync + 2 data
packed words
10 = I
2
S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
3:2
IWL[1:0]
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK rising
edge after LRC rising edge
0 = MSB is available on 1st BCLK rising
edge after LRC rising edge
0000111
Digital Audio
Interface Format
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
0
USB/
NORMAL
0
Mode Select
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
1
BOSR
0
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
5:2
SR[3:0]
0000
(fs)
ADC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
0001000
Sampling
Control
6
CLKIDIV2
0
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
WM8739 / WM8739L
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PD Rev 3.1 December 2002
30
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001001
Active Control
0
ACTIVE
0
Activate Interface
1 = Active
0 = Inactive
0001111
Reset Register
8:0
RESET
not reset
Reset Register
Write 000000000 to register triggers
reset
Table 20 Register Map Description
Note
1.
All other bits not explicitly defined in the register table should be set to zero, unless specified
otherwise (see Powerdown section).
DIGITAL FILTER CHARACTERISTICS
The ADC employs different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3.
The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in
the proceeding pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Filter Type 0 (USBMode, 250fs operation)
+/- 0.05dB
0
0.416fs
Passband
-6dB
0.5fs
Passband Ripple
+/- 0.05
dB
Stopband
0.584fs
Stopband Attenuation
f > 0.584fs
-60
dB
ADC Filter Type 1 (USBmode, 272fs or Normal mode operation)
+/- 0.05dB
0
0.4535fs
Passband
-6dB
0.5fs
Passband Ripple
+/- 0.05
dB
Stopband
0.5465fs
Stopband Attenuation
f > 0.5465fs
-60
dB
High Pass Filter Corner
Frequency
-3dB
-0.5dB
-0.1dB
3.7
10.4
21.6
Hz
Table 21 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple any variation of the frequency response in the pass-band region
WM8739 / WM8739L
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31
ADC FILTER RESPONSES
-100
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 21 ADC Digital Filter Frequency Response Type 0
Figure 22 ADC Digital Filter Ripple Type 0
-100
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 23 ADC Digital Filter Frequency Response Type 1
Figure 24 ADC Digital Filter Ripple Type 1
-100
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0
0.05
0.1
0.15
0.2
0.25
Response (dB)
Frequency (Fs)
Figure 25 ADC Digital Filter Frequency Response Type 2
Figure 26 ADC Digital Filter Ripple Type 2
WM8739 / WM8739L
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PD Rev 3.1 December 2002
32
-100
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0
0.05
0.1
0.15
0.2
0.25
Response (dB)
Frequency (Fs)
Figure 27 ADC Digital Filter Frequency Response Type 3
Figure 28 ADC Digital Filter Ripple Type 3
ADC HIGH PASS FILTER
The WM8739 has a selectable digital high pass filter to remove DC offsets. The filter response is
characterised by the following polynomial.
H(z) =
1 z
-1
1 0.9995 z
-1
WM8739 / WM8739L
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PD Rev 3.1 December 2002
33
RECOMMENDED EXTERNAL COMPONENTS
Audio Serial Data I/F
3-wire Interface
2-wire Interface
WM8739
ADC
VMID
AVDD
AGND
14
15
3.3V
0.1
F
10
F
+
16
ADCLRC
ADCDAT
DBVDD
DCVDD
3.3V
DGND
1.5V - 3.3V
+
+
7
6
5
BCLK
8
12
11
SDIN
1
CSB
19
SCLK
20
MODE
2
10
F
0.1
F
XTO
XTI/MCLK
15pF
15pF
4
3
+
10
F
RLINEIN
5K
5K
47pF
+
470nF
17
LLINEIN
5K
5K
47pF
+
470nF
18
0.1
F
10
F
0.1
F
3-wire or 2-wire
MPU Interface
10k
3.3V
Notes:
1. AGND and DGND should be connected as close to the WM8739 as possible.
2. 0.1
F capacitors should be positioned as close the the WM8739 as possible.
3. Capacitor types should be carefully chosen. Capacitors with very low ESR
are recommended for optimum performance.
Figure 29 External Components Diagram
WM8739 / WM8739L
Production Data
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PD Rev 3.1 December 2002
34
PACKAGE DIMENSIONS (SSOP)
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM0015.B
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
2.0
A
1
0.05
-----
-----
A
2
1.65
1.75
1.85
b
0.22
0.30
0.38
c
0.09
-----
0.25
D
6.90
7.20
7.50
e
0.65 BSC
E
7.40
7.80
8.20
5.00
5.30
5.60
L
0.55
0.75
0.95
REF:
A A2
A1
SEATING PLANE
-C-
0.10 C
10
1
D
11
20
e
b
E1
E
-
JEDEC.95, MO 150
0
o
4
o
8
o
E
1
L
1
0.125 REF
c
L
GAUGE
PLANE
0.25
L
1
WM8739 / WM8739L
Production Data
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PD Rev 3.1 December 2002
35
PACKAGE DIMENSIONS (QFN)
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM
PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF
ETCHING OF LEADFRAME.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY
DM023.D
FL: 28 PIN QFN PLASTIC PACKAGE 5
X
5
X
0.9 mm BODY, 0.50 mm LEAD PITCH
C
aaa
INDEX AREA
(D/2 X E/2)
C
aaa
2 X
2 X
TOP VIEW
D
E
C
0.08
C
ccc
A
A1
C
(A3)
SEATING PLANE
1
14
13
b
15
L
D2/2
D2
E2
E2/2
SEE DETAIL B
B
C
ccc
M
A
B
B
A
A
27
28
1
2
7
8
21
22
e
5
CORNER
TIE BAR
DETAIL A
B
C
bbb
M
A
28x b
L
28x
K
L1
R
1
1
0.
566
mm
5
CORNER
TIE BAR
0.1
5
DETAIL B
T
E
RM
I
N
AL
TI
P
R
DATUM
e
e/
2
L1
1
SEE DETAIL A
Symbols
Dimensions (mm)
MIN
NOM
MAX
NOTE
A
A1
A3
b
D
D2
E
E2
e
L
L1
R
0.85
0.90
1.00
0.05
0.02
0
0.2 REF
0.30
0.23
0.18
5.00 BSC
3.4
3.3
3.2
5.00 BSC
0.5 BSC
3.3
3.4
3.2
0.35
0.4
0.45
0.1
b(min)/2
1
2
2
1
K
0.20
aaa
bbb
ccc
REF:
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VKKD-2
Tolerances of Form and Position
EXPOSED
CENTRE
PAD
WM8739 / WM8739L
Production Data
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PD Rev 3.1 December 2002
36
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of
liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any
license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of WM covering or relating to any combination, machine, or process in which such products or services might be or are
used. WM's publication of information regarding any third party's products or services does not constitute WM's approval,
license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product
or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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