Document Outline

WM8971L
Stereo CODEC for Portable Audio Applications
DESCRIPTION
FEATURES
APPLICATIONS
BLOCK DIAGRAM
TABLE OF CONTENTS
PIN CONFIGURATION
ORDERING INFORMATION
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATION CONDITIONS
ELECTRICAL CHARACTERISTICS
- OUTPUT PGAS LINEARITY
- HEADPHONE OUTPUT THD VERSUS POWER
- SPEAKER THD AND NOISE VERSUS POWER
POWER CONSUMPTION
SIGNAL TIMING REQUIREMENTS
- SYSTEM CLOCK TIMING
- AUDIO INTERFACE TIMING … MASTER MODE
- AUDIO INTERFACE TIMING … SLAVE MODE
INTERNAL POWER ON RESET CIRCUIT
DEVICE DESCRIPTION
- INTRODUCTION
- INPUT SIGNAL PATH
- AUTOMATIC LEVEL CONTROL (ALC)
- OUTPUT SIGNAL PATH
- ANALOGUE OUTPUTS
- ENABLING THE OUTPUTS
- HEADPHONE SWITCH
- THERMAL SHUTDOWN
- HEADPHONE OUTPUT
- DIGITAL AUDIO INTERFACE
- AUDIO INTERFACE CONTROL
- CLOCKING AND SAMPLE RATES
- CONTROL INTERFACE
- POWER SUPPLIES
- POWER MANAGEMENT
REGISTER MAP
DIGITAL FILTER CHARACTERISTICS
- TERMINOLOGY
- DAC FILTER RESPONSES
- ADC FILTER RESPONSES
- DE-EMPHASIS FILTER RESPONSES
- HIGHPASS FILTER
APPLICATIONS INFORMATION
- RECOMMENDED EXTERNAL COMPONENTS
- LINE INPUT CONFIGURATION
- MICROPHONE INPUT CONFIGURATION
- MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS
- POWER MANAGEMENT EXAMPLES
PACKAGE DIMENSIONS
IMPORTANT NOTICE
ADDRESS:

WM8971L

Stereo CODEC for Portable Audio Applications

WOLFSON MICROELECTRONICS plc

To receive regular email updates, sign up

http://www.wolfsonmicro.com/enews/

Production Data, August 2005, Rev 4.1

2005 Wolfson Microelectronics plc

DESCRIPTION

The WM8971L is a low power, high quality stereo codec
designed for portable digital audio applications.

The device integrates complete interfaces to stereo or mono
microphones and a stereo headphone. External component
requirements are drastically reduced as no separate
microphone or headphone amplifiers are required.
Advanced on-chip digital signal processing performs
graphic equaliser, and automatic level control for the
microphone or line input.

The WM8971L can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256f

rates like 12.288MHz and

24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.

The WM8971L operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.

The WM8971L is supplied in a very small and thin 5x5mm
QFN package, ideal for use in hand-held and portable
systems.

FEATURES

· DAC SNR 98dB (`A' weighted), THD 84dB at 48kHz, 3.3V

· ADC SNR 95dB (`A' weighted), THD -82dB at 48kHz, 3.3V

· Complete Stereo / Mono Microphone Interface

- Programmable ALC / Noise Gate

· On-chip 400mW BTL Speaker Driver (mono)

· On-chip

Headphone

Driver

>40mW output power on 16

/ 3.3V

THD 80dB at 20mW, SNR 90dB with 16

load

No DC blocking capacitors required (capless mode)

· Separately mixed mono output

· Digital Graphic Equaliser

· Low

Power

7mW stereo playback (1.8V / 1.5V supplies)

14mW record and playback (1.8V / 1.5V supplies)

· Low Supply Voltages

Analogue 1.8V to 3.6V

Digital core: 1.42V to 3.6V

Digital I/O: 1.8V to 3.6V

· 256fs / 384fs or USB master clock rates: 12MHz, 24MHz

· Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,

88.2, 96kHz generated internally from master clock

· 5x5x0.9mm QFN package

APPLICATIONS

· Digital

Still

Cameras

· MP3 Player / Recorders

· Minidisc Player / Recorders

· Portable Digital Music Systems

BLOCK DIAGRAM

WM8971L

Production Data

PD Rev 4.1 August 2005

TABLE OF CONTENTS

DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................4
ORDERING INFORMATION ..................................................................................4
PIN DESCRIPTION ................................................................................................5
ABSOLUTE MAXIMUM RATINGS .........................................................................6
RECOMMENDED OPERATION CONDITIONS .....................................................6
ELECTRICAL CHARACTERISTICS ......................................................................7

OUTPUT PGA'S LINEARITY ......................................................................................... 9

HEADPHONE OUTPUT THD VERSUS POWER......................................................... 10

SPEAKER THD AND NOISE VERSUS POWER ......................................................... 11

POWER CONSUMPTION ....................................................................................12
SIGNAL TIMING REQUIREMENTS .....................................................................13

SYSTEM CLOCK TIMING............................................................................................ 13

AUDIO INTERFACE TIMING MASTER MODE ......................................................... 13

AUDIO INTERFACE TIMING SLAVE MODE ............................................................ 14

INTERNAL POWER ON RESET CIRCUIT ..........................................................17
DEVICE DESCRIPTION .......................................................................................18

INTRODUCTION.......................................................................................................... 18

INPUT SIGNAL PATH.................................................................................................. 18

AUTOMATIC LEVEL CONTROL (ALC) ....................................................................... 25

OUTPUT SIGNAL PATH.............................................................................................. 28

ANALOGUE OUTPUTS ............................................................................................... 33

ENABLING THE OUTPUTS ......................................................................................... 35

HEADPHONE SWITCH ............................................................................................... 35

THERMAL SHUTDOWN .............................................................................................. 37

HEADPHONE OUTPUT ............................................................................................... 37

DIGITAL AUDIO INTERFACE...................................................................................... 38

AUDIO INTERFACE CONTROL .................................................................................. 42

CLOCKING AND SAMPLE RATES .............................................................................. 44

CONTROL INTERFACE .............................................................................................. 46

POWER SUPPLIES ..................................................................................................... 47

POWER MANAGEMENT ............................................................................................. 47

REGISTER MAP...................................................................................................50
DIGITAL FILTER CHARACTERISTICS ...............................................................51

TERMINOLOGY........................................................................................................... 51

DAC FILTER RESPONSES ......................................................................................... 52

ADC FILTER RESPONSES ......................................................................................... 53

DE-EMPHASIS FILTER RESPONSES ........................................................................ 54

HIGHPASS FILTER ..................................................................................................... 55

APPLICATIONS INFORMATION .........................................................................56

RECOMMENDED EXTERNAL COMPONENTS........................................................... 56

LINE INPUT CONFIGURATION................................................................................... 57

MICROPHONE INPUT CONFIGURATION .................................................................. 57

MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS ........................................ 57

POWER MANAGEMENT EXAMPLES ......................................................................... 58

Production Data

WM8971L

PD Rev 4.1 August 2005

PIN DESCRIPTION

PIN NO

NAME

TYPE

DESCRIPTION

1 MCLK

Digital Input

Master Clock

2 DCVDD

Supply Digital

Core

Supply

3 DBVDD

Supply

Digital Buffer (I/O) Supply

4 DGND

Supply

Digital Ground (return path for both DCVDD and DBVDD)

5 BCLK

Digital Input / Output

Audio Interface Bit Clock

6 DACDAT

Digital Input

DAC Digital Audio Data

7 DACLRC

Digital Input / Output

Audio Interface Left / Right Clock/Clock Out

8 ADCDAT

Digital Output

ADC Digital Audio Data

9 ADCLRC

Digital Input / Output

Audio Interface Left / Right Clock

10 MONOOUT

Analogue Output

Mono Output

11 NC

No Connect

12 ROUT1

Analogue Output

Right Output 1 (Line or Headphone)

13 LOUT1

Analogue Output

Left Output 1 (Line or Headphone)

14 HPGND

Supply

Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2)

15 ROUT2

Analogue Output

Right Output 1 (Line or Headphone or Speaker)

16 LOUT2

Analogue Output

Left Output 1 (Line or Headphone or Speaker)

17 HPVDD

Supply

Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2,
MONOUT)

18 AVDD

Supply Analogue

Supply

19 AGND

Supply

Analogue Ground (return path for AVDD)

20 VREF

Analogue Output

Reference Voltage Decoupling Capacitor

21 VMID

Analogue Output

Midrail Voltage Decoupling Capacitor

22 MICBIAS

Analogue Output

Microphone Bias

23 HPDETECT

Analogue Input

Headphone Plug-in Detection

24 NC

No Connect

25 MIC

Analogue Input

Single Ended Microphone Input

26 NC

No Connect

27 RINPUT1

Analogue Input

Right Channel Input 1

28 LINPUT1

Analogue Input

Left Channel Input 1

29 MODE

Digital Input

Control Interface Selection

30 CSB

Digital Input

Chip Select / Device Address Selection

31 SDIN

Digital Input/Output

Control Interface Data Input / 2-wire Acknowledge output

SCLK

Digital Input

Control Interface Clock Input

Note:

It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.

WM8971L

Production Data

PD Rev 4.1 August 2005

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30

°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30

°C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30

°C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION MIN

MAX

Supply voltages

-0.3V +3.63V

Voltage range digital inputs

DGND -0.3V

DBVDD +0.3V

Voltage range analogue inputs

AGND -0.3V

AVDD +0.3V

Operating temperature range, T

-25

°C +85°C

Storage temperature after soldering

-65

°C +150°C

Notes

Analogue and digital grounds must always be within 0.3V of each other.

All digital and analogue supplies are completely independent from each other.

DCVDD must be less than or equal to AVDD and DBVDD.

RECOMMENDED OPERATION CONDITIONS

PARAMETER SYMBOL

MIN

TYP

MAX

UNIT

Digital supply range (Core)

DCVDD 1.42

2.0

3.6

Digital supply range (Buffer)

DBVDD 1.7

2.0

3.6

Analogue supplies range

AVDD, HPVDD

1.8

2.0

3.6

Ground

DGND,AGND, HPGND

Production Data

WM8971L

PD Rev 4.1 August 2005

ELECTRICAL CHARACTERISTICS

Test Conditions

DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T

= +25

C, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio

data unless otherwise stated.

PARAMETER SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Analogue Inputs (LINPUT1, RINPUT1, MIC) to ADC

AVDD = 3.3V

1.0

Full Scale Input Signal Level

(for ADC 0dB Input at 0dB Gain)

INFS

AVDD = 1.8V

0.545

V rms

L/RINPUT1 to ADC,

PGA gain = 0dB

L/RINPUT1 to ADC,

PGA gain = +30dB

1.5

L/RINPUT1 DC

measurement

Input Resistance

L/RINPUT1 unused

Input Capacitance

AVDD = 3.3V

Signal to Noise Ratio

(A-weighted)

SNR

AVDD = 1.8V

Dynamic Range

-60dBFs

-1dBFs input,

AVDD = 3.3V

-82

0.008

Total Harmonic Distortion

THD

-1dBFs input,

AVDD = 1.8V

-74

0.02

ADC Channel Separation

1kHz signal

Channel Matching

1kHz

signal 0.2 dB

Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT)

0dB Full scale output voltage

AVDD/3.3

Vrms

1kHz, full scale signal

Mute attenuation

MONOOUT pin

Channel Separation

analogue in

to analogue out

85 dB

DAC to Line-Out (L/ROUT2 with 10k

/ 50pF load)

AVDD=3.3V 90

Signal to Noise Ratio

(A-weighted)

SNR

AVDD=1.8V

AVDD=3.3V

-84

Total Harmonic Distortion

THD

AVDD=1.8V

-80

Channel Separation

1kHz signal

100

Headphone Output (LOUT1/ROUT1, using capacitors)

Output Power per channel

Output power is very closely correlated with THD; see below.

HPVDD=1.8V, R

=32

=5mW

0.016

-76

HPVDD=1.8V, R

=16

=5mW

0.022

-73

HPVDD=3.3V, R

=32

=20mW

0.013

-78

Total Harmonic Distortion

THD

HPVDD=3.3V, R

=16

=20mW

0.018

-75

HPVDD = 3.3V

Signal to Noise Ratio

(A-weighted)

SNR

HPVDD = 1.8V

WM8971L

Production Data

PD Rev 4.1 August 2005

Test Conditions

DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T

= +25

C, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio

data unless otherwise stated.

PARAMETER SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Speaker Output (LOUT2/ROUT2 with 8

bridge tied load, ROUT2INV=1)

Output Power at 1% THD

THD = 1%

330

mW (rms)

Abs. Max Power Output

max

500

(rms)

Total Harmonic Distortion

THD Po=200mW,

HPVDD=3.3V

-63

0.07

Signal to Noise Ratio

(A-weighted)

SNR HPVDD=3.3V,

Analogue Reference Levels

Midrail Reference Voltage

VMID

AVDD/2

+3%

Buffered Reference Voltage

VREF

AVDD/2

+3%

Microphone Bias

Bias Voltage

MICBIAS

3mA load current

0.9

×AVDD +

Bias Current Source

MICBIAS

Output Noise Voltage

1K to 20kHz

nV/

Digital Input / Output

Input HIGH Level

0.7

×DBVDD

Input LOW Level

0.3

×DBVDD V

Output HIGH Level

= +1mA

0.9

×DBVDD

Output LOW Level

= -1mA

0.1

×DBVDD V

HPDETECT (pin 23)

Input HIGH Level

0.7

×AVDD

Input LOW Level

0.3

×AVDD V

WM8971L

Production Data

PD Rev 4.1 August 2005

POWER CONSUMPTION

The power consumption of the WM8971L depends on the following factors.
·

Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power
savings, especially in the digital sections of the WM8971L.

Operating mode: Significant power savings can be achieved by always disabling parts of the WM8971L that are not
used (e.g. mic pre-amps, unused outputs, DAC, ADC, etc.)

Control Register

R23

Other settings

Tot. Power

Bit

VMI

SEL

AIN

DCL

DCR

LOUT

DCO

VSEL

I (mA)

OFF

00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11

Clocks stopped

3.3 0.0016 3.3 0.0190 3.3 0.0080 3.3 0.0002

0.0950

2.5 0.0008 2.5 0.0170 2.5 0.0050 2.5 0.0000

0.0570

1.8 0.0005 1.5 0.0120 1.5 0.0029 1.8 0.0000

0.0233

Standby

10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11

Interface Stopped

3.3 0.3900 3.3 0.0390 3.3 0.0080 3.3 0.0000

1.4421

(500 KOhm VMID string)

2.5 0.2880 2.5 0.0170 2.5 0.0050 2.5 0.0000

0.7750

1.8 0.1970 1.5 0.0120 1.5 0.0030 1.8 0.0000

0.3771

Playback to Line-out

01 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 11

3.3 3.7310 3.3 5.6600 3.3 0.3000 3.3 0.2370

32.7624

2.5 2.6940 2.5 3.8600 2.5 0.2200 2.5 0.2100

17.4600

1.8 1.8820 1.5 2.1400 1.5 0.1240 1.8 0.1500

7.0536

Playback to Line-out

01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 11

3.3 3.5170 3.3 4.6470 3.3 0.3000 3.3 0.9500

31.0662

(64x oversampling mode)

2.5 2.5760 2.5 3.2030 2.5 0.2200 2.5 0.6480

16.6175

1.8 1.7760 1.5 1.7590 1.5 0.1240 1.8 0.4130

6.7647

Playback to 16 Ohm Headphone 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 11

3.3 3.7260 3.3 5.6700 3.3 0.3000 3.3 0.9530

35.1417

2.5 2.7530 2.5 3.9250 2.5 0.2200 2.5 0.6570

18.8875

1.8 1.8900 1.5 2.1410 1.5 0.1240 1.8 0.4150

7.5465

Playback to 8 Ohm BTL Speaker 01 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 11

R24, ROUT2INV=1

3.3 3.8820 3.3 5.6470 3.3 0.3000 3.3 0.2830

33.3696

2.5 2.8780 2.5 3.9390 2.5 0.2200 2.5 0.2100

18.1175

1.8 1.9800 1.5 2.1630 1.5 0.1240 1.8 0.1510

7.2663

Headphone Amp

01 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 11

Clocks Stopped

3.3 1.8400 3.3 0.0200 3.3 0.0080 3.3 0.9540

9.3126

(line-in to 16 Ohm headphone)

2.5 1.3300 2.5 0.0190 2.5 0.0050 2.5 0.6400

4.9850

1.8 0.9300 1.5 0.0130 1.5 0.0030 1.8 0.4100

2.4360

Speaker Amp

01 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 11

Clocks Stopped

3.3 1.9780 3.3 0.0200 3.3 0.0080 3.3 0.3310

7.7121

(line-in to 8 Ohm speaker)

R24, ROUT2INV=1

2.5 1.4300 2.5 0.0190 2.5 0.0050 2.5 0.2430

4.2425

1.8 0.9860 1.5 0.0130 1.5 0.0030 1.8 0.1760

2.1156

Phone Call

01 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 11

Clocks Stopped

3.3 2.5230 3.3 0.0370 3.3 0.0080 3.3 0.4420

9.9330

(mono line-in to headphone,

2.5 1.8520 2.5 0.0190 2.5 0.0050 2.5 0.3200

5.4900

mic to MONOOUT)

1.8 1.2900 1.5 0.0130 1.5 0.0030 1.8 0.2240

2.7492

Record from Line-in

01 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 11

3.3 8.6600 3.3 6.5700 3.3 0.3330 3.3 0.0000

51.3579

2.5 7.7100 2.5 4.2800 2.5 0.2320 2.5 0.0000

30.5550

1.8 6.8000 1.5 2.2100 1.5 0.1350 1.8 0.0000

15.7575

Record from Line-in

01 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 11

3.3 5.0720 3.3 5.9100 3.3 0.3390 3.3 0.0000

37.3593

(64x oversampling mode)

2.5 4.2550 2.5 3.7500 2.5 0.2320 2.5 0.0000

20.5925

1.8 3.5900 1.5 1.9100 1.5 0.1350 1.8 0.0000

9.5295

Record from mono microphone

01 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 11

3.3 4.9330 3.3 6.5400 3.3 0.3390 3.3 0.0000

38.9796

R23, DATSEL=01

2.5 4.2970 2.5 4.2500 2.5 0.2400 2.5 0.0000

21.9675

1.8 3.7210 1.5 2.2200 1.5 0.1370 1.8 0.0000

10.2333

Stereo Record & Playback

01 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 11

3.3 11.927 3.3 10.870 3.3 0.3320 3.3 0.2820

77.2563

2.5 10.112 2.5 7.3600 2.5 0.2340 2.5 0.2060

44.7800

1.8 7.3910 1.5 4.0610 1.5 0.1320 1.8 0.1480

19.8597

Stereo Record & Playback

01 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 11

3.3 8.1090 3.3 9.3300 3.3 0.3330 3.3 0.2820

59.5782

(64x oversampling mode)

2.5 6.5500 2.5 6.3020 2.5 0.2340 2.5 0.2070

33.2325

1.8 4.7000 1.5 3.3800 1.5 0.1320 1.8 0.1490

13.9962

DBVDD

HPVDD

R24

R25 (19h)

R26 (1Ah)

AVDD

DCVDD

Table 1 Supply Current Consumption

Notes:

All figures are at T

= +25

C, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), with zero signal (quiescent)

The power dissipated in the headphone or speaker is not included in the above table.

Production Data

WM8971L

PD Rev 4.1 August 2005

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 System Clock Timing Requirements

Test Conditions

CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T

= +25

C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

MCLKL

MCLK System clock pulse width low

MCLKH

MCLK System clock cycle time

MCLKY

MCLK duty cycle

MCLKDS

60:40

40:60

Test Conditions

CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T

= +25

C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

MCLKL

MCLK System clock pulse width low

MCLKH

MCLK System clock cycle time

MCLKY

AUDIO INTERFACE TIMING MASTER MODE

BCLK

(Output)

ADCDAT

ADCLRC/

DACLRC

(Outputs)

DACDAT

DDA

DHT

DST

Figure 2 Digital Audio Data Timing Master Mode (see Control Interface)

WM8971L

Production Data

PD Rev 4.1 August 2005

Figure 3 Bit Clock Mode

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T

= +25

C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER SYMBOL

MIN

TYP

MAX

UNIT

Bit Clock Timing Information

BCLK rise time (10pF load)

BCLKR

BCLK fall time (10pF load)

BCLKF

BCLK duty cycle (normal mode, BCLK = MCLK/n)

BCLKDS

50:50

BCLK duty cycle (USB mode, BCLK = MCLK)

BCLKDS

MCLKDS

Audio Data Input Timing Information

ADCLRC/DACLRC propagation delay from BCLK falling edge

ADCDAT propagation delay from BCLK falling edge

DDA

DACDAT setup time to BCLK rising edge

DST

DACDAT hold time from BCLK rising edge

DHT

AUDIO INTERFACE TIMING SLAVE MODE

BCLK

DACLRC/

ADCLRC

BCH

BCL

BCY

DACDAT

ADCDAT

LRSU

LRH

Figure 4 Digital Audio Data Timing Slave Mode

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T

= +25

C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

BCY

BCLK pulse width high

BCH

BCLK pulse width low

BCL

ADCLRC/DACLRC set-up time to BCLK rising edge

LRSU

ADCLRC/DACLRC hold time from BCLK rising edge

LRH

DACDAT hold time from BCLK rising edge

ADCDAT propagation delay from BCLK falling edge

Note:

BCLK period should always be greater than or equal to MCLK period.

Production Data

WM8971L

PD Rev 4.1 August 2005

INTERNAL POWER ON RESET CIRCUIT

VDD

GND

AVDD

DCVDD

DGND

Internal PORB

Power on Reset

Circuit

Figure 7 Internal Power on Reset Circuit Schematic

The WM8971 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to
reset the digital logic into a default state after power up. The power on reset circuit is powered from
DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a
minimum threshold.

Figure 8 Typical Power-Up Sequence

Figure 8 shows a typical power-up sequence. When DCVDD and AVDD go above the minimum
thresholds, Vpord_dcvdd and Vpord_avdd, there is enough voltage for the circuit to guarantee the
Power on Reset is asserted low and the chip is held in reset. In this condition, all writes to the control
interface are ignored. When DCVDD rises to Vpor_dcvdd_on and AVDD rises to Vpor_avdd_on,
PORB is released high and all registers are in their default state and writes to the control interface
may take place. If DCVDD and AVDD rise at different rates then PORB will only be released when
DCVDD and AVDD have both exceeded the Vpor_dcvdd_on and Vpor_avdd_on thresholds.

On power down, PORB is asserted low whenever DCVDD drops below the minimum threshold
Vpor_dcvdd_off or AVDD drops below the minimum threshold Vpor_avdd_off.

SYMBOL MIN TYP MAX UNIT

pord_dcvdd

0.4 0.6 0.8 V

por_dcvdd_on

0.9 1.26 1.6 V

por_avdd_on

0.5 0.7 0.9 V

por_avdd_off

0.4

0.6

0.8

Table 2 Typical POR Operation (typical values, not tested)

WM8971L

Production Data

PD Rev 4.1 August 2005

DEVICE DESCRIPTION

INTRODUCTION

The WM8971L is a low power audio codec offering a combination of high quality audio, advanced
features, low power and small size. These characteristics make it ideal for portable digital audio
applications such as Digital Still Cameras, MP3 and minidisk player / recorders. Stereo 24-bit multi-
bit delta sigma ADCs and DACs are used with oversampling digital interpolation and decimation
filters.

The device includes a stereo analogue input which can be switched internally. This input can be used
as either a line level input, as a microphone input or be selected as a mono differential input. A mono
input is also included which can be configured as a microphone or line input.

When recording a programmable gain amplifier with automatic level control (ALC) keeps the
recording volume constant. The on-chip stereo ADC and DAC are of a high quality using a multi-bit,
low-order oversampling architecture to deliver optimum performance with low power consumption.

The DAC output signal first enters an analogue mixer where an analogue input and/or the post-ALC
signal can be added to it. This mix is available on line and headphone outputs.

The WM8971L has a configurable digital audio interface where ADC data can be read and digital
audio playback data fed to the DAC. It supports a number of audio data formats including I

S, DSP

Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left
justified and MSB-First, right justified, and can operate in master or slave modes.

The WM8971L uses a unique clocking scheme that can generate many commonly used audio
sample rates from either a 12.00MHz USB clock or an industry standard 256/384 f

clock. This

feature eliminates the common requirement for an external phase-locked loop (PLL) in applications
where the master clock is not an integer multiple of the sample rate. Sample rates of 8kHz,
11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz can be
generated. The digital filters used for recording and playback are optimised for each sampling rate
used.

To allow full software control over all its features, the WM8971L offers a choice of 2 or 3 wire MPU
control interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs.

The design of the WM8971L has given much attention to power consumption without compromising
performance. It operates at very low voltages, and includes the ability to power off parts of the
circuitry under software control, including standby and power off modes.

INPUT SIGNAL PATH

The input signal path for each channel consists of a switch to select between three analogue inputs,
followed by a PGA (programmable gain amplifier) and an optional microphone gain boost. A
differential input of (LINPUT1 RINPUT1) may also be selected. The gain of the PGA can be
controlled either by the user or by the on-chip ALC function (see Automatic Level Control).

The signal then enters an ADC where it is digitised. Alternatively, the two channels can also be
mixed in the analogue domain and digitised in one ADC while the other ADC is switched off. The
mono-mix signal appears on both digital output channels.

SIGNAL INPUTS

The WM8971L has three high impedance, low capacitance AC coupled analogue inputs, LINPUT1,
RINPUT1, and MIC. The LINSEL and RINSEL control bits select between them. These inputs can be
configured as microphone or line inputs by enabling or disabling the microphone gain boost. A
differential input, LINPUT1-RINPUT1 may also be selected using L/RINSEL.

The signal inputs are biased internally to the reference voltage VREF. Whenever the line inputs are
muted or the device placed into standby mode, the inputs are kept biased to VREF using special
anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when changing
inputs.

Production Data

WM8971L

PD Rev 4.1 August 2005

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

7:6

LINSEL

Left Channel Input Select

00 = LINPUT1

11 = Differential

R32 (20h)

ADC Signal
Path Control
(Left)

5:4

LMICBOOST

Left Channel Microphone Gain Boost

00 = Boost off (bypassed)

01 = 13dB boost

10 = 20dB boost

11 = 29dB boost

7:6

RINSEL

Right Channel Input Select

00 = RINPUT1

01 = MIC

11 = Differential

R33 (21h)

ADC Signal
Path Control
(Right)

5:4

RMICBOOST

Right Channel Microphone Gain Boost

00 = Boost off (bypassed)

01 = 13dB boost

10 = 20dB boost

11 = 29dB boost

Table 3 Input Software Control

MONO MIXING

The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono,
either in the analogue domain (i.e. before the ADC) or in the digital domain (after the ADC).
MONOMIX selects the mode of operation. The user also has the flexibility to select the data output
from the audio interface using DATSEL. The default is for left and right channel ADC data to be
output, but the interface may also be configured so that e.g. left channel ADC data is output as both
left and right data for when an analogue mono mix is selected.

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

R31 (1Fh)

ADC input
Mode

7:6

MONOMIX

[1:0]

00 00:

Stereo

01: Analogue Mono Mix (using left ADC)

10: Analogue Mono Mix (using right ADC)

11: Digital Mono Mix

Table 4 Mono Mixing

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

R23 (17h)

Additional
Control (1)

3:2

DATSEL

[1:0]

00: left data=left ADC; right data =right ADC

01: left data =left ADC; right data = left ADC

10: left data = right ADC; right data =right ADC

11: left data = right ADC; right data = left ADC

Table 5 ADC Data Output Configuration

WM8971L

Production Data

PD Rev 4.1 August 2005

The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The output can be enabled or disables
using the MICB control bit (see also the "Power Management" section).

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Power
Management (1)

MICB

Microphone Bias Enable

0 = OFF (high impedance output)

1 = ON

Table 6 Microphone Bias Control

The internal MICBIAS circuitry is shown below. Note that the is a maximum source current capability
for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the
MICBIAS current to 3mA.

AGND

MICBIAS
= 1.8 x VMID
= 0.9 X AVDD

VMID

internal
resistor

MICB

Figure 9 Microphone Bias Schematic

PGA CONTROL

The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically
adjustable from +30dB to 17.25dB in 0.75dB steps. Each PGA can be controlled either by the user
or by the ALC function (see Automatic Level Control). When ALC is enabled for one or both
channels, then writing to the corresponding PGA control register has no effect.

The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the
LIVU or RIVU bits whilst programming the PGA gain, both channels are simultaneously updated.
This reduces the required number of software writes required. Setting the LZCEN and RZCEN bits
enables a zero-cross detector which ensures that PGA gain changes only occur when the signal is at
zero, eliminating any zipper noise. If zero cross is enabled a timeout is also available to update the
gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R23
(17h).

Production Data

WM8971L

PD Rev 4.1 August 2005

The inputs can also be muted in the analogue domain under software control. The software control
registers are shown in Table 7. If zero crossing is enabled, it is necessary to enable zero cross
timeout to un-mute the input PGAs. This is because their outputs will not cross zero when muted.
Alternatively, zero cross can be disabled before sending the un-mute command.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

LIVU

Left Volume Update

0 = Store LINVOL in intermediate
latch (no gain change)

1 = Update left and right channel
gains (left = LINVOL, right =
intermediate latch)

LINMUTE

Left Channel Input Analogue Mute

1 = Enable Mute

0 = Disable Mute

Note: LIVU must be set to un-mute.

LZCEN

Left Channel Zero Cross Detector

1 = Change gain on zero cross only

0 = Change gain immediately

R0 (00h)

Left Channel

PGA

5:0

LINVOL

[5:0]

010111

( 0dB )

Left Channel Input Volume Control

111111 = +30dB

111110 = +29.25dB

. . 0.75dB steps down to

000000 = -17.25dB

8 RIVU

Right

Volume

Update

0 = Store RINVOL in intermediate
latch (no gain change)

1 = Update left and right channel
gains (right = RINVOL, left =
intermediate latch)

RINMUTE

Right Channel Input Analogue Mute

1 = Enable Mute

0 = Disable Mute

Note: RIVU must be set to un-mute.

RZCEN

Right Channel Zero Cross Detector

1 = Change gain on zero cross only

0 = Change gain immediately

R1 (01h)

Right Channel

PGA

5:0 RINVOL

[5:0]

010111

( 0dB )

Right Channel Input Volume Control

111111 = +30dB

111110 = +29.25dB

. . 0.75dB steps down to

000000 = -17.25dB

R23 (17h)

Additional
Control (1)

0 TOEN

Timeout

Enable

0 : Timeout Disabled

1 : Timeout Enabled

Table 7 Input PGA Software Control

WM8971L

Production Data

PD Rev 4.1 August 2005

ANALOGUE TO DIGITAL CONVERTER (ADC)

The WM8971L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit
feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The
ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is
1.0 Volts r.m.s. Any voltage greater than full scale may overload the ADC and cause distortion.

ADC DIGITAL FILTER

The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path is illustrated in Figure 10.

FROM ADC

DIGITAL
HPF

DIGITAL
FILTER

TO DIGITAL

AUDIO

INTERFACE

DIGITAL

DECIMATOR

ADCHPD

Figure 10 ADC Digital Filter

The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass
filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is
enabled the dc offset is continuously calculated and subtracted from the input signal. By setting
HPOR, the last calculated dc offset value is stored when the high-pass filter is disabled and will
continue to be subtracted from the input signal. If the DC offset is changed, the stored and
subtracted value will not change unless the high-pass filter is enabled. This feature can be used for
calibration purposes. In addition the high-pass filter may be enabled separately on the left and right
channels (see Table 9).

The output data format can be programmed by the user to accommodate stereo or monophonic
recording on both inputs. The polarity of the output signal can also be changed under software
control. The software control is shown in Table 8.

Production Data

WM8971L

PD Rev 4.1 August 2005

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

6:5 ADCPOL

[1:0]

00 = Polarity not inverted

01 = L polarity invert

10 = R polarity invert

11 = L and R polarity invert

HPOR

Store dc offset when high-pass
Filter disabled

1 = store offset

0 = clear offset

ADC high-pass filter enable
(Digital)

HPFLREN = 0

1 = Disable High-pass filter on left
and right channels

0 = Enable High-pass filter on left
and right channels

R5 (05h)

ADC and DAC
Control

0 ADCHPD 0

HPFLREN = 1

0 = High-pass enabled on left,
disabled on right

1 = High-pass enabled on right,
disabled on left

R27 (1Bh)

HPFLREN

ADC high-pass filter left or right
enable

0 = High-pass filter enable/disable
on left and right channels
controlled by ADCHPD

1 = High-pass filter enabled on left
or right channel, as selected by
ADCHPD

Table 8 ADC Signal Path Control

HPFLREN ADCHPD

HIGH

PASS

MODE

0 0

High-pass filter enabled on left and right
channels

0 1

High-pass filter disabled on left and right
channels

1 0

High-pass filter enabled on left channel,
disabled on right channel

1 1

High-pass filter disabled on left channel,
enabled on right channel

Table 9 ADC High Pass Filter Enable Modes

WM8971L

Production Data

PD Rev 4.1 August 2005

DIGITAL ADC VOLUME CONTROL

The output of the ADCs can be digitally amplified or attenuated over a range from 97dB to +30dB in
0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit
code X is given by:

0.5

× (X-195) dB for 1 X 255;

MUTE for X = 0

The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or
RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control
register, but will not actually change the digital gain setting. Both left and right gain settings are
updated when either LAVU or RAVU are set to 1. This makes it possible to update the gain of both
channels simultaneously.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

7:0 LADCVOL

[7:0]

11000011

( 0dB )

Left ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -97dB

0000 0010 = -96.5dB

... 0.5dB steps up to

1111 1111 = +30dB

R21 (15h)

Left ADC
Digital Volume

LAVU

Left ADC Volume Update

0 = Store LADCVOL in intermediate
latch (no gain change)

1 = Update left and right channel
gains (left = LADCVOL, right =
intermediate latch)

7:0 RADCVOL

[7:0]

11000011

( 0dB )

Right ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -97dB

0000 0010 = -96.5dB

... 0.5dB steps up to

1111 1111 = +30dB

R22 (16h)

Right ADC
Digital Volume

RAVU

Right ADC Volume Update

0 = Store RADCVOL in intermediate
latch (no gain change)

1 = Update left and right channel
gains (left = intermediate latch, right
= RADCVOL)

Table 10 ADC Digital Volume Control

Production Data

WM8971L

PD Rev 4.1 August 2005

AUTOMATIC LEVEL CONTROL (ALC)

The WM8971L has an automatic level control that aims to keep a constant recording volume
irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that
the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output
and changes the PGA gain if necessary. Note that when the ALC function is enabled, the settings of
registers 0 and 1 (LINVOL, LIVU, LIZC, LINMUTE, RINVOL, RIVU, RIZC and RINMUTE) are
ignored.

hold
time

decay

time

attack

time

input

signal

after
ALC

PGA

gain

ALC

target

level

Figure 11 ALC Operation

The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume
can be programmed between 6dB and 28.5dB (relative to ADC full scale) using the ALCL register
bits. An upper limit for the PGA gain can be imposed by setting the MAXGAIN control bits.

HLD, DCY and ATK control the hold, decay and attack times, respectively:

Hold time is the time delay between the peak level detected being below target and the PGA gain
beginning to ramp up. It can be programmed in power-of-two (2

) steps, e.g. 2.67ms, 5.33ms,

10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time only
applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is
above target.

Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its
range (e.g. from 15B up to 27.75dB). The time it takes for the recording level to return to its target
value therefore depends on both the decay time and on the gain adjustment required. If the gain
adjustment is small, it will be shorter than the decay time. The decay time can be programmed in
power-of-two (2

) steps, from 24ms, 48ms, 96ms, etc. to 24.58s.

Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90%
of its range (e.g. from 27.75dB down to -15B gain). The time it takes for the recording level to return
to its target value therefore depends on both the attack time and on the gain adjustment required. If
the gain adjustment is small, it will be shorter than the attack time. The attack time can be
programmed in power-of-two (2

) steps, from 6ms, 12ms, 24ms, etc. to 6.14s.

When operating in stereo, the peak detector takes the maximum of left and right channel peak
values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is
preserved. However, the ALC function can also be enabled on one channel only. In this case, only
one PGA is controlled by the ALC mechanism, while the other channel runs independently with its
PGA gain set through the control register.

When one ADC channel is unused, the peak detector disregards that channel. The ALC function can
also operate when the two ADC outputs are mixed to mono in the digital domain, but not if they are
mixed to mono in the analogue domain, before entering the ADCs.

WM8971L

Production Data

PD Rev 4.1 August 2005

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

8:7 ALCSEL

[1:0]

(OFF)

ALC function select

00 = ALC off (PGA gain set by register)

01 = Right channel only

10 = Left channel only

11 = Stereo (PGA registers unused)

Note: ensure that LINVOL and
RINVOL settings (reg. 0 and 1) are
the same before entering this mode.

6:4 MAXGAIN

[2:0]

111
(+30dB)

Set Maximum Gain of PGA

111 : +30dB

110 : +24dB

....(-6dB steps)

001 : -6dB

000 : -12dB

R17 (11h)

ALC Control 1

3:0 ALCL

[3:0]

1011

(-12dB)

ALC target sets signal level at ADC
input

0000 = -28.5dB FS

0001 = -27.0dB FS

... (1.5dB steps)

1110 = -7.5dB FS

1111 = -6dB FS

7 ALCZC

(zero

cross
off)

ALC uses zero cross detection circuit.

R18 (12h)

ALC Control 2

3:0 HLD

[3:0]

0000

(0ms)

ALC hold time before gain is increased.

0000 = 0ms

0001 = 2.67ms

0010 = 5.33ms

... (time doubles with every step)

1111 = 43.691s

7:4 DCY

[3:0]

0011

(192ms)

ALC decay (gain ramp-up) time

0000 = 24ms

0001 = 48ms

0010 = 96ms

... (time doubles with every step)

1010 or higher = 24.58s

R19 (13h)

ALC Control 3

3:0 ATK

[3:0]

0010

(24ms)

ALC attack (gain ramp-down) time

0000 = 6ms

0001 = 12ms

0010 = 24ms

... (time doubles with every step)

1010 or higher = 6.14s

Table 11 ALC Control

PEAK LIMITER

To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.

Note:

If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to
prevent clipping when long attack times are used.

Production Data

WM8971L

PD Rev 4.1 August 2005

NOISE GATE

When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise
pumping", i.e. loud hissing noise during silence periods. The WM8971L has a noise gate function
that prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3
pins against a noise gate threshold, NGTH. The noise gate cuts in when:

Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB]

This is equivalent to:

Signal level at input pin [dB] < NGTH [dB]

The ADC output can then either be muted or digitally attenuated by 18dB. Alternatively, the PGA gain
can be held constant (preventing it from ramping up as it normally would when the signal is quiet).

The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
setup of the function. Note that the noise gate only works in conjunction with the ALC function, and
always operates on the same channel(s) as the ALC (left, right, both, or none).

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

7:3

NGTH

[4:0]

00000

Noise gate threshold

00000 -76.5dBfs

00001 -75dBfs

... 1.5 dB steps

11110 -31.5dBfs

11111 -30dBfs

2:1

NGG

[1:0]

Noise gate type

X0 = PGA gain held constant

01 = mute ADC output

10 = reserved (do not use this setting)

11 = reserved (do not use this setting)

R20 (14h)

Noise Gate

Control

NGAT

Noise gate function enable

1 = enable

0 = disable

Table 12 Noise Gate Control

Note:
The performance of the ADC may degrade at high input signal levels if the monitor bypass mux is
selected with MIC boost and ALC enabled.

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

ADCDIV2

ADC 6dB attenuate enable

0 = disabled (0dB)

1 = -6dB enabled

R5 (05h)

ADC and DAC
control

DACDIV2

DAC 6dB attenuate enable

0 = disabled (0dB)

1 = -6dB enabled

Table 13 ADC and DAC 6dB Attenuation Select

WM8971L

Production Data

PD Rev 4.1 August 2005

OUTPUT SIGNAL PATH

The WM8971L output signal paths consist of digital filters, DACs, analogue mixers and output
drivers. The digital filters and DACs are enabled when the WM8971L is in `playback only' or `record
and playback' mode. The mixers and output drivers can be separately enabled by individual control
bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification
provided by the WM8971L, irrespective of whether the DACs are running or not.

The WM8971L receives digital input data on the DACDAT pin. The digital filter block processes the
data to provide the following functions:

Digital volume control

Graphic equaliser and Dynamic Bass Boost

· Sigma-Delta

Modulation

Two high performance sigma-delta audio DACs convert the digital data into two analogue signals (left
and right). These can then be mixed with analogue signals from the LINPUT1/2/3 and RINPUT1/2/3
pins, and the mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2 and MONOOUT.

LOUT1/ROUT1: can drive a 16

or 32 stereo headphone or stereo line output.

LOUT2/ROUT2: can drive a 16

or 32 stereo headphone or stereo line output, or an

mono speaker.

MONOOUT: can drive a mono line output or other load down to 10k

DIGITAL DAC VOLUME CONTROL

The signal volume from each DAC can be controlled digitally, in the same way as the ADC volume
(see Digital ADC Volume Control). The gain and attenuation range is 127dB to 0dB in 0.5dB steps.
The level of attenuation for an eight-bit code X is given by:

0.5

× (X-255) dB for 1 X 255;

MUTE for X = 0

The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or
RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register,
but the actual gain does not change. Both left and right gain settings are updated simultaneously
when either LDVU or RDVU are set to 1.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

LDVU

Left DAC Volume Update

0 = Store LDACVOL in intermediate
latch (no gain change)

1 = Update left and right channel
gains (left = LDACVOL, right =
intermediate latch)

R10 (0Ah)

Left Channel
Digital Volume

7:0 LDACVOL

[7:0]

11111111

( 0dB )

Left DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

RDVU

Right DAC Volume Update

0 = Store RDACVOL in intermediate
latch (no gain change)

1 = Update left and right channel
gains (left = intermediate latch, right
= RDACVOL)

R11 (0Bh)

Right Channel
Digital Volume

7:0 RDACVOL

[7:0]

11111111

( 0dB )

Right DAC Digital Volume Control

similar to LDACVOL

Table 14 Digital Volume Control

Production Data

WM8971L

PD Rev 4.1 August 2005

GRAPHIC EQUALISER

The WM8971L has a digital graphic equaliser and adaptive bass boost function. This function
operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take
two different forms:

Linear bass control: bass signals are amplified or attenuated by a user programmable
gain. This is independent of signal volume, and very high bass gains on loud signals
may lead to signal clipping.

Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass
volume is low, it is boosted more than when the bass volume is high. This method is
recommended because it prevents clipping, and usually sounds more pleasant to the
human ear.

Treble control applies a user programmable gain, without any adaptive boost function. Bass and
treble control are completely independent with separately programmable gains and filter
characteristics.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

7 BB

Bass

Boost

0 = Linear bass control

1 = Adaptive bass boost

Bass Filter Characteristic

0 = Low Cutoff (130Hz at 48kHz sampling)

1 = High Cutoff (200Hz at 48kHz sampling)

Bass Intensity

Code BB=0 BB=1

0000 +9dB 15

(max)

0001 +9dB 14

0010 +7.5dB

0011 +6dB 12

0100 +4.5dB

0101 +3dB 10

0110 +1.5dB

0111 0dB 8

1000 -1.5dB

1001 -3dB 6

1010 -4.5dB

1011 -6dB 4

1100 -6dB 3

1101 -6dB 2

1110 -6dB 1

R12 (0Ch)

Bass Control

3:0 BASS

[3:0]

1111
(Disabled)

1111 Bypass

(OFF)

6 TC

Treble

Filter

Characteristic

0 = High Cutoff (8kHz at 48kHz sampling)

1 = Low Cutoff (4kHz at 48kHz sampling)

R13 (0Dh)

Treble Control

3:0 TRBL

[3:0]

1111
(Disabled)

Treble Intensity

0000 or 0001 = +9dB

0010 = +7.5dB

... (1.5dB steps)

1011 to 1110 = -6dB

1111 = Disable

Table 15 Graphic Equaliser

WM8971L

Production Data

PD Rev 4.1 August 2005

DIGITAL TO ANALOGUE CONVERTER (DAC)

After passing through the graphic equaliser filters, digital `de-emphasis' can be applied to the audio
data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording).
De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz.

The WM8971L also has a Soft Mute function, which gradually attenuates the volume of the digital
signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is
enabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit
to zero.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

2:1

DEEMP

[1:0]

00 De-emphasis

Control

11 = 48kHz sample rate

10 = 44.1kHz sample rate

01 = 32kHz sample rate

00 = No De-emphasis

R5 (05h)

ADC and DAC
Control

DACMU

Digital Soft Mute

1 = mute

0 = no mute (signal active)

Table 16 DAC Control

The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to
high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and
sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and
low distortion.

In normal operation, the left and right channel digital audio data is converted to analogue in two
separate DACs. However, it is also possible to disable one channel, so that the same signal (left or
right) appears on both analogue output channels. Additionally, there is a mono-mix mode where the
two audio channels are mixed together digitally and then converted to analogue using only one DAC,
while the other DAC is switched off. The mono-mix signal can be selected to appear on both
analogue output channels.

The DAC output defaults to non-inverted. Setting DACINV will invert the DAC output phase on both
left and right channels.

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

5:4

DMONOMIX

[1:0]

DAC mono mix

00: stereo

01: mono ((L+R)/2) into DACL, `0' into
DACR

10: mono ((L+R)/2) into DACR, `0' into
DACL

11: mono ((L+R)/2) into DACL and
DACR

R23 (17h)

Additional
Control (1)

DACINV 0

DAC

phase

invert

0 : non-inverted

1 : inverted

Table 17 DAC Mono Mix and Phase Invert Select

Production Data

WM8971L

PD Rev 4.1 August 2005

OUTPUT MIXERS

The WM8971L provides the option to mix the DAC output signal with analogue line-in signals from
the LINPUT1, RINPUT1, MIC pins or a mono differential input (LINPUT1 RINPUT1). The level of
the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers).

The mono mixer is designed to allow a number of signal combinations to be mixed, including the
possibility of mixing both the right and left channels together to produce a mono output. To prevent
overloading of the mixer when full-scale DAC left and right signals are input, the mixer inputs from
the DAC outputs each have a fixed gain of -6dB. The bypass path inputs to the mono mixer have
variable gain as determined by R38/R39 bits [6:4].

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

R34 (22h)

Left Mixer (1)

2:0

LMIXSEL

000

Left Input Selection for Output Mix

000 = LINPUT1

011 = Left ADC Input (after PGA /
MICBOOST)

100 = Differential input

R36 (24h)

Right Mixer
(1)

2:0

RMIXSEL

000

Right Input Selection for Output Mix

000 = RINPUT1

001 = MIC

010 = Reserved (do not use)

011 = Right ADC Input (after PGA /
MICBOOST)

100 = Differential input

Table 18 Output Mixer Signal Selection

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

LD2LO

Left DAC to Left Mixer

0 = Disable (Mute)

1 = Enable Path

LI2LO

LMIXSEL Signal to Left Mixer

0 = Disable (Mute)

1 = Enable Path

R34 (22h)

Left Mixer
Control (1)

6:4 LI2LOVOL

[2:0]

101

(-9dB)

LMIXSEL Signal to Left Mixer Volume

000 = +6dB

... (3dB steps)

111 = -15dB

RD2LO

Right DAC to Left Mixer

0 = Disable (Mute)

1 = Enable Path

RI2LO

RMIXSEL Signal to Left Mixer

0 = Disable (Mute)

1 = Enable Path

R35 (23h)

Left Mixer
Control (2)

6:4 RI2LOVOL

[2:0]

101

(-9dB)

RMIXSEL Signal to Left Mixer Volume

000 = +6dB

... (3dB steps)

111 = -15dB

Table 19 Left Output Mixer Control

WM8971L

Production Data

PD Rev 4.1 August 2005

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

LD2RO

Left DAC to Right Mixer

0 = Disable (Mute)

1 = Enable Path

LI2RO

LMIXSEL Signal to Right Mixer

0 = Disable (Mute)

1 = Enable Path

R36 (24h)

Right Mixer
Control (1)

6:4 LI2ROVOL

[2:0]

101

(-9dB)

LMIXSEL Signal to Right Mixer Volume

000 = +6dB

... (3dB steps)

111 = -15dB

RD2RO

Right DAC to Right Mixer

0 = Disable (Mute)

1 = Enable Path

RI2RO

RMIXSEL Signal to Right Mixer

0 = Disable (Mute)

1 = Enable Path

R37 (25h)

Right Mixer
Control (2)

6:4 RI2ROVOL

[2:0]

101

(-9dB)

RMIXSEL Signal to Right Mixer Volume

000 = +6dB

... (3dB steps)

111 = -15dB

Table 20 Right Output Mixer Control

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

LD2MO

Left DAC to Mono Mixer

0 = Disable (Mute)

1 = Enable Path

LI2MO

LMIXSEL Signal to Mono Mixer

0 = Disable (Mute)

1 = Enable Path

R38 (26h)

Mono Mixer
Control (1)

6:4 LI2MOVOL

[2:0]

101

(-9dB)

LMIXSEL Signal to Mono Mixer
Volume

000 = +6dB

... (3dB steps)

111 = -15dB

RD2MO

Right DAC to Mono Mixer

0 = Disable (Mute)

1 = Enable Path

RI2MO

RMIXSEL Signal to Mono Mixer

0 = Disable (Mute)

1 = Enable Path

R39 (27h)

Mono Mixer
Control (2)

6:4 RI2MOVOL

[2:0]

101

(-9dB)

RMIXSEL Signal to Mono Mixer
Volume

000 = +6dB

... (3dB steps)

111 = -15dB

Table 21 Mono Output Mixer Control

Production Data

WM8971L

PD Rev 4.1 August 2005

ANALOGUE OUTPUTS

LOUT1/ROUT1 OUTPUTS

The LOUT1 and ROUT1 pins can drive a 16

or 32 headphone or a line output (see Headphone

Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be
independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL,
respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting
below 0101111 (minimum) mutes the output driver. The corresponding output pin remains at the
same DC level (the reference voltage on the VREF pin), so that no click noise is produced when
muting or un-muting.

A zero cross detect on the analogue output may also be enabled when changing the gain setting to
minimize audible clicks and zipper noise as the gain updates. If zero cross is enabled a timeout is
also available to update the gain if a zero cross does not occur. This function may be enabled by
setting TOEN in register R23 (17h).

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

8 LO1VU

Left

Volume

Update

0 = Store LOUT1VOL in intermediate
latch (no gain change)

1 = Update left and right channel gains
(left = LOUT1VOL, right =
intermediate latch)

LO1ZC

Left zero cross enable

1 = Change gain on zero cross only

0 = Change gain immediately

R2 (02h)

LOUT1

Volume

6:0 LOUT1VOL

[6:0]

1111001

(0dB)

LOUT1 Volume

1111111 = +6dB

... (80 steps)

0110000 = -67dB

0101111 to 0000000 = Analogue
MUTE

8 RO1VU

Right

Volume

Update

0 = Store ROUT1VOL in intermediate
latch (no gain change)

1 = Update left and right channel gains
(left = intermediate latch, right =
ROUT1VOL)

RO1ZC

Right zero cross enable

1 = Change gain on zero cross only

0 = Change gain immediately

R3 (03h)

ROUT1

Volume

6:0 ROUT1VOL

[6:0]

1111001 ROUT1

Volume

Similar to LOUT1VOL

Table 22 LOUT1/ROUT1 Volume Control

WM8971L

Production Data

PD Rev 4.1 August 2005

LOUT2/ROUT2 OUTPUTS

The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are
independently controlled and can also drive an 8

mono speaker (see Speaker Output section). For

speaker drive, the ROUT2 signal must be inverted (ROUT2INV = 1), so that the left and right channel
are mixed to mono in the speaker [L(-R) = L+R].

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

6:0 LOUT2VOL

[6:0]

1111001

(0dB)

Similar to LOUT1VOL

LO2ZC

Left zero cross enable

1 = Change gain on zero cross only

0 = Change gain immediately

R40 (28h)

LOUT2

Volume

8 LO2VU 0

Same

LO1VU

6:0 ROUT2VOL

[6:0]

1111001

(0dB)

Similar ROUT1VOL

RO2ZC

Right zero cross enable

1 = Change gain on zero cross only

0 = Change gain immediately

R41 (29h)

ROUT2

Volume

8 RO2VU 0

Same

RO1VU

R24 (18h)

Additional
Control (2)

4 ROUT2INV

ROUT2 Invert

0 = No Inversion (0

° phase shift)

1 = Signal inverted (180

° phase shift)

Table 23 LOUT2/ROUT2 Volume Control

MONO OUTPUT

The MONOOUT pin can drive a mono line output. The signal volume on MONOOUT can be adjusted
under software control by writing to MONOOUTVOL.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

6:0 MONOOUT

VOL [6:0]

1111001

(0dB)

MONOOUT Volume

1111111 = +6dB

... (80 steps)

0110000 = -67dB

0101111 to 0000000 = Analogue MUTE

R42 (2Ah)

MONOOUT

Volume

MOZC

MONOOUT zero cross enable

1 = Change gain on zero cross only

0 = Change gain immediately

Table 24 MONOOUT Volume Control

Production Data

WM8971L

PD Rev 4.1 August 2005

ENABLING THE OUTPUTS

Each analogue output of the WM8971L can be separately enabled or disabled. The analogue mixer
associated with each output is powered on or off along with the output pin. All outputs are disabled by
default. To save power, unused outputs should remain disabled.

Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop
noise (see "Power Management" and "Applications Information" sections)

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

6 LOUT1 0

LOUT1

Enable

5 ROUT1 0

ROUT1

Enable

4 LOUT2 0

LOUT2

Enable

3 ROUT2 0

ROUT2

Enable

R26 (1Ah)

Power
Management
(2)

2 MONO

MONOOUT

Enable

Note: All "Enable" bits are 1 = ON, 0 = OFF

Table 25 Analogue Output Control

Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor.
This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and
each output can be controlled using the VROI bit in register 27. The default is low (1.5k

), so that

any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for
disabled outputs, VROI can then be set to 1, increasing the resistance to about 40k

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

R27 (1Bh)

Additional (1)

VROI

VREF to analogue output resistance

0: 1.5 k

1: 40 k

Table 26 Disabled Outputs to VREF Resistance

HEADPHONE SWITCH

The HPDETECT pin can be used as a headphone switch control input to automatically disable the
speaker output and enable the headphone output e.g. when a headphone is plugged into a jack
socket. In this mode, enabled by setting HPSWEN, HPDETECT switches between headphone and
speaker outputs (e.g. when the pin is connected to a mechanical switch in the headphone socket to
detect plug-in). The HPSWPOL bit reverses the pin's polarity. Note that the LOUT1, ROUT1, LOUT2
and ROUT2 bits in register 26 must also be set for headphone and speaker output (see Table 27 and
Table 28).

HPSWEN HPSWPOL HPDETECT

(PIN23)

L/ROUT1

(REG. 26)

L/ROUT2

(REG. 26)

HEADPHONE

ENABLED

SPEAKER
ENABLED

0 X X 0 0 no no

0 X X 0 1 no yes

0 X X 1 0 yes no

0 X X 1 1 yes yes

1 0 0 X 0 no no

1 0 0 X 1 no yes

1 0 1 0 X no no

1 0 1 1 X yes no

1 1 0 0 X no no

1 1 0 1 X yes no

1 1 1 X 0 no no

1 1 1 X 1 no yes

Table 27 Headphone Switch Operation

Production Data

WM8971L

PD Rev 4.1 August 2005

THERMAL SHUTDOWN

The speaker and headphone outputs can drive very large currents. To protect the WM8971L from
overheating a thermal shutdown circuit is included. If the device temperature reaches approximately
150

C and the thermal shutdown circuit is enabled (TSDEN = 1) then the analogue outputs

(OUT1L/R, OUT2L/R) will be disabled.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

R23 (17h)

Additional
Control (1)

8 TSDEN 0

Thermal Shutdown Enable

0 : thermal shutdown disabled

1 : thermal shutdown enabled

Table 29 Thermal Shutdown

HEADPHONE OUTPUT

Analogue outputs LOUT1/ROUT1 and LOUT2/ROUT2, can drive a 16

or 32 headphone load,

through DC blocking capacitors.

Figure 14 Recommended Headphone Output Configuration

The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
f

. Increasing the capacitance lowers f

, improving the bass response. Smaller capacitance values

will diminish the bass response. Assuming a 16 Ohm load and C1, C2 = 220

µF:

= 1 / 2

= 1 / (2

x 16 x 220µF) = 45 Hz

SPEAKER OUTPUT

LOUT2 and ROUT2 can differentially drive a mono 8

speaker as shown below.

Figure 15 Speaker Output Connection

The right channel is inverted by setting the ROUT2INV bit, so that the signal across the loudspeaker
is the sum of left and right channels.

LINE OUTPUT

The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs.
Recommended external components are shown below.

Figure 16 Recommended Circuit for Line Output

WM8971L

Production Data

PD Rev 4.1 August 2005

The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
f

. Assuming a 10 kOhm load and C1, C2 = 1

µF:

= 1 / 2

) C

= 1 / (2

x 10.1k x 1µF) = 16 Hz

Increasing the capacitance lowers f

, improving the bass response. Smaller values of C1 and C2 will

diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data into the WM8971L and outputting ADC data
from it. It uses five pins:

ADCDAT: ADC data output

ADCLRC: ADC data alignment clock

DACDAT: DAC data input

DACLRC: DAC data alignment clock

BCLK: Bit clock, for synchronisation

The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8971L operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).

Four different audio data formats are supported:

· Left

justified

· Right

justified

· DSP

mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8971L can be configured as either a master or slave mode device. As a master device the
WM8971L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8971L responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see
Table 23). Master and slave modes are illustrated below.

Figure 17 Master Mode

Figure 18 Slave Mode

Production Data

WM8971L

PD Rev 4.1 August 2005

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 19 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 20 Right Justified Audio Interface (assuming n-bit word length)

In I

S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.

Figure 21 I

S Justified Audio Interface (assuming n-bit word length)

WM8971L

Production Data

PD Rev 4.1 August 2005

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised in
Table 30. MS selects audio interface operation in master or slave mode. In Master mode BCLK,
ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample
rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs.

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

BCLKINV

BCLK invert bit (for master and slave
modes)

0 = BCLK not inverted

1 = BCLK inverted

Master / Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

LRSWAP

Left/Right channel swap

1 = swap left and right DAC data in
audio interface

0 = output left and right data as normal

right, left and i2s modes LRCLK
polarity

1 = invert LRCLK polarity

0 = normal LRCLK polarity

4 LRP

DSP Mode mode A/B select

1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)

0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)

3:2

WL[1:0]

Audio Data Word Length

11 = 32 bits (see Note)

10 = 24 bits

01 = 20 bits

00 = 16 bits

R7 (07h)

Digital Audio
Interface
Format

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode

10 = I

S Format

01 = Left justified

00 = Right justified

Table 30 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data.

AUDIO INTERFACE OUTPUT TRISTATE

Register bit TRI, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC,
DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by
default configured as inputs and only ADCDAT will be tri-stated, (see Table 31).

REGISTER

ADDRESS

BIT LABEL

DEFAULT DESCRIPTION

R24(18h)
Additional
Control (2)

3 TRI

0 Tristates ADCDAT and switches ADCLRC,

DACLRC and BCLK to inputs.

0 = ADCDAT is an output, ADCLRC, DACLRC
and BCLK are inputs (slave mode) or outputs
(master mode)

1 = ADCDAT is tristated, ADCLRC, DACLRC
and BCLK are inputs

Table 31 Tri-stating the Audio Interface

Production Data

WM8971L

PD Rev 4.1 August 2005

MASTER MODE ADCLRC AND DACLRC ENABLE

In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled
when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the
ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to
use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only operation is
required, (see Table 32).

REGISTER

ADDRESS

BIT LABEL

DEFAULT DESCRIPTION

R24(18h)
Additional
Control (2)

2 LRCM

0 Selects disable mode for ADCLRC and

DACLRC

0 = ADCLRC disabled when ADC (Left and

Right) disabled, DACLRC disabled when
DAC (Left and Right) disabled.

1 = ADCLRC and DACLRC disabled only when

ADC (Left and Right) and DAC (Left and
Right) are disabled.

Table 32 ADCLRC/DACLRC Enable

BIT CLOCK MODE

The default master mode bit clock generator produces a bit clock frequency based on the sample
rate and input MCLK frequency as shown in Table 36. When enabled by setting the appropriate
BCM[1:0] bits, the bit clock mode (BCM) function overrides the default master mode bit clock
generator to produce the bit clock frequency shown in the table below:

REGISTER

ADDRESS

BIT LABEL

DEFAULT DESCRIPTION

R8 (08h)

Clocking and
Sample Rate
Control

8:7 BCM[1:0]

BCLK Frequency

00 = BCM function disabled

01 = MCLK/4

10 = MCLK/8

11 = MCLK/16

Table 33 Master Mode BCLK Frequency Control

The BCM mode bit clock generator produces 16 or 24 bit clock cycles per sample. The number of bit
clock cycles per sample in this mode is determined by the word length bits (WL[1:0]) in the Digital
Audio Interface Format register (R7). When these bits are set to 00, there will be 16 bit clock cycles
per sample. When these bits are set to 01, 10 or 11, there will be 24 bit clock cycles per sample.
Please refer to Figure 26.

The BCM generator uses the ADCLRC signal, hence the ADCLRC signal must be enabled when
using bit clock mode. To enable the ADCLRC signal, either the ADC must be powered up or, if the
ADC is not in use, the LRCM bit must be set to enable both the ADCLRC and DACLRC signals when
either the ADC or the DAC is enabled.

When the BCM function is enabled, the following restrictions apply:

1. The bit clock invert (BCLKINV) function is not available.

2. The DAC and ADC must be operated at the same sample rate.

3. DSP late digital audio interface mode is not available and must not be enabled.

Figure 26 Bit Clock Mode

WM8971L

Production Data

PD Rev 4.1 August 2005

Note: The shaded bit clock cycles are present only when 24-bit mode is selected. Please refer to the
"Bit Clock Mode" description for details.

CLOCK OUTPUT

By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0],
register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01,
10 or 11 then ADCLRC pin is always an output even in slave mode or when TRI = `1', (see Table 34).
The ADC then uses the DACLRC pin as its LRCLK in both master and slave modes.

REGISTER

ADDRESS

BIT LABEL

DEFAULT DESCRIPTION

R27(1Bh)
Additional
Control (3)

[8:7] ADCLRM

[1:0]

Configures ADCLRC pin

00 = ADCLRC is ADC word clock input (slave
mode) or ADCLRC output (master mode)

01 = ADCLRC pin is MCLK output

10 = ADCLRC pin is MCLK / 5.5 output

11 = ADCLRC pin is MCLK / 6 output

Table 34 ADCLRC Clock Output

CLOCKING AND SAMPLE RATES

The WM8971L supports a wide range of master clock frequencies on the MCLK pin, and can
generate many commonly used audio sample rates directly from the master clock. The ADC and
DAC do not need to run at the same sample rate; several different combinations are possible.

There are two clocking modes:

`Normal' mode supports master clocks of 128f

, 192f

, 256f

, 384f

, and their multiples

(Note: f

refers to the ADC or DAC sample rate, whichever is faster)

USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio codec.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

CLKDIV2

Master Clock Divide by 2

1 = MCLK is divided by 2

0 = MCLK is not divided

5:1

SR [4:0]

00000

Sample Rate Control

R8 (08h)

Clocking and
Sample Rate
Control

USB

Clocking Mode Select

1 = USB Mode

0 = `Normal' Mode

Table 35 Clocking and Sample Rate Control

The clocking of the WM8971L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between `Normal' and USB mode.
Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination
of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their
accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change
proportionately.

Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.

The SR[4:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master
and slave mode.

Production Data

WM8971L

PD Rev 4.1 August 2005

MCLK

CLKDIV2=0

MCLK

CLKDIV2=1

ADC SAMPLE RATE

(ADCLRC)

DAC SAMPLE RATE

(DACLRC)

USB SR

[4:0] FILTER

TYPE

BCLK

(MS=1)

`Normal' Clock Mode (`*' indicates backward compatibility with WM8731)

8 kHz (MCLK/1536)

00110 *

MCLK/4

8 kHz (MCLK/1536)

48 kHz (MCLK/256)

00100 *

MCLK/4

12 kHz (MCLK/1024)

01000

MCLK/4

16 kHz (MCLK/768)

01010

MCLK/4

24 kHz (MCLK/512)

11100

MCLK/4

32 kHz (MCLK/384)

01100 *

MCLK/4

48 kHz (MCLK/256)

8 kHz (MCLK/1536)

00010 *

MCLK/4

48 kHz (MCLK/256)

00000 *

MCLK/4

12.288 MHz 24.576 MHz

96 kHz (MCLK/128)

01110 *

MCLK/2

8.0182 kHz (MCLK/1408)

10110 *

MCLK/4

8.0182 kHz (MCLK/1408)

44.1 kHz (MCLK/256)

10100 *

MCLK/4

11.025 kHz (MCLK/1024)

11000

MCLK/4

22.05 kHz (MCLK/512)

11010

MCLK/4

44.1 kHz (MCLK/256)

8.0182 kHz (MCLK/1408)

10010 *

MCLK/4

44.1 kHz (MCLK/256)

10000 *

MCLK/4

11.2896MHz

22.5792MHz

88.2 kHz (MCLK/128)

11110 *

MCLK/2

8 kHz (MCLK/2304)

00111 *

MCLK/6

8 kHz (MCLK/2304)

48 kHz (MCLK/384)

00101 *

MCLK/6

12 kHz (MCLK/1536)

01001

MCLK/6

16kHz (MCLK/1152)

16 kHz (MCLK/1152)

01011

MCLK/6

24kHz (MCLK/768)

24 kHz (MCLK/768)

11101

MCLK/6

32 kHz (MCLK/576)

01101 *

MCLK/6

48 kHz (MCLK/384)

00001 *

MCLK/6

48 kHz (MCLK/384)

8 kHz (MCLK/2304)

00011 *

MCLK/6

18.432MHz

36.864MHz

96 kHz (MCLK/192)

01111 *

MCLK/3

8.0182 kHz (MCLK/2112)

10111 *

MCLK/6

8.0182 kHz (MCLK/2112)

44.1 kHz (MCLK/384)

10101 *

MCLK/6

11.025 kHz (MCLK/1536)

11001

MCLK/6

22.05 kHz (MCLK/768)

11011

MCLK/6

44.1 kHz (MCLK/384)

8.0182 kHz (MCLK/2112)

10011 *

MCLK/6

44.1 kHz (MCLK/384)

10001 *

MCLK/6

16.9344MHz

33.8688MHz

88.2 kHz (MCLK/192)

11111 *

MCLK/3

USB Mode (`*' indicates backward compatibility with WM8731)

8 kHz (MCLK/1500)

00110 *

MCLK

8 kHz (MCLK/1500)

48 kHz (MCLK/250)

00100 *

MCLK

8.0214 kHz (MCLK/1496)

8.0214kHz (MCLK/1496)

10111 *

MCLK

8.0214 kHz (MCLK/1496)

44.118 kHz (MCLK/272)

10101 *

MCLK

11.0259 kHz (MCLK/1088)

11.0259kHz (MCLK/1088)

11001

MCLK

12 kHz (MCLK/1000)

01000

MCLK

16kHz (MCLK/750)

01010

MCLK

22.0588kHz (MCLK/544)

11011

MCLK

24kHz (MCLK/500)

11100

MCLK

32 kHz (MCLK/375)

01100 *

MCLK

44.118 kHz (MCLK/272)

8.0214kHz (MCLK/1496)

10011 *

MCLK

44.118 kHz (MCLK/272)

10001 *

MCLK

48 kHz (MCLK/250)

8 kHz (MCLK/1500)

00010 *

MCLK

48 kHz (MCLK/250)

00000 *

MCLK

88.235kHz (MCLK/136)

11111 *

MCLK

12.000MHz 24.000MHz

96 kHz (MCLK/125)

01110 *

MCLK

Table 36 Master Clock and Sample Rates

WM8971L

Production Data

PD Rev 4.1 August 2005

CONTROL INTERFACE

SELECTION OF CONTROL MODE

The WM8971L is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control
register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
selects the interface format.

MODE INTERFACE

FORMAT

Low 2

wire

High 3

wire

Table 37 Control Interface Mode Selection

3-WIRE SERIAL CONTROL MODE

In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.

B15

B14

B13

B12

B11

B10

SDIN

SCLK

CSB

control register address

control register data bits

latch

Figure 27 3-Wire Serial Control Interface

2-WIRE SERIAL CONTROL MODE

The WM8971L supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8971L).

The WM8971L operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8971L and the R/W bit is `0', indicating a write, then the WM8971L responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1',
the WM8971L returns to the idle condition and wait for a new start condition and valid address.

Once the WM8971L has acknowledged a correct address, the controller sends the first byte of
control data (B15 to B8, i.e. the WM8971L register address plus the first bit of register data). The
WM8971L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8971L acknowledges again by pulling SDIN low.

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8971L returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.

SDIN

SCLK

1st register data bit

DEVICE ADDRESS

(7 BITS)

RD / WR

BIT

ACK

(LOW)

CONTROL BYTE 1

(BITS 15 TO 8)

CONTROL BYTE 2

(BITS 7 TO 0)

remaining 8 bits of

STOP

START

ACK

(LOW)

ACK

(LOW)

Figure 28 2-Wire Serial Control Interface

Production Data

WM8971L

PD Rev 4.1 August 2005

The WM8971L has two possible device addresses, which can be selected using the CSB pin.

CSB STATE

DEVICE ADDRESS

Low

0011010 (0 x 34h)

High

0011011 (0 x 36h)

Table 38 2-Wire MPU Interface Address Selection

POWER SUPPLIES

The WM8971L can use up to four separate power supplies:

AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers.
AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power
consumption (except for power consumed in the headphone). A large AVDD slightly improves
audio quality.

HPVDD / HPGND: Headphone supply, powers analogue outputs L/ROUT1, L/ROUT2 and
MONOOUT. HPVDD is normally tied to AVDD, but requires separate layout and decoupling
capacitors to curb harmonic distortion. If HPVDD is lower than AVDD, the output signal may be
clipped.

DCVDD: Digital core supply, powers all digital functions except the audio and control
interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The
return path for DCVDD is DGND, which is shared with DBVDD.

DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it
possible to run the digital core at very low voltages, saving power, while interfacing to other
digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has
no effect on audio quality. DBVDD can range from 1.8V to 3.6V. The return path for DBVDD is
DGND, which is shared with DCVDD.

It is possible to use the same supply voltage on all four. However, digital and analogue supplies
should be routed and decoupled separately to keep digital switching noise out of the analogue signal
paths.

POWER MANAGEMENT

The WM8971L has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,
it is important to enable or disable functions in the correct order (see Applications Information).
VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a
50kOhm potential divider or, for low power maintenance of Vref when all other blocks are disabled,
as a 500kOhm potential divider.

WM8971L

Production Data

PD Rev 4.1 August 2005

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

Vmid divider enable and select

00 Vmid disabled (for OFF mode)

01 50k

divider enabled (for

playback/record)

10 500k

divider enabled (for low-power

standby)

11 5k

divider enabled (for fast start-up)

VREF

VREF (necessary for all other functions)

Power down = 0

Power up = 1

AINL

Analogue in PGA Left

Power down = 0

Power up = 1

AINR

Analogue in PGA Right

Power down = 0

Power up = 1

3 ADCL 0

ADC

Left

Power down = 0

Power up = 1

2 ADCR 0

ADC

Right

Power down = 0

Power up = 1

R25 (19h)

Power
Management
(1)

1 MICB 0

MICBIAS

Power down = 0

Power up = 1

8 DACL 0

DAC

Left

Power down = 0

Power up = 1

7 DACR 0

DAC

Right

Power down = 0

Power up = 1

6 LOUT1 0

LOUT1

Output

Buffer*

Power down = 0

Power up = 1

5 ROUT1 0

ROUT1

Output

Buffer*

Power down = 0

Power up = 1

4 LOUT2 0

LOUT2

Output

Buffer*

Power down = 0

Power up = 1

3 ROUT2 0

ROUT2

Output

Buffer*

Power down = 0

Power up = 1

R26 (1Ah)

Power
Management
(2)

MONO

MONOOUT Output Buffer and Mono Mixer

Power down = 0

Power up = 1

* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when
ROUT1=1 or ROUT2=1.

Table 39 Power Management

Production Data

WM8971L

PD Rev 4.1 August 2005

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8971L, the master clock may be
stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.
However, since setting DIGENB has no effect on the power consumption of other system
components external to the WM8971L, it is preferable to disable the master clock at its source
wherever possible.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

R25 (19h)

Additional Control
(1)

DIGENB

Master clock disable

0: master clock enabled

1: master clock disabled

Table 40 ADC and DAC Oversampling Rate Selection

Note: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set to
zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may prevent
DACs and ADCs from re-starting correctly.

SAVING POWER BY REDUCING OVERSAMPLING RATE

The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode.
Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in
a slight decrease in noise performance but will also reduce the power consumption of the device.

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

ADCOSR

ADC oversample rate select

1 = 64x (lowest power)

0 = 128x (best SNR)

R24 (18h)

Additional Control
(2)

DACOSR

DAC oversample rate select

1 = 64x (lowest power)

0 = 128x (best SNR)

Table 41 ADC and DAC Oversampling Rate Selection

Note: ADCOSR set to 1, 64x oversample mode, is not supported in USB mode (USB=1)

SAVING POWER AT HIGHER SUPPLY VOLTAGES

The analogue supplies to the WM8971L can run from 1.8V to 3.6V. By default, all analogue circuitry
on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down
to 1.8V.

At lower voltages, performance can be improved by increasing the bias current. If low

power operation is preferred the bias current can be left at the default setting. This is controlled as
shown below.

REGISTER

ADDRESS

BIT LABEL

DEFAULT

DESCRIPTION

R23 (17h)

Additional
Control(1)

7:6 VSEL

[1:0]

Analogue Bias optimization

00: Highest bias current, optimized for
AVDD=1.8V

01: Bias current, optimized for AVDD=2.5V

1X: Lowest bias current, optimized for AVDD=3.3V

WM8971L

Production Data

PD Rev 4.1 August 2005

REGISTER MAP

REGISTER

ADDRESS

(Bit 15 9)

remarks

Bit[8] Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]

default page

ref

R0 (00h)

0000000

Left Input volume

LIVU

LINMUTE

LIZC

LINVOL

010010111

R1 (01h)

0000001

Right Input volume

RIVU

RINMUTE

RIZC

RINVOL

010010111

R2 (02h)

0000010

LOUT1 volume

LO1VU

LO1ZC

LOUT1VOL[6:0]

001111001

R3 (03h)

0000011

ROUT1 volume

RO1VU

RO1ZC

ROUT1VOL[6:0]

001111001

(04h)

0000100 Reserved

0 0 0 0 0 0 0 0 0 000000000 -

R5 (05h)

0000101

ADC and DAC Control ADCDIV2 DACDIV2

ADCPOL[1:0]

HPOR

DACMU

DEEMPH[1:0]

ADCHPD

000001000

21,27,30

(06h)

0000110 Reserved

0 0 0 0 0 0 0 0 0 000000000 -

(07h) 0000111

Audio

Interface

0 BCLKINV MS LRSWAP LRP

WL[1:0]

FORMAT[1:0]

000001010

R8 (08h)

0001000

Sample rate

BCM[1:0]

CLKDIV2

SR[4:0]

USB

000000000

(09h)

0001001 Reserved

0 0 0 0 0 0 0 0 0 000000000 -

R10 (0Ah)

0001010

Left DAC volume

LDVU

LDACVOL[7:0]

011111111

R11 (0Bh)

0001011

Right DAC volume

RDVU

RDACVOL[7:0]

011111111

R12 (0Ch)

0001100

Bass control

BASS[3:0]

000001111

R13 (0Dh)

0001101

Treble control

TRBL[3:0]

000001111

R15 (0Fh)

0001111

Reset

writing to this register resets all registers to their default state

not reset

R16

(10h)

0010000 Reserved

0 0 0 0 0 0 0 0 0 000000000 -

R17 (11h)

0010001

ALC1

ALCSEL[1:0]

MAXGAIN[2:0]

ALCL[3:0]

001111011

R18 (12h)

0010010

ALC2

ALCZC

HLD[3:0]

000000000

R19 (13h)

0010011

ALC3

DCY[3:0]

ATK[3:0]

000110010

R20 (14h)

0010100

Noise Gate

NGTH[4:0]

NGG[1:0]

NGAT

000000000

R21 (15h)

0010101

Left ADC volume

LAVU

LADCVOL[7:0]

011000011

R22 (16h)

0010110

Right ADC volume

RAVU

RADCVOL[7:0]

011000011

R23 (17h)

0010111

Additional control(1)

TSDEN

VSEL[1:0]

DMONOMIX[1:0]

DATSEL[1:0]

DACINV

TOEN

011000000

19,21,30,37

R24 (18h)

0011000

Additional control(2)

HPSWEN HPSWPOL ROUT2INV

TRI LRCM

ADCOSR

DACOSR

000000000

34, 36,50

R25 (19h)

0011001

Pwr Mgmt (1)

VMIDSEL[1:0]

VREF

AINL

AINR

ADCL

ADCR

MICB

DIGENB

000000000

R26 (1Ah)

0011010

Pwr Mgmt (2)

DACL

DACR

LOUT1

ROUT1

LOUT2

ROUT2

MONO

000000000

R27 (1Bh)

0011011

Additional Control (3)

ADCLRM[1:0]

VROI

HPFLREN

000000000

R31 (1Fh)

0011111

ADC input mode

MONOMIX[1:0]

000000000

R32 (20h)

0100000

ADCL signal path

LINSEL[1:0]

LMICBOOST[1:0]

000000000

R33 (21h)

0100001

ADCR signal path

RINSEL[1:0]

RMICBOOST[1:0]

000000000

R34 (22h)

0100010

Left out Mix (1)

LD2LO

LI2LO

LI2LOVOL[2:0]

LMIXSEL[2:0]

001010000

R35 (23h)

0100011

Left out Mix (2)

RD2LO

RI2LO

RI2LOVOL[2:0]

001010000

R36 (24h)

0100100

Right out Mix (1)

LD2RO

LI2RO

LI2ROVOL[2:0]

RMIXSEL[2:0]

001010000

R37 (25h)

0100101

Right out Mix (2)

RD2RO

RI2RO

RI2ROVOL[2:0]

001010000

R38 (26h)

0100110

Mono out Mix (1)

LD2MO

LI2MO

LI2MOVOL[2:0]

001010000

R39 (27h)

0100111

Mono out Mix (2)

RD2MO

RI2MO

RI2MOVOL[2:0]

001010000

R40 (28h)

0101000

LOUT2 volume

LO2VU

LO2ZC

LOUT2VOL[6:0]

001111001

R41 (29h)

0101001

ROUT2 volume

RO2VU

RO2ZC

ROUT2VOL[6:0]

001111001

R42 (2Ah)

0101010

MONOOUT volume

MOZC

MOUTVOL[6:0]

001111001

Note:

All unused register bits must be set to `0' when writing to WM8971L.

Production Data

WM8971L

PD Rev 4.1 August 2005

DIGITAL FILTER CHARACTERISTICS

The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2
and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is
shown in the proceeding pages.

PARAMETER TEST

CONDITIONS

MIN

TYP

MAX

UNIT

ADC Filter Type 0 (USB Mode, 250fs operation)

+/- 0.05dB

0.416fs

Passband

-6dB

0.5fs

Passband Ripple

+/-

0.05

Stopband

0.584fs

Stopband Attenuation

f > 0.584fs

-60

ADC Filter Type 1 (USB mode, 272fs or Normal mode operation)

+/- 0.05dB

0.4535fs

Passband

-6dB

0.5fs

Passband Ripple

+/-

0.05

Stopband

0.5465fs

Stopband Attenuation

f > 0.5465fs

-60

-3dB

3.7

-0.5dB

10.4

High Pass Filter Corner
Frequency

-0.1dB

21.6

DAC Filter Type 0 (USB mode, 250fs operation)

+/- 0.03dB

0.416fs

Passband

-6dB

0.5fs

Passband Ripple

+/-0.03

Stopband

0.584fs

Stopband Attenuation

f > 0.584fs

-50

DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)

+/- 0.03dB

0.4535fs

Passband

-6dB

0.5fs

Passband Ripple

+/-

0.03

Stopband

0.5465fs

Stopband Attenuation

f > 0.5465fs

-50

Table 42 Digital Filter Characteristics

DAC FILTERS

ADC FILTERS

Mode Group

Delay

Mode Group

Delay

0 (250 USB)

11/FS

0 (250 USB)

13/FS

(256/272) 16/FS

(256/272) 23/FS

2 (250 USB, 96k mode)

4/FS

2 (250 USB, 96k mode)

4/FS

3 (256/272, 88.2/96k mode)

3/FS

3 (256/272, 88.2/96k mode)

5/FS

Table 43 ADC/DAC Digital Filters Group Delay

TERMINOLOGY

Stop Band Attenuation (dB) the degree to which the frequency spectrum is attenuated (outside audio band)

Pass-band Ripple any variation of the frequency response in the pass-band region

Production Data

WM8971L

PD Rev 4.1 August 2005

-100

-80

-60

-40

-20

0.5

1.5

2.5

Response (dB)

Frequency (Fs)

-0.25

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25

0.05

0.1

0.15

0.2

0.25

Response (dB)

Frequency (Fs)

Figure 35 DAC Digital Filter Frequency Response Type 3 Figure 36 DAC Digital Filter Ripple Type 3

ADC FILTER RESPONSES

-100

-80

-60

-40

-20

0.5

1.5

2.5

Response (dB)

Frequency (Fs)

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Response (dB)

Frequency (Fs)

Figure 37 ADC Digital Filter Frequency Response Type 0

Figure 38 ADC Digital Filter Ripple Type 0

-100

-80

-60

-40

-20

0.5

1.5

2.5

Response (dB)

Frequency (Fs)

-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Response (dB)

Frequency (Fs)

Figure 39 ADC Digital Filter Frequency Response Type 1

Figure 40 ADC Digital Filter Ripple Type 1

Production Data

WM8971L

PD Rev 4.1 August 2005

LINE INPUT CONFIGURATION

When LINPUT1/RINPUT1 or MIC are used as line inputs, the microphone boost and ALC functions
should normally be disabled.

In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This
may require a potential divider circuit in some applications. It is also recommended to remove RF
interference picked up on any cables using a simple first-order RC filter, as high-frequency
components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals
with no DC bias should be fed to the WM8971L through a DC blocking capacitor, e.g. 1

µF.

MICROPHONE INPUT CONFIGURATION

Figure 53 Recommended Circuit for Line Input

For interfacing to a microphone, the ALC function should be enabled and the microphone boost
switched on. Microphones held close to a speaker's mouth would normally use the 13dB gain setting,
while tabletop or room microphones would need a 29dB boost.

The recommended application circuit is shown above. R1 and R2 form part of the biasing network
(refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type
microphones that require a voltage bias. R2 should always be present to prevent the microphone
input from charging to a high voltage which may damage the microphone on connection. R1 and R2
should be large so as not to attenuate the signal from the microphone, which can have source
impedance greater than 2kOhm. C1 together with the source impedance of the microphone and the
WM8971L input impedance forms an RF filter. C2 is a DC blocking capacitor to allow the microphone
to be biased at a different DC voltage to the MICIN signal.

MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS

To minimise any pop or click noise when the system is powered up or down, the following procedures
are recommended.

POWER UP

· Switch on power supplies. By default the WM8971L is in Standby Mode, the DAC is

digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF
(DACMU = 1 Power Management registers 1 and 2 are all zeros).

· Enable Vmid and VREF.
· Enable DACs as required
· Enable line and / or headphone output buffers as required.
· Set DACMU = 0 to soft-un-mute the audio DACs.

POWER DOWN

· Set DACMU = 1 to soft-mute the audio DACs.
· Disable all output buffers.
· Switch off the power supplies.

47kOhm

220pF

1uF

AGND

AGND AGND

L/RINPUT1
MIC

FROM

MICROPHONE

R1
680 Ohm to 2.2kOhm
check microphone's specification

MICBIAS

Production Data

WM8971L

PD Rev 4.1 August 2005

PACKAGE DIMENSIONS

DM030.E

FL: 32 PIN QFN PLASTIC PACKAGE 5

0.9 mm BODY, 0.50 mm LEAD PITCH

NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM
PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF
ETCHING OF LEADFRAME.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY.
6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.

SEE DETAIL B

E2/2

CORNER
TIE BAR

D2/2

SEE DETAIL A

INDEX AREA
(D/2 X E/2)

TOP VIEW

aaa

2 X

aaa

2 X

DETAIL B

TERMI

NAL T

I
P

DAT

e/2

DETAIL A

bbb

32x b

2x K

0.5

0.4

3 m

CORNER
TIE BAR

Symbols

Dimensions (mm)

MIN

NOM

MAX

NOTE

0.85

0.90

1.00

0.05

0.02

0.2 REF

0.30

0.23

0.18

5.00

3.4

3.3

3.2

0.5 BSC

0.35

0.4

0.45

0.1

b(min)/2

0.20

aaa

bbb

ccc

REF:

0.15

0.10
0.10

JEDEC, MO-220, VARIATION VHHD-2

Tolerances of Form and Position

4.90

5.10

5.00

4.90

5.10

3.4

3.3

3.2

EXPOSED
GROUND
PADDLE

BOTTOM VIEW

0.08

ccc

(A3)

SEATING PLANE

SIDE VIEW

WM8971L

Production Data

PD Rev 4.1 August 2005

IMPORTANT NOTICE

Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.

WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.

In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.

WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's
approval, license, warranty or endorsement thereof.

Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.

Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.

ADDRESS:

Wolfson Microelectronics plc

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email ::

sales@wolfsonmicro.com

Production Data

WM8971L

PD Rev 4.1 August 2005

Revision History

DATE

RELEASE

DESCRIPTION OF CHANGES

PAGES

14/08/03 2.0

Initial

Release

30/03/04

3.0

Pin Configuration Pins 11, 24 and 26 renamed

Ordering Information Peak Soldering Temp added and order codes changed

Pin Description Pin Descriptions for 11, 24 and 26 changed

Speaker Output Power updated

12/05/04

4.0

Updated to Production Data

Block Diagram ROUT2 updated to show inverting buffer, buffer added to LD2MO
and RD2MO

Pin Diagram rotated

Pin Description, Ground padded note added

Recommended Operating Conditions, DBVDD to 1.7

Electrical Characteristics updated, Speaker Output

Speaker THD and Noise Versus Power added

Fig 3, Bit Clock Mode added

Control Interface Timing 3-wire mode test conditions table updated

Power on Reset added

Speaker Output THD Versus Power removed

PGA Control text updated

Automatic Level Control text updated

Note added to Noise Gate Control table

Output Mixers, mono mixer para added

Timing Diagrams, Figs, 17,18 and 19 updated LRP = 1 changed to LRP = 0

DSP diagrams updated, Figs 20, 21

Bit Clock added

Clock Output table and text updated

Updates to Table 38 Power Management

Group Delay added

Recommended External Component diagram updated to show component
values, ground paddle added

External component values table deleted

Ref updated in Package Drawing

16/08/05 4.2

Ordering information leaded parts removed

Pin description - Changed pin 19 description

Electrical Characteristics ADC THD max values removed

Updated Operation Mode table (Stereo Headphone playback, AINL/UR changed
from 1 to 0)

Package Drawing updated to DM030.E to include ground paddle info

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WM8971

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WM8971