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Электронный компонент: X1288-4.5A

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PRELIMINARY
REV 1.1.26 1/13/03
Characteristics subject to change without notice.
1 of 28
www.xicor.com
256K (32K x 8)
2-Wire
TM
RTC
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
Real Time Clock/Calendar
-- Tracks time in Hours, Minutes, Seconds and Hun-
dredths of a Second
-- Day of the Week, Day, Month, and Year
2 Polled Alarms (Non-volatile)
-- Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
-- Repeat Mode (periodic interrupts)
Oscillator Compensation on chip
-- Internal feedback resistor and compensation
capacitors
-- 64 position Digitally Controlled Trim Capacitor
-- 6 digital-frequency adjustment setting to 30ppm
CPU Supervisor Functions
-- Power On Reset, Low Voltage Sense
-- Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
Battery Switch or Super Cap Input
32K x 8 Bits of EEPROM
-- 128-Byte Page Write Mode
-- 8 modes of Block LockTM Protection
-- Single Byte Write Capability
High Reliability
--Data Retention: 100 years
--Endurance: 100,000 cycles per byte
2-WireTM Interface interoperable with I2C*
-- 400kHz data transfer rate
Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
Low Power CMOS
-- 1.25A Operating Current (Typical)
Small Package Options
-- 16-Lead SOIC and 14-Lead TSSOP
APPLICATIONS
Utility Meters
HVAC Equipment
Audio / Video Components
Set Top Box / Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers / PDA
POS Equipment
Test Meters / Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial / Medical / Automotive
DESCRIPTION
The X1288 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 32kx8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
X1288
Preliminary Information
BLOCK DIAGRAM
X1
X2
Oscillator
Frequency
Timer
Logic
Divider
Calendar
8
Control/
Registers
1Hz
Time
Keeping
Registers
Alarm Regs
Compare
Mask
RESET
Control
Decode
Logic
Alarm
(EEPROM)
(EEPROM)
SCL
SDA
Serial
Interface
Decoder
256K
EEPROM
ARRAY
Watchdog
Timer
Low Voltage
Reset
Registers
Status
(SRAM)
Select
PHZ/IRQ
V
CC
V
BACK
32.768kHz
(SRAM)
Battery
Circuitry
Switch
OSC
Compensation
*I2C is a Trademark of Philips.
New Features
Repetitive Alarms &
Temperature Compensation
PRELIMINARY
X1288 Preliminary Information
REV 1.1.26 1/13/03
Characteristics subject to change without notice.
2 of 28
www.xicor.com
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds and 1/100 of a
second. The Calendar has separate registers for Date,
Month, Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 100 Hz, or 32,768 Hz.
The X1288 device integrates CPU Supervisor func-
tions and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from power
on. It will also assert RESET when Vcc goes below the
specified threshold. The V
trip
threshold is user repro-
grammable. There is a WatchDog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s, 1.75s) and a
disabled setting. The watchdog activates the RESET
pin when it expires.
The device offers a backup power input pin. This
V
BACK
pin allows the device to be backed up by battery
or SuperCap. The entire X1288 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1288 device remains fully operational
down to 1.8 volts (Standby Mode).
The X1288 device provides 256K bits of EEPROM with 8
modes of BlockLockTM control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
V
BACK
This input provides a backup supply voltage to the
device. V
BACK
supplies power to the device in the
event the V
CC
supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
RESET Output RESET
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
that the voltage has dropped below a fixed V
TRIP
thresh-
old. It is an open drain active LOW output. Recom-
mended value for the pullup resistor is 5K Ohms. If
unused, tie to ground.
Programmable Frequency/Interrupt Output PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a fre-
quency of 32.768kHz, 100Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. Refer to "Programmable frequency output
bits" on page 6.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1288 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more information.
X1288
X1
X2
V
BACK
V
CC
NC
PHZ/IRQ
NC
V
SS
1
2
3
4
13
14
12
11
14-pin TSSOP
NC
NC
SCL
NC
RESET
SDA
5
6
7
9
10
8
16-pin SOIC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X1
X2
NC
V
SS
NC
NC
RESET
NC
V
BACK
V
CC
PHZ/IRQ
NC
SCL
NC
SDA
NC
NC = No internal connection
PRELIMINARY
X1288 Preliminary Information
REV 1.1.26 1/13/03
Characteristics subject to change without notice.
3 of 28
www.xicor.com
Figure 1. Recommended Crystal connection
POWER CONTROL OPERATION
The power control circuit accepts a V
CC
and a V
BACK
input. The power control circuit powers the clock from
V
BACK
when V
CC
< V
BACK
- 0.2V. It will switch back to
power the device from V
CC
when V
CC
exceeds V
BACK
.
Figure 2. Power Control
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate
internal representation of the 1/100 of a second, sec-
ond, minute, hour, day, date, month, and year. The
RTC has leap-year correction. The clock also corrects
for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the
X1288 powers up after the loss of both V
CC
and
V
BACK
, the clock will not operate until at least one byte
is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the SSEC register reset to "0" at the
next sub-second update after the stop bit is written.
The 1Hz frequency output from the PHZ/IRQ pin will
be reset to restart after the stop bit is written. The RTC
continues to update the time while an RTC register
write is in progress and the RTC continues to run dur-
ing any nonvolatile write sequences. A single byte may
be written to the RTC without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC performance
will also be dependent upon temperature. The frequency
deviation of the crystal is a function of the turnover
temperature of the crystal from the crystal's nominal
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
these parameters are available from the crystal
manufacturer. Xicor's RTC family provides on-chip crystal
compensation networks to adjust load-capacitance to
tune oscillator frequency from +116 ppm to 37 ppm
when using a 12.5 pF load crystal. For more detail
information see the Application section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of "1101111x" and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section "Writing to the Clock/Control Registers.")
X1
X2
V
BACK
In
Voltage
V
CC
On
Off
PRELIMINARY
X1288 Preliminary Information
REV 1.1.26 1/13/03
Characteristics subject to change without notice.
4 of 28
www.xicor.com
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Range
Default
7
6
5
4
3
2
1
0
(optional)
003F
Status
SR
BAT
AL1
AL0
0
0
RWEL
WEL
RTCF
01h
0037
RTC
(SRAM)
SSEC
SS23
SS22
SS21
SS20
SS13
SS12
SS11
SS10
0-99
xxh
0036
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
xxh
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
xxh
0034
MO
0
0
0
G20
G13
G12
G11
G10
1-12
xxh
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
xxh
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
xxh
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
xxh
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
xxh
0013
Control
(EEPROM)
DTR
0
0
0
0
0
DTR2
DTR1
DTR0
00h
0012
ATR
0
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
0011
INT
IM
AL1E
AL0E
FO1
FO0
Read Only Read Only Read Only
00h
0010
BL
BP2
BP1
BP0
WD1
WD0
Read Only Read Only Read Only
00h
000F
Alarm1
(EEPROM)
Y2K1
Read-only - Default = 20h
20
20h
000E
DWA1
EDW1
0
0
0
0
DY2
DY1
DY0
0-6
00h
000D
YRA1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
000C
MOA1
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
0007
Alarm0
(EEPROM)
Y2K0
Read-only - Default = 20h
20
20h
0006
DWA0
EDW0
0
0
0
0
DY2
DY1
DY0
0-6
00h
0005
YRA0
Unused - Default = RTC Year value (No EEPROM) Future expansion
0004
MOA0
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
00h
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
PRELIMINARY
X1288 Preliminary Information
REV 1.1.26 1/13/03
Characteristics subject to change without notice.
5 of 28
www.xicor.com
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to `0',
there are no alarms.
The user can set the X1288 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to `1' and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to `1' and the HRAn*
and MNAn* registers are set to 9:30 PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
(H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99. The SSEC
register is read-only.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as `0'.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indi-
cator with a `1' representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1288 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply--Volatile
This bit set to "1" indicates that the device is operating
from V
BACK
, not V
CC
. It is a read-only bit and is set/reset
by hardware (X1288 internally). Once the device begins
operating from V
CC
, the device sets this bit to "0".
AL1, AL0: Alarm bits--Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to `1'. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch--Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to "1" prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
Addr
7
6
5
4
3
2
1
0
003Fh
BAT
AL1
AL0
0
0
RWEL
WEL
RTCF
Default
0
0
0
0
0
0
0
1