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Электронный компонент: X20C17PM-55

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X20C17
1
Xicor, Inc. 1992, 1995 Patents Pending
Characteristics subject to change without notice
2015-2.5 8/1/97 T1/C0/D0 SH
AUTOSTORETM NOVRAM is a trademark of Xicor, Inc.
High Speed AUTOSTORETM NOVRAM
DESCRIPTION
The Xicor X20C17 is a 2K x 8 NOVRAM featuring a high-
speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E
2
PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E
2
PROM at power-down. The X20C17
is fabricated with advanced CMOS floating gate technol-
ogy to achieve high speed with low power and wide
power-supply margin. The X20C17 features a compat-
ible JEDEC approved byte-wide memory pinout for
industry standard SRAMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E
2
PROM (store) and E
2
PROM to
RAM (recall). The store operation is completed in 2.5ms
or less. An automatic array recall operation reloads the
contents of the E
2
PROM into RAM upon power-up.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E
2
PROM, and a minimum 1,000,000 store operations to
the E
2
PROM. Data retention is specified to be greater
than 100 years.
FEATURES
24-Pin Standard SRAM DIP Pinout
Fast Access Time: 35ns, 45ns, 55ns
High Reliability
--Endurance: 1,000,000 Nonvolatile Store
Operations
--Retention: 100 Years Minimum
AUTOSTORETM NOVRAM
--Automatically Stores SRAM Data Into the
E
2
PROM Array When V
CC
Low Threshold is
Detected
--E
2
PROM Data Automatically Recalled Into
RAM Upon Power-up
Low Power CMOS
--Standby: 250
A
Infinite E
2
PROM Array Recall, and RAM Read
and Write Cycles
16K
X20C17
2K x 8 Bit
PIN CONFIGURATION
2015 ILL F02.1
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
VCC
A8
A9
WE
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
X20C17
2
3
4
5
6
7
8
9
10
11
12
22
23
24
21
20
19
18
17
16
15
14
13
PLASTIC
A
PPLICATION
N
OTE
A V A I L A B L E
AN56
X20C17
2
PIN DESCRIPTIONS
Addresses (A
0
A
10
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (
OE
)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of
CE
,
WE
.
Data In/Data Out (I/O
0
I/O
7
)
Data is written to or read from the X20C17 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CE
or
OE
is HIGH.
Write Enable (
WE
)
The Write Enable input controls the writing of data to the
static RAM.
FUNCTIONAL DIAGRAM
2015 FHD F01.1
PIN NAMES
Symbol
Description
A
0
A
10
Address Inputs
I/O
0
I/O
7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
V
CC
+5V
V
SS
Ground
2015 PGM T01
VCC SENSE
ROW
SELECT
CONTROL
LOGIC
COLUMN
SELECT
&
I/OS
EEPROM ARRAY
HIGH SPEED
2K x 8
SRAM
ARRAY
CE
OE
WE
A3A8
I/O0I/O7
A0A2
A9A10
RECALL
ST
ORE
X20C17
3
DEVICE OPERATION
The
CE
,
OE
, and
WE
inputs control the X20C17 opera-
tion. The X20C17 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW. A write operation requires
CE
and
WE
to be LOW. There is no limit to the number of
read or write operations performed to the RAM portion
of the X20C17.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E
2
PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E
2
PROM array.
Recall operations are performed automatically upon
power-up.
Store operations are performed automatically upon
power-down. The store operation take a maximum of
2.5ms.
Write Protection
The X20C17 supports two methods of protecting the
nonvolatile data.
--If after power-up no RAM write operations have
occured, no AUTOSTORE operation can be initiated.
--V
CC
Sense All functions are inhibited when V
CC
is
3V typical.
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user's application.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X20C17
4
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
CC1
V
CC
Current (Active)
100
mA
WE
= V
IH
,
CE
=
OE
= V
IL
Address Inputs = 0.4V/2.4V Levels
@ f = 20MHz, All I/Os = Open
I
CC2
(2)
V
CC
Current During
2.5
mA
All I/Os = Open
AUTOSTORE
I
SB1
V
CC
Standby Current
10
mA
All Inputs = V
IH
, All I/Os = Open
(TTL Input)
I
SB2
V
CC
Standby Current
250
A
All Inputs = V
CC
0.3V
(CMOS Input)
All I/Os = Open
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
,
CE
= V
IH
V
IL
(1)
Input LOW Voltage
1
0.8
V
V
IH
(1)
Input HIGH Voltage
2
V
CC
+ 1
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 4mA
V
OH
Output HIGH Voltage
2.4
V
I
OH
= 4mA
2015 PGM T04.3
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to V
SS .......................................
1V to +7V
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds) ...... 300
C
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any conditions other than those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Military
55
C
+125
C
2015 PGM T02.1
Supply Voltage
Limits
X20C17
4.5V to 5.25V
2015 PGM T03.1
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR
(2)
Power-Up to RAM Operation
100
s
t
PUW
(2)
Power-Up to Nonvolatile Operation
5
ms
2015 PGM T05
Notes: (1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
CAPACITANCE T
A
= +25
C, f = 1MHz, V
CC
= 5V.
Symbol
Test
Max.
Units
Conditions
C
I/O
(2)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(2)
Input Capacitance
6
pF
V
IN
= 0V
2015 PGM T06.2
X20C17
5
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
Data Changes Per Bit
Store Cycles
1,000,000
Store Cycles
Data Retention
100
Years
2015 PGM T07.1
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
5ns
Input and Output
Timing Levels
1.5V
2015 PGM T08.1
2015 FHD F04
MODE SELECTION
CE
WE
OE
Mode
I/O
Power
H
X
X
Not Selected
Output High Z
Standby
L
H
L
Read RAM
Output Data
Active
L
L
H
Write "1" RAM
Input Data High
Active
L
L
H
Write "0" RAM
Input Data Low
Active
L
L
L
Not Allowed
Output High Z
Active
L
H
H
No Operation
Output High Z
Active
2015 PGM T09
5V
893
347
OUTPUT
30pF