Xicor, Inc. 2000 Patents Pending
9800-5004.1 1/31/00 EP
Characteristics subject to change without notice.
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FEATURES
Save Critical Data with Programmable Block
Lock Protection
--Block Lock (first page, first 2 pages, first 4
pages, first 8 pages, 1/4, 1/2, or all of E
2
PROM
Array)
--Software Write Protection
--Programmable Hardware Write Protect
In Circuit Programmable ROM Mode
400KHz 2-Wire Serial Interface
--Schmitt Trigger Input Noise Suppression
--Output Slope Control for Ground Bounce
Noise Elimination
Longer Battery Life With Lower Power
--Active Read Current Less Than 1mA
--Active Write Current Less Than 3mA
--Standby Current Less Than 1
A
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Versions
64 Byte Page Write Mode
--Minimizes Total Write Time Per Word
Internally Organized 32K x 8
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
--Typical Write Cycle Time of 5ms
High Reliability
--Endurance: 100,000 Cycles
--Data Retention: 100 Years
8-Lead XBGA, 8-Lead SOIC, 14-Lead TSSOP
DESCRIPTION
The X24257 is a CMOS Serial E
2
PROM, internally
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
Three device select inputs (S
0
S
2
) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and Pro-
grammable Hardware Write Protect. The Software
Write Protect feature prevents any nonvolatile writes to
the device until the WEL bit in the Write Protect Regis-
ter is set. The Block Lock Protection feature gives the
user eight array block protect options, set by program-
ming three bits in the Write Protect Register. The Pro-
grammable Hardware Write Protect feature allows the
user to install the device with WP tied to V
CC
, write to
and Block Lock the desired portions of the memory
array in circuit, and then enable the In Circuit Program-
mable ROM Mode by programming the WPEN bit
HIGH in the Write Protect Register. After this, the
Block Locked portions of the array, including the Write
Protect Register itself, are protected from being
erased if WP is high.
Preliminary
X24257
400KHz 2-Wire Serial E
2
PROM with Block Lock
TM
256K
32K x 8Bit
FUNCTIONAL DIAGRAM
SERIAL E
2
PROM DATA
AND ADDRESS (SDA)
SCL
S
1
S
0
WP
COMMAND
DECODE
AND
CONTROL
LOGIC
BLOCK LOCK AND
WRITE PROTECT
CONTROL LOGIC
DEVICE
SELECT
LOGIC
WRITE
PROTECT
REGISTER
PAGE
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
WRITE VOLTAGE
CONTROL
SERIAL E
2
PROM
ARRAY
32K x 8
S
2
X24257
Characteristics subject to change without notice.
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Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
, S
2
)
The device select inputs (S
0
, S
1
, S
2
) are used to set
bits in the slave address. This allows up to eight
devices to share a common bus. These inputs can be
static or actively driven. If used statically they must be
tied to V
SS
or V
CC
as appropriate. If actively driven,
they must be driven with CMOS levels (driven to V
CC
or V
SS
) and they must be constant between each start
and stop issued on the SDA bus. These pins have an
active pull down internally and will be sensed as low if
the pin is left unconnected.
Write Protect (WP)
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Pro-
tect feature. When held LOW, Hardware Write Protec-
tion is disabled. When this input is held HIGH, and the
WPEN bit in the Write Protect Register is set HIGH,
the Write Protect Register is protected, preventing
changes to the Block Lock Protection and WPEN bits.
PIN NAMES
PIN CONFIGURATION
Symbol
Description
S
0
, S
1
, S
2
Device Select Inputs
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
8 Lead PDIP/SOIC
VCC
WP
SCL
S0
S1
1
2
3
4
6
7
8
X24257
VSS
SDA
S
2
5
14 Lead TSSOP
VCC
WP
SCL
S0
S1
NC
1
2
3
4
7
6
5
X24257
VSS
SDA
NC
NC
NC
NC
8
9
10
11
12
14
13
NC
8-Lead XBGA: Top View
S
1
SDA
S
2
SCL
VCC
VSS
S
0
WP
8
7
6
5
1
2
3
4
S
2
X24257
Characteristics subject to change without notice.
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DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
SCL
SDA
DATA STABLE
DATA
CHANGE
SCL
SDA
START BIT
STOP BIT
X24257
Characteristics subject to change without notice.
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Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
8
9
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal "1010". The next 3 bits are the
device select bits S
0
, S
1
, and S
2
. This allows up to 8
devices to share a single bus. These bits are com-
pared to the S
0
, S
1
, and S
2
device select input pins.
The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a write operation is selected. Refer to Figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
"1010" and the device select bits with the status of the
device select input pins. If the compare is not success-
ful, no acknowledge is output during the ninth clock
cycle and the device returns to the standby mode.
On power up the internal address is undefined, so the
first read or write operation must supply an address.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
The internal organization of the E
2
array is 512 pages
by 64 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
X24257
Characteristics subject to change without notice.
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Figure 4. Device Addressing
1
S
1
S
0
R/ W
DEVICE
SELECT
0
1
0
DEVICE TYPE
IDENTIFIER
SLAVE ADDRESS BYTE
D7
D2
D1
D6
D5
D4
D3
DATA BYTE
A2
A1
A0
A5
LOW ORDER WORD ADDRESS
A4
A3
WORD ADDRESS BYTE 0
*
A10
A9
A8
A14
HIGH ORDER WORD ADDRESS
A11
X24257 WORD ADDRESS BYTE 1
A13
A12
A7
A6
D0
*This bit is 0 for access to the array and 1 for access to the Control Register
S
2
WRITE OPERATIONS
Byte Write
For a write operation, the device follows "3 byte" proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
Page Write
The device is capable of a 64 byte page write opera-
tion. It is initiated in the same manner as the byte write
operation; but instead of terminating the write opera-
tion after the first data word is transferred, the master
can transmit up to sixty-three more words. The device
will respond with an acknowledge after the receipt of
each word, and then the byte address is internally
incremented by one. The page address remains con-
stant. When the counter reaches the end of the page,
it "rolls over" and goes back to the first byte of the cur-
rent page. This means that the master can write 64
bytes to the page beginning at any byte. If the master
begins writing at byte 32, and loads 64 bytes, then the
first 32 bytes are written to bytes 32 through 63, and
the last 16 words are written to bytes 0 through 31.
Afterwards, the address counter would point to byte 32.
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