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Recommend System Management
Alternative: X4163
8K
X24C08
1024 x 8 Bit
Serial EEPROM
FEATURES
2.7V to 5.5V power supply
Low power CMOS
--Active read current less than 1 mA
--Active write current less than 3 mA
Internally organized 1024 x 8
2-wire serial interface
--Bidirectional data transfer protocol
--Schmitt trigger input noise suppression
400kHz across V
CC
range
Sixteen byte page write mode
--Minimizes total write time per byte
Self-timed write cycle
--Typical write cycle time of 5 ms
High reliability
--Endurance: 1,000,000 cycles
--Data retention: 100 years
8-pin SOIC package
DESCRIPTION
The X24C08 is a CMOS 8,192 bit serial EEPROM,
internally organized 1024 x 8. The X24C08 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
The X24C08 is fabricated with Xicor's advanced
CMOS Textured Poly Floating Gate Technology.
The X24C08 utilizes Xicor's proprietary Direct Write
TM
cell providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
START
STOP
Logic
Control
Logic
Slave Address
Register
+Comparator
H.V. Generation
Timing
& Control
Word
Address
Counter
XDEC
YDEC
D
OUT
ACK
EEPROM
64 X 128
Data Register
START Cycle
(8) V
CC
R/W
Pin
(4) V
SS
(5) SDA
(6) SCL
(3) A
2
(2) A
1
(1) A
0
D
OUT
LOAD
INC
CK
(7) TEST
8
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PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
Up Resistor selection graph at the end of this data
sheet.
Address (A
0
, A
1
)
A
0
and A
1
are unused by the X24C08; however, they
must be tied to V
SS
to insure proper device operation.
Address (A
2
)
The A
2
input is used to set the appropriate bit of the
seven bit slave address. This input can be used static
or actively driven. If used statically, it must be tied to
V
SS
or V
CC
as appropriate. If actively driven, it must be
driven to V
SS
or to V
CC
.
PIN CONFIGURATION
PIN NAMES
DEVICE OPERATION
The X24C08 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24C08 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C08 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the
X24C08 to place the device into the standby power
mode after a read sequence. A stop condition can only
be issued after the transmitting device has released
the bus.
V
CC
TEST
SCL
A
0
A
1
A
2
V
SS
X24C08
SOIC
SDA
1
2
3
4
8
7
6
5
Symbol
Description
A
0
A
2
Address Inputs
SDA
Serial Data
SCL
Serial Clock
TEST
Hold at V
SS
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
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Figure 1. Data Validity
Figure 2. Definition of Start and Stop
SCL
SDA
Data Stable
Data
Change
SCL
SDA
START Bit
STOP Bit
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the
ninth clock cycle the receiver will pull the SDA line
LOW to acknowledge that it received the eight bits of
data. Refer to Figure 3.
The X24C08 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24C08 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
In the read mode the X24C08 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24C08
will continue to transmit data. If an acknowledge is not
detected, the X24C08 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24C08 to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL From
Master
Data Output
From Transmitter
Data Output
From Receiver
START
Acknowledge
1
8
9
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DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (see Figure 4). For the X24C08 this is fixed as
1010[B].
Figure 4. Slave Address
The next bit addresses a particular device. A system
could have up to two X24C08 devices on the bus (see
Figure 10). The two addresses are defined by the state
of the A2 input.
The next two bits of the slave address field are an
extension of the array's address and are concatenated
with the eight bits of address in the word address field,
providing direct access to the whole 1024 x 8 array.
The last bit of the slave address defines the operation
to be performed. When set to one a read operation is
selected; when set to zero a write operation is
selected.
Following the start condition, the X24C08 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A2
input.) Upon a correct compare the X24C08 outputs an
acknowledge on the SDA line. Depending on the state
of the R/W bit, the X24C08 will execute a read or write
operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C08 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
1024 words in the array. Upon receipt of the word
address the X24C08 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time
the X24C08 begins the internal write cycle to the non-
volatile memory. While the internal write cycle is in
progress the X24C08 inputs are disabled, and the
device will not respond to any requests from the mas-
ter. Refer to Figure 5 for the address, acknowledge and
data transfer sequence.
A2
A1
A0
R/W
Device Type
Identifier
Device
Address
0
1
0
1
High
Order Word
Address
Figure 5. Byte Write
Bus Activity:
Master
SDA Line
Bus Activity:
X24C08
S
T
A
Slave
Address
S
S
T
P
A
A
A
Word
Address
Data
O
P
R
T
C
K
C
K
C
K
Page Write
The X24C08 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte
write operation, but instead of terminating the write
cycle after the first data word is transferred, the master
can transmit up to fifteen more words. After the receipt
of each word, the X24C08 will respond with an
acknowledge.
After the receipt of each word, the four low order
address bits are internally incremented by one. The
high order six bits of the word address remain con-
stant. If the master should transmit more than sixteen
words prior to generating the stop condition, the
address counter will "roll over" and the previously writ-
ten data will be overwritten. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address,
acknowledge and data transfer sequence.
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Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host's
write operation, the X24C08 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition, followed by the
slave address for a write operation. If the X24C08 is
still busy with the write operation no ACK will be
returned. If the X24C08 has completed the write oper-
ation an ACK will be returned and the host can then
proceed with the next read or write operation. Refer to
Flow 1.
Flow 1. ACK Polling Sequence
Write Operation
Completed
Enter ACK Polling
Issue
START
Issue Slave
Address and R/W = 0
ACK
Returned?
Next
Operation
A Write?
Issue Byte
Address
PROCEED
Issue STOP
No
Yes
Yes
PROCEED
Issue STOP
No
Figure 6. Page Write
Bus Activity:
Master
SDA Line
Bus Activity:
S
T
A
Slave
Address
S
S
T
P
A
A
A
A
A
Word
Address
Data n
Data n+1
Data n+15
R
T
O
P
C
K
C
K
C
K
C
K
C
K
X24C08
Note: In this example n = xxxx 000 (B); x = 1 or 0
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READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address is set to a one. There are three basic
read operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle, or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the X24C08 contains an address counter
that maintains the address of the last word accessed,
incremented by one. Therefore, if the last access
(either a read or write) was to address n, the next read
operation would access data from address n + 1. Upon
receipt of the slave address with R/W set to one, the
X24C08 issues an acknowledge and transmits the
eight bit word. The read operation is terminated by the
master by not responding with an acknowledge and by
issuing a stop condition. Refer to Figure 7 for the
sequence of address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to
issuing the slave address with the R/W bit set to one,
the master must first perform a "dummy" write opera-
tion. The master issues the start condition, and the
slave address followed by the word address it is to
read. After the word address acknowledge, the master
immediately reissues the start condition and the slave
address with the R/W bit set to one. This will be fol-
lowed by an acknowledge from the X24C08 and then
by the eight bit word. The read operation is terminated
by the master by not responding with an acknowledge
and by issuing a stop condition. Refer to Figure 8 for
the address, acknowledge and data transfer sequence.
Figure 7. Current Address Read
Figure 8. Random Read
Bus Activity:
Master
SDA Line
Bus Activity:
X24C08
S
T
A
Slave
Address
S
S
T
P
A
Data
R
T
O
P
C
K
Bus Activity:
Master
Sda Line
Bus Activity:
X24C08
S
T
A
Slave
Address
S
S
T
P
A
A
A
Word
Address n
Slave
Address
Data n
S
T
A
S
R
T
R
T
O
P
C
K
C
K
C
K
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24C08 continues to
output data for each acknowledge received. The read
operation is terminated by the master by not responding
with an acknowledge and by issuing a stop condition.
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The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 1023) the counter "rolls over" to address 0
and the X24C08 continues to output data for each
acknowledge received. Refer to Figure 9 for the
address, acknowledge and data transfer sequence.
Figure 9. Sequential Read
Figure 10. Typical System Configuration
Address
A
A
Data n+x
S
T
P
Data n
A
Data n+1
A
Data n+2
C
K
C
K
C
K
C
K
O
P
Bus Activity:
SDA Line
Bus Activity:
X24C08
Slave
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
SDA
SCL
V
CC
Pull-up
Resistors
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................65C to +135C
Storage temperature .........................65C to +150C
Voltage on any pin with
respect to V
SS
..................................... 1.0V to +7V
D.C. output current .............................................. 5 mA
Lead temperature (soldering, 10 seconds).........300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0C
70C
Industrial
40C
+85C
Supply Voltage
Limits
X24C08-2.7
2.7V to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified.)
CAPACITANCE
T
A
= 25C, f = 1.0MHz, V
CC
= 5V
Notes:
(1) Must perform a stop command prior to measurement.
(2) V
IL
min and V
IH
max. are for reference only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Max.
l
CC1
V
CC
supply current (read)
1
mA
SCL = V
CC
x 0.1/V
CC
x 0.9 Levels @ 100 kHz,
SDA = Open, All Other Inputs = GND or
V
CC
0.3V
l
CC2
V
CC
supply current (write)
3
I
SB1
(1)
V
CC
standby current
150
A
SCL = SDA = V
CC
0.3V, All Other
Inputs = GND or V
CC
, V
CC
= 5.5V
I
SB2
(1)
V
CC
standby current
50
A
SCL = SDA = V
CC
0.3V, All Other
Inputs = GND or V
CC
, V
CC
= 3V
I
LI
Input leakage current
10
A
V
IN
= GND to V
CC
I
LO
Output leakage current
10
A
V
OUT
= GND to V
CC
V
lL
(2)
Input low voltage
1.0
V
CC
x 0.3
V
V
IH
(2)
Input high voltage
V
CC
x 0.7 V
CC
+ 0.5
V
V
OL
Output low voltage
0.4
V
I
OL
= 3 mA
Symbol
Test
Max.
Unit
Conditions
C
I/O
(3)
Input/output capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(3)
Input capacitance (A
0
, A
1
, A
2
, SCL)
6
pF
V
IN
= 0V
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A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
I/O timing levels
V
CC
x 0.5
1533
Output
100pF
5.0V
A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
t
SCL
SCL clock frequency
0
100
kHz
t
I
Noise suppression time constant at SCL, SDA inputs
100
ns
t
AA
SCL low to SDA data out valid
0.3
3.5
s
t
BUF
Time the bus must be free before a new transmission can start
4.7
s
t
HD:STA
Start condition hold time
4.0
s
t
LOW
Clock low period
4.7
s
t
HIGH
Clock high period
4.0
s
t
SU:STA
Start condition setup time
4.7
s
t
HD:DAT
Data in hold time
0
s
t
SU:DAT
Data in setup time
250
ns
t
R
SDA and SCL rise time
1
s
t
F
SDA and SCL fall time
300
ns
t
SU:STO
Stop condition setup time
4.7
s
t
DH
Data out hold time
300
ns
Symbol
Parameter
Max.
Unit
t
PUR
(4)
Power-Up to read operation
1
ms
t
PUW
(4)
Power-Up to write operation
5
ms
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Bus Timing
Note:
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
WRITE CYCLE LIMITS
Notes: (5) Typical values are for T
A
= 25C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/pro-
gram cycle. During the write cycle, the X24C08 bus interface circuits are disabled, SDA is allowed to remain high,
and the device does not respond to its slave address.
Write Cycle Timing
Symbol
Parameter
Min.
Typ.
(5)
Max.
Unit
t
WR
(6)
Write Cycle Time
5
10
ms
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
SU:STO
t
R
t
BUF
SCL
SDA IN
SDA OUT
t
DH
t
AA
t
F
t
HIGH
SDA
8
th
Bit
Word n
ACK
t
WR
STOP
Condition
START
Condition
X24C08
Address
SCL
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Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
120
100
80
40
60
20
20
40
60
80 100 120
Bus Capacitance (pF)
Min.
Resistance
Max.
Resistance
R
MAX
=
C
BUS
t
R
Max.
R
MIN
=
I
OL
Min.
V
CC
Max.
= 1.8K
0
0
Resistance (K
)
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"
Typical
0.030"
Typical
8 Places
FOOTPRINT
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LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
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Ordering Information
Park Mark Convention
Device
V
CC
Limits
2.7 = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0C to +70C
I = Industrial = 40C to +85C
Package
S8 = 8-Lead SOIC
X24C08
P
-V
T
X24C08 X
X
S8 = 8-Lead SOIC
F = 2.7V to 5.5V, 0C to +70C
G = 2.7V to 5.5V, 40C to +85C
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