REV 1.1.1 12/8/00
Characteristics subject to change without notice.
1 of 14
www.xicor.com
Recommended System Management
Alternative: X4163
For a more
Integrated Solution use
Xicor System Management Products
BLOCK DIAGRAM
START
STOP
Logic
Slave Address
Register
+Comparator
H.V. Generation
Timing
& Control
Word
Address
Counter
X Dec
Y Dec
D
OUT
128 X 128
Data Register
R/W
PIN
(6) SCL
(3) A2
D
OUT
LOAD
INC
CK
8
(7) TEST
Control
Logic
ACK
EEPROM
START Cycle
(8) V
CC
(4) V
SS
(5) SDA
(2) A1
(1) A0
16K
X24C16
2048 x 8 Bit
Serial EEPROM
FEATURES
2.7V to 5.5V power supply
Low power CMOS
--Active read current less than 1 mA
--Active write current less than 3 mA
--Standby current less than 1A
Internally organized 2048 x 8
2-wire serial interface
--Bidirectional data transfer protocol
Sixteen byte page write mode
--Minimizes total write time per byte
Self-timed write cycle
--Typical write cycle time of 5 ms
High reliability
--Endurance: 1,000,000 cycles
--Data retention: 100 years
Packages
--14-lead TSSOP
--8-lead SOIC
DESCRIPTION
The X24C16 is a CMOS 16,384 bit serial EEPROM,
internally organized 2048 X 8. The X24C16 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
The X24C16 is fabricated with Xicor's advanced
CMOS Textured Poly Floating Gate Technology.
The X24C16 utilizes Xicor's proprietary Direct Write
TM
cell providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
X24C16
Characteristics subject to change without notice.
2 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
Up Resistor selection graph at the end of this data
sheet.
Address (A
0
, A
1
, A
2
)
The A
0
, A
1
and A
2
inputs are unused by the X24C16,
however, they must be tied to V
SS
to insure proper
device operation.
PIN NAMES
PIN CONFIGURATION
DEVICE OPERATION
The X24C16 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master, and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24C16 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Symbol
Description
A
0
A
2
Address Inputs
SDA
Serial Data
SCL
Serial Clock
TEST
Hold at V
SS
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
A
0
A
1
A
2
V
SS
1
2
3
4
8
7
6
5
V
CC
TEST
SCL
SDA
X24C16
8-Lead SOIC
A
0
A
1
NC
NC
1
2
3
4
14
13
12
11
V
CC
TEST
NC
NC
X24C16
14-Lead TSSOP
NC
A
2
V
SS
5
6
7
10
9
8
NC
SCL
SDA
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
X24C16
Characteristics subject to change without notice.
3 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C16 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the
X24C16 to place the device into the standby power
mode after a read sequence. A stop condition can only
be issued after the transmitting device has released
the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
The X24C16 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24C16 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
In the read mode the X24C16 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24C16
will continue to transmit data. If an acknowledge is not
detected, the X24C16 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24C16 to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response from Receiver
SCL from
Master
Data Output
from Transmitter
1
8
9
from Receiver
START
Acknowledge
Data Output
X24C16
Characteristics subject to change without notice.
4 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (see Figure 4). For the X24C16 this is fixed as
1010[B].
Figure 4. Slave Addressing
The next three bits of the slave address field are the
bank select bits. They are used by the host to toggle
between the eight 256 x 8 banks of memory. These
are, in effect, the most significant bits for the word
address.
The next three bits of the slave address are an exten-
sion of the array's address and are concatenated with
the eight bits of address in the word address field, pro-
viding direct access to the whole 2048 x 8 array.
Following the start condition, the X24C16 monitors the
SDA bus, comparing the slave address being transmit-
ted with its slave address (device type). Upon a correct
compare, the X24C16 outputs an acknowledge on the
SDA line. Depending on the state of the R/W bit, the
X24C16 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C16 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 2048 words in the array. Upon receipt of the word
address the X24C16 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time
the X24C16 begins the internal write cycle to the non-
volatile memory. While the internal write cycle is in
progress the X24C16 inputs are disabled, and the
device will not respond to any requests from the mas-
ter. Refer to Figure 5 for the address, acknowledge and
data transfer sequence.
1
A
1
A
0
R/W
Word Address
0
1
0
A
2
Device Type
Identifier
High Order
Figure 5. Byte Write
Figure 6. Page Write
Bus Activity:
Master
SDA Bus
Bus Activity:
X24C16
S
T
A
R
T
Slave
Address
S
T
O
P
A
C
K
A
C
K
A
C
K
Word Address
Data
P
S
S
T
A
R
T
Slave
Address
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data n + 1
Word
Address (n)
Data n
S
P
Data n + 15
Note: In this example n = xxxx 000 (B); x = 1 or 0
Bus Activity:
Master
SDA Line
Bus Activity:
X24C16
X24C16
Characteristics subject to change without notice.
5 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
Page Write
The X24C16 is capable of a 16 byte page write opera-
tion. It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle after
the first data word is transferred, the master can trans-
mit up to fifteen more words. After the receipt of each
word, the X24C16 will respond with an acknowledge.
After the receipt of each word, the four low order
address bits are internally incremented by one. The
high order seven bits of the address remain constant. If
the master should transmit more than sixteen words
prior to generating the stop condition, the address
counter will "roll over" and the previously written data
will be overwritten. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. Refer to Figure 6 for the address, acknowledge
and data transfer sequence.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host's
write operation, the X24C16 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the
slave address for a write operation. If the X24C16 is
still busy with the write operation, no ACK will be
returned. If the X24C16 has completed the write oper-
ation, an ACK will be returned and the host can then
proceed with the next read or write operation. Refer to
Flow 1.
Flow 1. ACK Polling Sequence
Write Operation
Completed
Enter ACK Polling
Issue
START
Issue Slave
Address and R/W = 0
ACK
Returned?
Next
Operation
a Write?
Issue Byte
Address
PROCEED
Issue STOP
NO
YES
YES
PROCEED
Issue STOP
NO
X24C16
Characteristics subject to change without notice.
6 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address is set to a one. There are three basic
read operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle, or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Current Address Read
Internally, the X24C16 contains an address counter
that maintains the address of the last word accessed,
incremented by one. Therefore, if the last access
(either a read or write) was to address n, the next read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the X24C16 issues an acknowledge and transmits the
eight bit word. The read operation is terminated by the
master by not responding with an acknowledge, and
issuing a stop condition. Refer to Figure 7 for the
sequence of address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to
issuing the slave address with the R/W bit set to one,
the master must first perform a "dummy" write opera-
tion. The master issues the start condition, and the
slave address followed by the word address it is to read.
After the word address acknowledge, the master imme-
diately reissues the start condition and the slave
address with the R/W bit set to one. This will be followed
by an acknowledge from the X24C16 and then by the
eight bit word. The read operation is terminated by the
master by not responding with an acknowledge, and
issuing a stop condition. Refer to Figure 8 for the
address, acknowledge and data transfer sequence.
Figure 7. Current Address Read
S
T
A
R
T
Slave
Address
A
C
K
S
Bus Activity:
Master
SDA Line
Bus Activity:
X24C16
Data
S
T
O
P
P
Figure 8. Random Read
S
T
A
R
T
Slave
Address
A
C
K
A
C
K
S
S
T
A
R
T
Slave
Address
Word
Address n
S
A
C
K
Data n
S
T
O
P
P
Bus Activity:
Master
SDA Line
Bus Activity:
X24C16
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24C16 continues to
output data for each acknowledge received. The read
operation is terminated by the master by not respond-
ing with an acknowledge, and then issuing a stop con-
dition.
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 2047), the counter "rolls over" to 0 and the
X24C16 continues to output data for each acknowl-
edge received. Refer to Figure 9 for the address,
acknowledge and data transfer sequence.
X24C16
Characteristics subject to change without notice.
7 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
Figure 9. Sequential Read
Figure 10. Typical System Configuration
Slave
Address
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data n
Data n+1
Data n+2
Data n+x
P
Bus Activity:
Master
SDA Line
Bus Activity:
X24C16
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Pull-Up
Resistors
SDA
SCL
V
CC
X24C16
Characteristics subject to change without notice.
8 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ........................65 to +135
C
Storage temperature .............................65 to +150
C
Voltage on any pin with respect to V
SS
.......1V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300
C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70C
Industrial
40
C
+85C
Supply Voltage
Limits
X24C162.5
2.5V to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
CAPACITANCE
T
A
= +25C, f = 1.0 MHz, V
CC
= 5V
Notes: (1) Must perform a stop command prior to measurement.
(2) V
IL
min. and V
IH
max. are for reference only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Max.
I
CC1
V
CC
supply current (read)
1
mA
SCL = V
CC
X 0.1/V
CC
X 0.9 Levels @ 100 kHz,
SDA = Open, All Other Inputs =
GND
or
V
CC
0.3V
I
CC2
V
CC
supply current (write)
3
I
SB1
(1)
V
CC
standby current
X24C16
150
A
SCL = SDA = V
CC
0.3V, All Other Inputs =
GND
or V
CC
, V
CC
= 5V
I
SB2
(1)
V
CC
standby current
X24C16-3
50
A
SCL = SDA = V
CC
0.3V, All Other Inputs =
GND
or V
CC
, V
CC
= 3.3V 10%
I
SB3
(1)
V
CC
standby current
X24C16-2.5
1
A
SCL = SDA = V
CC
0.3V, All Other Inputs =
GND
or V
CC
, V
CC
= 2.5V
I
SB4
(1)
V
CC
standby current
X24C16-1.8
1
A
SCL = SDA = V
CC
0.3V, All Other Inputs =
GND
or V
CC
, V
CC
= 1.8V
I
LI
Input leakage current
10
A
V
IN
=
GND
to V
CC
I
LO
Output leakage current
10
A
V
OUT
=
GND
to V
CC
V
lL
(2)
Input low voltage
1.0
V
CC
x 0.3
V
V
IH
(2)
Input high voltage
V
CC
x 0.7 V
CC
+ 0.5
V
V
OL
Output low voltage
0.4
V
I
OL
= 3mA
Symbol
Parameter
Max.
Unit
Test Conditions
C
I/O
(3)
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(3)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
6
pF
V
IN
= 0V
X24C16
Characteristics subject to change without notice.
9 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing levels
V
CC
X 0.5
5V
1533
100pF
Output
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
POWER-UP TIMING
(4)
Note:
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
Symbol
Parameter
Min.
Max.
Unit
f
SCL
SCL clock frequency
0
400
kHz
T
I
Noise suppression time constant at SCL, SDA inputs
100
ns
t
AA
SCL low to SDA data out valid
0.3
3.5
s
t
BUF
Time the bus must be free before a new transmission can start
4.7
s
t
HD:STA
Start condition hold time
4.0
s
t
LOW
Clock low period
4.7
s
t
HIGH
Clock high period
4.0
s
t
SU:STA
Start condition setup time (for a repeated start condition)
4.7
s
t
HD:DAT
Data in hold time
0
s
t
SU:DAT
Data in setup time
250
ns
t
R
SDA and SCL rise time
1
s
t
F
SDA and SCL fall time
300
ns
t
SU:STO
Stop condition setup time
4.7
s
t
DH
Data out hold time
300
ns
Symbol
Parameter
Max.
Unit
t
PUR
Power-up to read operation
1
ms
t
PUW
Power-up to write operation
5
ms
X24C16
Characteristics subject to change without notice.
10 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
Bus Timing
Write Cycle Limits
Notes: (5) Typical values are for T
A
= 25C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24C16 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Bus Timing
Symbol
Parameter
Min.
Typ.
(5)
Max.
Unit
t
WC
(6)
Write Cycle Time
5
10
ms
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
SU:STO
t
R
t
BUF
SCL
SDA IN
SDA OUT
t
DH
t
AA
t
F
t
HIGH
SCL
SDA
8
th
Bit
Word n
ACK
t
WC
STOP
Condition
START
Condition
X24X16 Address
X24C16
Characteristics subject to change without notice.
11 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
120
100
80
40
60
20
20
40
60
80 100 120
0
0
Resistance (K
)
Bus Capacitance (pF)
Min.
Resistance
Max.
Resistance
R
MAX.
=
C
BUS
t
R
R
Min.
=
I
OL Min.
V
CC Max.
=1.8K
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X24C16
Characteristics subject to change without notice.
12 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"
Typical
0.030"
Typical
8 Places
FOOTPRINT
X24C16
Characteristics subject to change without notice.
13 of 14
REV 1.1.1 12/8/00
www.xicor.com
For a more
Integrated Solution use
Xicor System Management Products
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
For a more
Integrated Solution use
Xicor System Management Products
X24C16
Characteristics subject to change without notice.
14 of 14
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
REV 1.1.1 12/8/00
www.xicor.com
Ordering Information
Part Mark Convention
Device
X24C16
X
X
-X
V
CC
Range
2.7 = 2.7V to 5.5V
Temperature Range
Package
S8 = 8-Lead SOIC
Blank = Commercial = 0C to +70C
I = 40
C to +85
C
V14 = 14-Lead TSSOP
X24C16
X
X
S8 = 8-Lead SOIC
AB = 2.7V to 5.5V, 0C to +70C
AD = 2.7V to 5.5V, 40C to +85C
V14 = 14-Lead TSSOP
PDF 
ZIP