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2K
X25020
256 x 8 Bit
SPI Serial EEPROM with Block Lock
TM
Protection
FEATURES
2MHz clock rate
SPI modes (0,0 & 1,1)
256 X 8 bits
--16-byte page mode
Low power CMOS
--10A standby current
--3mA active write current
2.7V To 5.5V power supply
Block lock protection
--Protect 1/4, 1/2 or all of EEPROM array
Built-in inadvertent write protection
--Power-up/power-down protection circuitry
--Write latch
--Write protect pin
Self-timed write cycle
--5ms write cycle time (typical)
High reliability
--Endurance: 1,000,000 cycles per byte
--Data retention: 100 years
--ESD protection: 2000V on all pins
8-lead SOIC Package
DESCRIPTION
The X25020 is a CMOS 2048-bit serial EEPROM,
internally organized as 256 x 8. The X25020 features a
serial interface and software protocol, allowing opera-
tion on a simple three-wire bus. The bus signals are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled
through a chip select (CS) input, allowing any number
of devices to share the same bus.
The X25020 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25020 will ignore transitions on
its inputs, thus allowing the host to service higher pri-
ority interrupts. The WP input can be used as a hard-
wire input to the X25020 (disabling all write attempts),
thus providing a mechanism for limiting end user capa-
bility of altering the memory.
The X25020 utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 1,000,000
cycles per byte and a minimum data retention of 100
years.
BLOCK DIAGRAM
Command
Decode
And
Control
Logic
Write
Control
and
Timing
Logic
Write
Protect
Logic
X Decode
Logic
256 Byte
Array
4 X 128
Y Decode
Data Register
4 X 128
16 X 128
SO
SI
SCK
CS
HOLD
WP
4
4
16
Status
Register
16
8
Direct Write
TM
and Block Lock
TM
Protection is a trademark of Xicor, Inc.
X25020
Characteristics subject to change without notice.
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PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25020 is deselected and the
SO pin is at high impedance; unless an internal write
operation is underway, the X25020 will be in the
standby power mode. CS LOW enables the X25020,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25020 are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvol-
atile writes operate normally. WP going LOW while CS
is still LOW will interrupt a write to the X25020. If the
internal write cycle has already been initiated, WP
going LOW will have no affect on a write.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
PIN CONFIGURATION
PIN NAMES
PRINCIPLES OF OPERATION
The X25020 is a 256 x 8 EEPROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25020 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and
WP inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25020 into a "PAUSE" condition. After releasing
HOLD, the X25020 will resume operation from the
point when HOLD was first asserted.
Symbol
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
HOLD
Hold Input
SOIC
CS
SO
WP
V
SS
V
CC
HOLD
SCK
SI
X25020
1
2
3
4
8
7
6
5
X25020
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Write Enable Latch
The X25020 contains a "write enable" latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
BP0 and BP1 are set by the WRSR instruction. WEL
and WIP are read-only and automatically set by other
operations.
The Write-In-Process (WIP) bit indicates whether the
X25020 is busy with a write operation. When set to a
"1", a write is in progress, when set to a "0", no write is
in progress. During a write, all other bits are set to "1".
The Write Enable Latch (WEL) bit indicates the status
of the "write enable" latch. When set to a "1", the latch
is set, when set to a "0", the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25020 is divided into four 512-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected seg-
ments. The partitioning is controlled as illustrated
below.
7
6
5
4
3
2
1
0
0
0
0
0
BP1
BP0
WEL
WIP
Status Register Bits
Array Addresses Protected
BP1
BP0
0
0
None
0
1
$C0$FF
1
0
$80$FF
1
1
$00$FF
Table 1. Instruction Set
Notes:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name Instruction Format*
Operation
WREN
0000 0110
Set the write enable latch (enable write operations)
WRDI
0000 0100
Reset the write enable latch (disable write operations)
RDSR
0000 0101
Read status register
WRSR
0000 0001
Write status register
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address (1 to 32 bytes)
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25020, followed by
the 8-bit address. After the read opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached ($FF), the address counter rolls over
to address $00, allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS HIGH. Refer to the read EEPROM array operation
sequence illustrated in Figure 1.
X25020
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To read the status register CS line is first pulled LOW
to select the device, followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register are shifted out
on the SO line. Figure 2 illustrates the read status reg-
ister sequence.
Write Sequence
Prior to any attempt to write data into the X25020, the
"write enable" latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25020. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
To write data to the EEPROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and remain
LOW for the duration of the operation. The host may
continue to write up to 16 bytes of data to the X25020.
The only restriction is that the 16 bytes must reside on
the same page. If the address counter reaches the end
of the page and the clock continues, the counter will "roll
over" to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time, the write operation will not be completed. Refer to
Figures 4 and 5 for a detailed illustration of the write
sequences and time frames in which CS going HIGH
are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be "0". Figure 6 illustrates this sequence.
While the write is in progress following a status register
or EEPROM write sequence, the status register may
be read to check the WIP bit. During this time the WIP
bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at V
IH
) under normal
operation. If a data transfer is to be interrupted, HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW, and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25020 powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The "write enable" latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The "write enable" latch is reset upon power-up.
A WREN instruction must be issued to set the "write
enable" latch.
CS must come HIGH at the proper clock count in
order to start a write cycle.
X25020
Characteristics subject to change without notice.
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Figure 1. Read EEPROM Array Operation Sequence
Figure 2. Read Status Register Operation Sequence
Figure 3. Write Enable Latch Sequence
10 11 12 13 14 15 16 17 18 19 20 21 22
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
Byte Address
2
3
4
5
6
7
8
9
1
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
0
1
2
3
4
5
6
7
CS
SI
SCK
High Impedance
SO
X25020
Characteristics subject to change without notice.
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Figure 4. Byte Write Operation Sequence
Figure 5. Page Write Operation Sequence
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
SCK
SI
SO
High Impedance
Instruction
Byte Address
Data Byte
2
3
4
5
6
7
8
9
1
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
CS
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
Instruction
Byte Address
Data Byte 1
CS
40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte 4
2
3
4
5
6
7
8
9
1
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
X25020
Characteristics subject to change without notice.
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Figure 6. Write Status Register Operation Sequence
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Instruction
Data Byte
7
6
5
4
3
2
1
0
10 11 12 13 14 15
X25020
Characteristics subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ...................65C to +135C
Storage temperature ........................65C to +150C
Voltage on any pin with respect to V
SS
....... 1V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0C
+70C
Industrial
40C
+85C
Supply Voltage
Limits
X25020-2.7
2.7 to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
POWER-UP TIMING
CAPACITANCE
T
A
= +25C, F = 1MHZ, V
CC
= 5V.
Notes:
(1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Max.
I
CC
V
CC
supply current (active)
3
mA
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 1MHz,
SO = Open
I
SB
V
CC
supply current (standby)
10
A
CS = V
CC
, V
IN
= V
SS
or V
CC
0.3V
I
LI
Input leakage current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output leakage current
10
A
V
OUT
= V
SS
to V
CC
V
IL
(1)
Input LOW voltage
0.5
V
CC
x 0.3
V
V
IH
(1)
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL
Output LOW voltage
0.4
V
I
OL
= 2mA
V
OH
Output HIGH voltage
V
CC
0.8
V
I
OH
= 1mA
Symbol
Parameter Min.
Max.
Unit
t
PUR
(2)
Power-up to read operation
1
ms
t
PUW
(2)
Power-up to write operation
5
ms
Symbol
Test
Max.
Unit
Conditions
C
OUT
(2)
Output capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
(2)
Input capacitance (SCK, SI, CS, WP, HOLD)
6
pF
V
IN
= 0V
X25020
Characteristics subject to change without notice.
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EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
CC
A.C. TEST CONDITIONS
5V
2.16K
3.07K
Output
100pF
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x 0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Data Output Timing
Notes: (3) Parameter is tested on a sample basis only.
(4) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Symbol Parameter
Min.
Max.
Unit
f
SCK
Clock frequency
0
2
MHz
t
CYC
Cycle time
1000
ns
t
LEAD
CS lead time
500
ns
t
LAG
CS lag time
500
ns
t
WH
Clock HIGH time
400
ns
t
WL
Clock LOW time
400
ns
t
SU
Data setup time
100
ns
t
H
Data hold time
100
ns
t
RI
Data in rise time
2
s
t
FI
Data in Fall time
2
s
t
HD
HOLD setup time
200
ns
t
CD
HOLD hold time
200
ns
t
CS
CS deselect time
500
ns
t
WC
(4)
Write cycle time
10
ms
Symbol Parameter
Min.
Max.
Unit
f
SCK
Clock frequency
0
1
MHz
t
DIS
Output disable time
500
ns
t
V
Output valid from clock LOW
360
ns
t
HO
Output hold time
0
ns
t
RO
(3)
Output rise time
300
ns
t
FO
(3)
Output fall time
300
ns
t
LZ
HOLD HIGH to output in low Z
100
ns
t
HZ
HOLD LOW to output in high Z
100
ns
X25020
Characteristics subject to change without notice.
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Serial Output Timing
Serial Input Timing
SCK
CS
SO
SI
MSB Out
MSB1 Out
LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
High Impedance
X25020
Characteristics subject to change without notice.
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Hold Timing
SYMBOL TABLE
SCK
CS
SI
SO
t
HD
t
LZ
HOLD
t
CD
t
HZ
t
CD
t
HD
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X25020
Characteristics subject to change without notice.
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PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"
Typical
0.030"
Typical
8 Places
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X25020
Characteristics subject to change without notice.
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LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
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Ordering Information
Part Mark Convention
X25020
P -V
Device
V
CC
Limits
2.7V = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0C to +70C
I = Industrial = 40C to +85C
Package
S = 8-Lead SOIC
T
Blank = 8-Lead SOIC
F = 2.7V to 5.5V, 0C to +70C
G = 2.7V to 5.5V, 40C to +85C
X25020
X
X
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