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Recommended System Management
Alternative: X5083
8K
X25097
1024 x 8 Bit
5MHz Low Power SPI Serial EEPROM with IDLock
TM
Memory
FEATURES
5MHz clock rate
IDLock memory
--IDLock first or last page, any 1/4 or lower 1/2 of
EEPROM array
Low power CMOS
--<1A standby current
--<3mA active current during write
--<400A active current during read
2.7V-5.5V operation
Built-in inadvertent write protection
--Power-up/power-down protection circuitry
--Write enable latch
--Write protect pin
SPI modes (0,0 & 1,1)
1024 x 8 bits
--16-byte page mode
Self-timed write cycle
--5ms write cycle time (typical)
High reliability
--Endurance: 1,000,000 cycles/byte
--Data retention: 100 years
--ESD: 2000V on all pins
8-lead MSOP package
8-lead TSSOP package
8-lead SOIC package
DESCRIPTION
The X25097 is a CMOS 8K-bit serial EEPROM, inter-
nally organized as 1024 x 8. The X25097 features a
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data
in different portions of the EEPROM memory space,
ranging from as little as one page to as much as 1/2 of
the total array. The X25097 also features a WP pin that
can be used for hardwire protection of the part, dis-
abling all write attempts, as well as a Write Enable
Latch that must be set before a write operation can be
initiated.
The X25097 utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 1,000,000
cycles per byte and a minimum data retention of 100
years.
BLOCK DIAGRAM
Command
Decode
and
Control
Logic
Write Control Logic
Data Register
Y Decode Logic
X
Decode
Logic
High Voltage
Control
8K EERPM
Array
(1024 x 8)
SO
SI
SCK
CS
WP
8
16
64
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PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
It should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
When CS is HIGH, the X25097 is deselected and the
SO output pin is at high impedance, and unless an
internal write operation is underway, the X25097 will be
in the standby power mode. CS LOW enables the
X25097, placing it in the active power mode.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25097 are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvol-
atile writes operate normally. WP going LOW while CS
is still LOW will interrupt a write to the X25097. If the
internal write cycle has already been initiated, WP
going low will have no affect on this write.
PIN NAMES
PIN CONFIGURATION
PRINCIPLES OF OPERATION
The X25097 is a 1024 x 8 EEPROM designed to inter-
face directly with the synchronous Serial Peripheral
Interface (SPI) of many popular microcontroller families.
Symbol
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
SCK
SI
V
SS
WP
NC
V
CC
CS
SO
8-Lead TSSOP
V
CC
NC
SCK
SI
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
8-Lead SOIC
X25097
X25097
1
2
3
4
8
7
6
5
V
CC
NC
SI
SCK
SO
CS
V
SS
WP
8-Lead MSOP
X25057
1
2
3
4
8
7
6
5
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The X25097 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW and the
WP input must be HIGH during the entire operation.
Table 1
contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock, and then start it again to resume opera-
tions where left off.
Write Enable Latch
The X25097 contains a "Write Enable" latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 4). This latch is
automatically reset upon a power-up condition and
after the completion of a byte or page write cycle.
IDLock Memory
Xicor's IDLock Memory provides a flexible mechanism
to store and lock system ID and parametric informa-
tion. There are seven distinct IDLock Memory areas
within the array which vary in size from one page to as
much as half of the entire array. These areas and asso-
ciated address ranges are IDLocked by writing the
appropriate two byte IDLock instruction to the device
as described in Table 1 and Figure 7. Once an IDLock
instruction has been completed, that IDLock setup is
held in a nonvolatile Status Register (Figure 1) until the
next IDLock instruction is issued. The sections of the
memory array that are IDLocked can be read (but not
written) until IDLock Protection is removed or changed.
Table 1. Status Register/IDLock Protection Byte
Note:
Bits [7:3] specified to be "0's"
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25097, followed by
the 16-bit address, of which the last 10 bits are used
(bits [15:10] specified to be zeroes). After the READ
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO
line. The data stored in memory at the next address can
be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(03FFh), the address counter rolls over to address
0000h, allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
HIGH. Refer to the Read Operation Sequence illus-
trated in Figure 2.
Read Status Operation
If there is not a nonvolatile write in progress, the Read
Status instruction returns the ID Lock byte from the
Status Register which contains the ID Lock bits IDL2-
IDL0 (Figure 1). The ID Lock bits define the ID Lock
condition (Figure 1/Table1). The other bits are reserved
and will return `0' when read. See Figure 3.
If a nonvolatile write is in progress, the Read Status
Instruction returns a HIGH on SO. When the nonvola-
tile write cycle is completed, the status register data is
read out.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is
clocked, the pointer to the status register is also
clocked, even though the SO pin shows the status of
the nonvolatile write operation (See Figure 3).
Write Sequence
Prior to any attempt to write data into the X25097, the
"Write Enable" latch must first be set by issuing the
WREN instruction (See Table 1 and Figure 4). CS is
first taken LOW. Then the WREN instruction is clocked
into the X25097. After all eight bits of the instruction
are transmitted, CS must then be taken HIGH. If the
user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write
operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction, followed by the 16
bit address and the data to be written. Only the last 10
bits of the address are used and bits [15:10] are speci-
fied to be zeroes. This is minimally a thirty-two clock
operation. CS must go LOW and remain LOW for the
duration of the operation. The host may continue to
write up to 16 bytes of data to the X25097. The only
7
6
5
4
3
2
1
0
0
0
0
0
0
IDL2
IDL1
IDL0
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restriction is the 16 bytes must reside on the same
page. If the address counter reaches the end of the
page and the clock continues, the counter will "roll
over" to the first address of the page and overwrite any
data that may have been previously written.
For a byte or page write operation to be completed, CS
can only be brought HIGH after bit 0 of the last data
byte to be written is clocked in. If it is brought HIGH at
any other time, the write operation will not be com-
pleted. Refer to Figures 5 and 6 for detailed illustration
of the write sequences and time frames in which CS
going HIGH are valid.
IDLock Operation
Prior to any attempt to perform an IDLock Operation,
the WREN instruction must first be issued. This instruc-
tion sets the "Write Enable" latch and allows the part to
respond to an IDLock sequence (Figure 7). The IDLock
instruction follows and consists of one command byte
followed by one IDLock byte (See Figure 1). This byte
contains the IDLock bits IDL2-IDL0. The rest of the bits
[7:3] are unused and must be written as zeroes. Bring-
ing CS HIGH after the two byte IDLock instruction, ini-
tiates a nonvolatile write to the Status Register. Writing
more than one byte to the Status Register will over-
write the previously written IDLock byte. See Table 1.
Operational Notes
The X25097 powers up in the following state:
The device is in the low power, standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is at high impedance.
The "Write Enable" latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The "Write Enable" latch is reset upon power-up.
A WREN instruction must be issued to set the "Write
Enable" latch.
CS must come HIGH at the proper clock count in
order to start a write cycle.
Table 2. Instruction Set and Block Lock Protection Byte Definition
Note:
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
Instruction Format*
Instruction Name and Operation
0000 0110
WREN: Set the write enable latch (write enable operation)
0000 0100
WRDI: Reset the write enable latch (write disable operation)
0000 0001
IDLock Instruction--followed by:
IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h>None of the Array
0000 0001 --->IDLock Q1: 0000h-00FFh--->Lower Quadrant (Q1)
0000 0010 --->IDLock Q2: 0100h-01FFh--->Q2
0000 0011 --->IDLock Q3: 0200h-02FFh--->Q3
0000 0100 --->IDLock Q4: 0300h-03FFh--->Upper Quadrant (Q4)
0000 0101 --->IDLock H1: 0000h-01FFh--->Lower Half of the Array (H1)
0000 0110 --->IDLock P0: 0000h-000Fh--->Lower Page (P0)
0000 0111 --->IDLock Pn: 03F0h-03FFh--->Upper Page (Pn)
0000 0101
READ STATUS: Reads IDLock & write in progress status on SO pin
0000 0010
WRITE: Write operation followed by address and data
0000 0011
READ: Read operation followed by address
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Figure 1. Read Operation Sequence
Figure 2. Read Status Operation Sequence
Figure 3. WREN/WRDI Sequence
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Read Instruction
(1 Byte)
Byte Address (2 Byte)
Data Out
15 14
3
2
1
0
20 21 22 23 24 25 26 27 28 29 30
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
CS
SCK
SI
SO
Nonvolatile Write in Progress
Read Status
Instruction
I
SO High During
Nonvolatile
Write Cycle
SO = Status Reg Bit
When No Nonvolatile
Write Cycle
...
...
...
D
L
2
I
D
L
1
I
D
L
0
0
1
2
3
4
5
6
7
CS
SI
SCK
High Impedance
SO
Instruction
(1 Byte)
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Figure 4. Byte Write Operation Sequence
Figure 5. Page Write Operation Sequence
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Write Instruction
(1 Byte)
Byte Address (2 Byte)
Data Byte
15 14
3
2
1
0
20
21 22 23 24 25 26 27 28 29 30 31
7
6
5
4
3
2
1
0
32 33 34 35 36 37 38 39
SCK
SI
CS
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
Program
Instruction
Byte Address
(2 Byte)
7
6
5
4
3
2
1
0
CS
40 41 42 43 44 45 46 47
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
15 14 13
3
2
1
0
20 21 22 23 24 25 26 27 28 29 30 31
6
5
4
3
2
1
0
Data Byte 16
Data Byte 1
146
145
147
149
148
150
151
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Figure 6. IDLock Operation Sequence
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
IDLock
10 11 12 13 14 15
IDLock
Byte
0
0
0
0
0
Instruction
I
D
L
2
I
D
L
1
I
D
L
0
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................65C to +135C
Storage temperature .........................65C to +150C
Voltage on any pin with
respect to V
SS
......................................... 1V to +7V
D.C. output current ............................................... 5mA
Lead Temperature
(soldering, 10 seconds) ..................................300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Supply Voltage
Limits
X25097-2.7
2.7V to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
POWER-UP TIMING
Notes:
(1) V
IL
Min. and V
IH
Max. are for reference only and are not 100% tested.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Max.
I
CC1
V
CC
supply current (write)
3
mA
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 5MHz,
SO = Open, CS =
V
SS
I
CC2
V
CC
supply current (read)
400
A
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 5MHz,
SO = Open, CS =
V
SS
I
SB
V
CC
supply current (standby)
1
A
CS = V
CC
, V
IN
=
V
SS
or V
CC
I
LI
Input leakage current
10
A
V
IN
=
V
SS
to V
CC
I
LO
Output leakage current
10
A
V
OUT
=
V
SS
to V
CC
V
IL
(1)
Input LOW voltage
0.5
V
CC
x 0.3
V
V
IH
(1)
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output LOW voltage
0.4
V
V
CC
> 3.3V, I
OL
= 2.1mA
V
OL2
Output LOW voltage
0.4
V
2V < V
CC
3.3V, I
OL
= 1mA
V
OL3
Output LOW voltage
0.4
V
V
CC
2V, I
OL
= 0.5mA
V
OH1
Output HIGH voltage
V
CC
0.8
V
V
CC
> 3.3V, I
OH
= -1.0mA
V
OH2
Output HIGH voltage
V
CC
0.4
V
2V < V
CC
3.3V, I
OH
= -0.4mA
V
OH3
Output HIGH voltage
V
CC
0.2
V
V
CC
2V, I
OH
= -0.25mA
Symbol
Parameter
Min.
Max.
Unit
t
PUR
(2)
Power-up to read operation
1
ms
t
PUW
(2)
Power-up to write operation
5
ms
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CAPACITANCE T
A
= +25C, f = 1MHz, V
CC
= 5.0V
Note:
(3) This parameter is periodically sampled and not 100% tested.
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Data Input Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Data Output Timing
Note:
(5) t
WC
is the time from the rising edge of tCS after a valid write sequence has been sent to the end of the self-timed internal nonvola-
tile write cycle.
Symbol
Parameter
Max.
Unit
Conditions
C
OUT
(3)
Output Capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
(3)
Input Capacitance (SCK, SI, CS, WP)
6
pF
V
IN
= 0V
Symbol
Parameter
Voltage
Min.
Max.
Unit
f
SCK
Clock frequency
2.7V5.5V
0
5
MHz
t
CYC
Cycle time
2.7V5.5V
200
ns
t
LEAD
CS lead time
2.7V5.5V
100
ns
t
LAG
CS lag time
2.7V5.5V
100
ns
t
WH
Clock HIGH time
2.7V5.5V
80
ns
t
WL
Clock LOW time
2.7V5.5V
80
ns
t
SU
Data setup time
20
ns
t
H
Data hold time
20
ns
t
RI
(3)
Data in rise time
2
s
t
FI
(3)
Data in fall time
2
s
t
CS
CS deselect time
100
ns
t
WC
(4)
Write cycle time
10
ms
Symbol
Parameter
Voltage
Min.
Max.
Unit
f
SCK
Clock frequency
2.7V5.5V
0
5
MHz
t
DIS
Output disable time
2.7V5.5V
100
ns
t
V
Output valid from clock LOW
2.7V5.5V
80
ns
t
HO
Output hold time
0
ns
t
RO
(5)
Output rise time
50
ns
t
FO
(5)
Output fall time
50
ns
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Figure 7. Serial Output Timing
SYMBOL TABLE
Figure 8. Serial Input Timing
SCK
CS
SO
SI
MSB Out
MSB1 Out
LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
SCK
CS
SI
SO
MSB In
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB In
t
CS
t
FI
High Impedance
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PACKAGING INFORMATION
0.118 0.002
(3.00 0.05)
0.040 0.002
(1.02 0.05)
0.150 (3.81)
Ref.
0.193 (4.90)
0.030 (0.76)
0.036 (0.91)
0.032 (0.81)
0.007 (0.18)
0.005 (0.13)
0.008 (0.20)
0.004 (0.10)
0.0216 (0.55)
7 Typ.
R 0.014 (0.36)
0.118 0.002
(3.00 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) Typ.
8-Lead Miniature Small Outline Gull Wing Package Type M
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
0.220"
0.0256" Typical
0.025"
Typical
0.020"
Typical
8 Places
FOOTPRINT
Ref.
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PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050" Typical
0.050"
Typical
0.030"
Typical
8 Places
FOOTPRINT
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
8-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.114 (2.9)
.122 (3.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16) (7.72)
(1.78)
(0.42)
(0.65)
All Measurements Are Typical
For a more
Integrated Solution use
Xicor System Management Products
X25097
Characteristics subject to change without notice.
14 of 14
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
REV 1.2 11/28/00
www.xicor.com
Ordering Information
Part Mark Convention
Device
X25097
P
T
Temperature Range
Blank = Commercial = 0
C to +70C
I = Industrial = 40
C to +85C
Package
V = 8-Lead TSSOP
S = 8-Lead SOIC
V
V
CC
Limits
2.7 = 2.7V to 5.5V
M = 8-Lead MSOP
8-Lead TSSOP
EYWW
5097XX
F = 2.7 to 5.5V, 0 to +70C
G = 2.7 to 5.5V, -40 to +85C
8-Lead SOIC/MSOP
X25097 X
XX
Blank = 8-Lead SOIC
F = 2.7 to 5.5V, 0 to +70C
G = 2.7 to 5.5V, -40 to +85C
P = 8-Lead PDIP
PDF 
ZIP