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Recommended System Management
Alternative: X5163
16K
X25170
2K x 8 Bit
SPI Serial EEPROM with Block Lock
TM
Protection
FEATURES
5MHz clock rate
SPI modes (0,0 & 1,1)
2K X 8 bits
--32-byte page mode
Low power CMOS
--<1A standby current
--<5mA active current
2.5V To 5.5V power supply
Block lock protection
--Protect 1/4, 1/2 or all of EEPROM array
Built-in inadvertent write protection
--Power-up/power-down protection circuitry
--Write enable latch
--Write protect pin
Self-timed write cycle
--5ms write cycle time (typical)
High reliability
--Endurance: 1,000,000 cycles
--Data retention: 100 Years
--ESD protection: 2000V on all pins
8-lead SOIC package
DESCRIPTION
The X25170 is a CMOS 16384-bit serial EEPROM,
internally organized as 2K x 8. The X25170 features a
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25170 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25170 will ignore transitions on
its inputs, thus allowing the host to service higher pri-
ority interrupts. The WP input can be used as a hard-
wire input to the X25170 (disabling all write attempts to
the status register), thus providing a mechanism for
limiting end user capability of altering 0, 1/4, 1/2 or all
of the memory.
The X25170 utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
Command
Decode
and
Control
Logic
Write
Control
and
Timing
Logic
Write
Protect
Logic
X Decode
Logic
2K Byte
Array
16 X 256
Y Decode
Data Register
SO
SI
SCK
CS
HOLD
WP
16
32
8
32
Status
Register
16
32 X 256
16 X 256
A
PPLICATION
N
OTE
A V A I L A B L E
AN61
Direct Write
TM
and Block Lock
TM
Protection is a trademark of Xicor, Inc.
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PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
It should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
When CS is HIGH, the X25170 is deselected and the
SO output pin is at high impedance; unless an internal
write operation is underway, the X25170 will be in the
standby power mode. CS LOW enables the X25170,
placing it in the active power mode.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is "1",
nonvolatile writes to the X25170 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25170 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no effect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is "0". This allows the user to install
the X25170 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set "1".
PIN NAMES
PIN CONFIGURATION
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
PRINCIPLES OF OPERATION
The X25170 is a 2K x 8 EEPROM designed to inter-
face directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller fami-
lies.
The X25170 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS must be LOW and the HOLD
and WP inputs must be HIGH during the entire opera-
tion. The WP input is "don't care" if WPEN is set "0".
Symbol
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
HOLD
Hold Input
NC
No Connect
SOIC
V
CC
HOLD
SCK
CS
1
2
3
4
6
7
8
X25170
V
SS
SI
5
SO
WP
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Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25170 into a "PAUSE" condition. After releasing
HOLD, the X25170 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25170 contains a "write enable" latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25170 is busy with a write operation. When set to a
"1", a write is in progress, when set to a "0", no write is
in progress. During a write, all other bits are set to "1".
The Write Enable Latch (WEL) bit indicates the status
of the "write enable" latch. When set to a "1", the latch
is set, when set to a "0", the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25170 is divided into four 4096-bit seg-
ments. One, two, or all four of the segments may be
protected. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
7
6
5
4
3
2
1
0
WPEN
X
X
X
BL1
BL0
WEL
WIP
Status Register Bits
Array Addresses
Protected
BP1
BP0
0
0
None
0
1
$0600$07FF
1
0
$0400$07FF
1
1
$0000$07FF
Table 1. Instruction Set
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the write enable latch (enable write operations)
WRDI
0000 0100
Reset the write enable latch (disable write operations)
RDSR
0000 0101
Read status register
WRSR
0000 0001
Write status register
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address (1 to 32-bytes)
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Write-Protect Enable
The Write-Protect-Enable (WPEN) bit is available for
the X25170 as a nonvolatile enable bit for the WP pin.
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
trol the programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
LOW, and the WPEN bit is "1". Hardware write protec-
tion is disabled when either the WP pin is HIGH or the
WPEN bit is "0". When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Protect bits and the
WPEN bit itself, as well as the block-protected sections
in the memory array. Only the sections of the memory
array that are not block-protected can be written.
Note:
Since the WPEN bit is write protected, it cannot
be changed back to a "0", as long as the WP pin is held
LOW.
WPEN
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
LOW
0
Protected
Protected
Protected
1
LOW
1
Protected
Writable
Protected
X
HIGH
0
Protected
Protected
Protected
X
HIGH
1
Protected
Writable
Writable
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25170, followed by the
16-bit address of which the last 11 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($07FF), the
address counter rolls over to address $0000, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
read EEPROM array operation sequence illustrated in
Figure 1.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the con-
tents of the status register are shifted out on the SO
line. The read status register sequence is illustrated in
Figure 2.
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Figure 1. Read EEPROM Array Operation Sequence
Figure 2. Read Status Register Operation Sequence
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
16 Bit Address
15 14 13
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
Write Sequence
Prior to any attempt to write data into the X25170, the
"write enable" latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25170. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
To write data to the EEPROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 32 bytes of data to the
X25170. The only restriction is the 32 bytes must reside
on the same page. If the address counter reaches the
end of the page and the clock continues, the counter will
"roll over" to the first address of the page and overwrite
any data that may have been written.
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Figure 3. Write Enable Latch Sequence
0
1
2
3
4
5
6
7
CS
SI
SCK
High Impedance
SO
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Figure 4. Byte Write Operation Sequence
0
1
2
3
4
5
6
7
8
9
10
CS
SCK
SI
SO
High Impedance
Instruction
16 Bit Address
Data Byte
7
6
5
4
3
2
1
0
15 14 13
3
2
1
0
20 21 22 23 24 25 26 27 28 29 30 31
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be "0". This sequence is shown in Figure 6.
While the write is in progress following a status register
or EEPROM write sequence, the status register may
be read to check the WIP bit. During this time the WIP
bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at V
IH
) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW, and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
V
CC
or tied to V
CC
through a resistor.
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Figure 5. Page Write Operation Sequence
Figure 6. Write Status Register Operation Sequence
32 33 34 35 36 37 38 39
SCK
SI
CS
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
Instruction
16 Bit Address
Data Byte 1
7
6
5
4
3
2
1
0
CS
40 41 42 43 44 45 46 47
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte N
15 14 13
3
2
1
0
20 21 22 23 24 25 26 27 28 29 30 31
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Instruction
Data Byte
7
6
5
4
3
2
1
0
10
11 12 13 14 15
Operational Notes
The X25170 powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The "write enable" latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The "write enable" latch is reset upon power-up.
A WREN instruction must be issued to set the "write
enable" latch.
CS must come HIGH at the proper clock count in order
to start a write cycle.
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................65C to +135
C
Storage temperature .........................65C to +150
C
Voltage on any pin with respect to V
SS
....... 1V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300
C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0C
+70C
Industrial
40C
+85C
Supply Voltage
Limits
X25170-2.5
2.5V to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
POWER-UP TIMING
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Max.
I
CC
V
CC
supply current (active)
5
mA
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 2MHz,
SO = Open, CS = V
SS
SO = Open, CS = V
SS
SO = Open, CS = V
SS
I
SB
V
CC
supply current (standby)
1
A
CS = V
CC
, V
IN
= V
SS
or V
CC
I
LI
Input leakage current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output leakage current
10
A
V
OUT
= V
SS
to V
CC
V
IL
(1)
Input LOW voltage
1
V
CC
x 0.3
V
V
IH
(1)
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output LOW voltage
0.4
V
V
CC
= 5V, I
OL
= 3mA
V
OH1
Output HIGH voltage
V
CC
0.8
V
V
CC
= 5V, I
OH
= -1.6mA
V
OL2
Output LOW voltage
0.4
V
V
CC
= 2.70V, I
OL
= 1.5mA
V
OH2
Output HIGH voltage
V
CC
0.3
V
V
CC
= 2.70V, I
OH
= -0.4mA
Symbol
Parameter
Min.
Max.
Unit
T
PUR
(3)
Power-up to read operation
1
ms
T
PUW
(3)
Power-up to write operation
1
ms
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CAPACITANCE T
A
= +25C, f = 1MHz, V
CC
= 5V
Notes: (1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
Symbol
Parameter
Max.
Unit
Test Conditions
C
OUT
(2)
Output capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
(2)
Input capacitance (SCK, SI, CS, WP, HOLD)
6
pF
V
IN
= 0V
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Output
5V
1.44K
1.95K
100pF
Output
3V
1.64K
4.63K
100pF
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing levels
V
CC
X 0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Data Input Timing
Symbol
Parameter
Min.
Max.
Unit
f
SCK
Clock frequency
0
5
MHz
t
CYC
Cycle time
200
ns
t
LEAD
CS lead time
100
ns
t
LAG
CS lag time
100
ns
t
WH
Clock HIGH time
80
ns
t
WL
Clock LOW time
80
ns
t
SU
Data setup time
20
ns
t
H
Data hold time
20
ns
t
RI
(4)
Data in rise time
2
s
t
FI
(4)
Data in fall time
2
s
t
HD
HOLD setup time
40
ns
t
CD
HOLD hold time
40
ns
t
CS
CS deselect time
100
ns
t
WC
(5)
Write cycle time
5
ms
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Data Output Timing
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle
Serial Output Timing
Serial Input Timing
Symbol
Parameter
Min.
Max.
Unit
f
SCK
Clock frequency
0
5
MHz
t
DIS
Output disable time
100
ns
t
V
Output valid from clock LOW
80
ns
t
HO
Output hold time
0
ns
t
RO
(4)
Output rise time
50
ns
t
FO
(4)
Output fall time
50
ns
t
LZ
(4)
HOLD HIGH to output in low Z
50
ns
t
HZ
(4)
HOLD LOW to output in high Z
50
ns
SCK
CS
SO
SI
MSB Out
MSB1 Out
LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
High Impedance
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Hold Timing
SYMBOL TABLE
SCK
CS
SI
SO
t
HD
t
LZ
HOLD
t
HZ
t
CD
t
HD
t
CD
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
WAVEFORM
INPUTS
OUTPUTS
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PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"
Typical
0.030"
Typical
8 Places
FOOTPRINT
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LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
REV 1.3 12/14/00
www.xicor.com
Ordering Information
Part Mark Convention
X25170
P
-V
Device
V
CC
Limits
2.5 = 2.5V to 5.5V
Temperature Range
Blank = Commercial = 0
C to +70
C
Package
S8 = 8-Lead SOIC
T
I = Industrial = 40
C to +85
C
X
Blank = 8-Lead SOIC
X
AE = 2.5V to 5.5V, 0C to +70C
AF = 2.5V to 5.5V, 40C to +85C
X25170
PDF 
ZIP