Document Outline
- Table of Contents
- Product Selection
- Data Sheet Alpha
- Ap Note Alpha
X25C02
1
2K
X25C02
256 x 8 Bit
FEATURES
1MHz Clock Rate
256 X 8 Bits
--4 Byte Page Mode
Low Power CMOS
--150
A Standby Current
--2mA Active Current
5V Power Supply
Built-in Inadvertent Write Protection
--Power-Up/Power-Down protection circuitry
--Write Latch
--Write Protect Pin
Self-Timed Write Cycle
--5ms Write Cycle Time (Typical)
High Reliability
--Endurance: 100,000 cycles per byte
--Data Retention: 100 Years
--ESD protection: 2000V on all pins
Available Packages
--8-Lead MSOP
--8-Lead PDlP
--8-Lead SOIC
Xicor, Inc. 1994, 1995, 1996 Patents Pending
Characteristics subject to change without notice
3843-1.6 6/10/96 T5/C1/D1 NS
DESCRIPTION
The X25C02 is a CMOS 2048-bit serial E
2
PROM, inter-
nally organized as 256 x 8. The X25C02 features a serial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(
CS
) input, allowing any number of devices to share the
same bus.
The X25C02 also features two additional inputs that
provide the end user with added flexibility. By asserting
the
HOLD
input, the X25C02 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The
WP
input can be used as a hardwire input
to the X25C02 disabling all write attempts, thus provid-
ing a mechanism for limiting end user capability of
altering the memory.
The X25C02 utilizes Xicor's proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
SPI Serial E
2
PROM
Direct Write
TM
is a trademark of Xicor, Inc.
FUNCTIONAL DIAGRAM
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
SO
SI
SCK
CS
HOLD
WP
256 BYTE ARRAY
(64 X 32)
Y DECODE
DATA REGISTER
X
DECODE
LOGIC
64
4
8
3843 FHD F01
A
PPLICATION
N
OTES
A V A I L A B L E
AN9 AN18 AN31 AN37 AN40
X25C02
2
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All data, opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are sampled or latched on the rising edge
of the clock input, while data on the SO pin change after
the falling edge of the clock input.
Chip Select (
CS
)
When
CS
is HIGH, the X25C02 is deselected and the
SO output pin is at HIGH impedance and unless an
internal write operation is underway, the X25C02 will be
in the standby power mode.
CS
LOW enables the
X25C02, placing it in the active power mode. It should be
noted that after power-up, a HIGH to LOW transition on
CS
is required prior to the start of any operation.
Write Protect (
WP
)
When
WP
is LOW, nonvolatile writes to the X25C02 are
disabled, but the part otherwise functions normally.
When
WP
is held HIGH, all functions, including nonvola-
tile writes operate normally.
WP
going LOW while
CS
is
still LOW will interrupt a write to the X25C02. If the
internal write cycle has already been initiated,
WP
going
LOW will have no affect on a write.
Hold (
HOLD
)
HOLD
is used in conjunction with the
CS
pin to select the
device. Once the part is selected and a serial sequence is
underway,
HOLD
may be used to pause the serial
communication with the controller without resetting
the serial sequence. To pause,
HOLD
must be brought
LOW while SCK is LOW. To resume communication,
HOLD
is brought HIGH, again while SCK is LOW. If the
pause feature is not used,
HOLD
should be held HIGH
at all times.
PIN CONFIGURATION
PIN NAMES
Symbol
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
HOLD
Hold Input
3843 PGM T01
3843 FHD F02.2
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
X25C02
MSOP/DIP/SOIC
X25C02
3
PRINCIPLES OF OPERATION
The X25C02 is a 256 x 8 E
2
PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25C02 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK.
CS
must be LOW and the
HOLD
and
WP
inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS
goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the
HOLD
input to place the X25C02 into
a "PAUSE" condition. After releasing
HOLD
, the X25C02
will resume operation from the point when
HOLD
was
first asserted.
Write Enable (WREN) and Write Disable (WRDI)
The X25C02 contains a "write enable" latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte or page write cycle. The latch is
also reset if
WP
is brought LOW.
Table 1. Instruction Set
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
READ
0000 0011
Read Data from Memory Array beginning at selected ad-
dress
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 4 Bytes)
3843 PGM T02
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
X25C02
4
DEVICE OPERATION
Clock and Data Timing
Data input on the SI line is sampled and latched on the
rising edge of SCK. Data is output on the SO line by the
falling edge of SCK.
Read Sequence
The
CS
line is first pulled LOW to select the device. The
8-bit read opcode is transmitted to the X25C02, fol-
lowed by the 8-bit address. After the READ opcode and
byte address are sent, the data stored in the memory
at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be
read sequentially by continuing to provide clock pulses.
The byte address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($FF) the
address counter rolls over to address $00 allowing the
read cycle to be continued indefinitely. The read opera-
tion is terminated by taking
CS
HIGH. Refer to the read
operation sequence illustrated in Figure 1.
Write Sequence
Prior to any attempt to write data into the X25C02, the
"write enable" latch must first be set by issuing the
WREN instruction (See Fig. 2).
CS
is first taken LOW,
then the instruction is clocked into the X25C02. After all
eight bits of the instruction are transmitted,
CS
must then
be taken HIGH. If the user continues the write operation
without taking
CS
HIGH after issuing the WREN instruc-
tion, the write operation will be ignored.
Once the "write enable" latch is set, the user may
proceed by issuing the write instruction, followed by the
address and then the data to be written. This is minimally
a twenty-four clock operation.
CS
must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to four bytes of data to the
X25C02. The only restriction is the four bytes must
reside on the same page. A page address begins with
address XXXX XX00 and ends with XXXX XX11. If the
byte address counter reaches XXXX XX11 and the clock
continues the counter will "roll over" to the first address
of the page and overwrite any data that may have been
written.
For the write operation (byte or page write) to be
completed,
CS
can only be brought HIGH after the
twenty-fourth, thirty-second, fourtieth or fourty-eighth
clock. If it is brought HIGH at any other time, the write
operation will not be completed. Refer to Figure 4 for a
detailed illustration of the page write sequence and time
frames in which
CS
going HIGH are valid.
Hold Operation
The
HOLD
input should be HIGH (at V
IH
) under normal
operation. If a data transfer is to be interrupted
HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
LOW when
HOLD
is first pulled low and SCK must also
be LOW when
HOLD
is released.
The
HOLD
input may be tied HIGH either directly to V
CC
or tied to V
CC
through a resistor.
X25C02
5
Figure 1. Read Operation Sequence
Operational Notes
The X25C02 powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on
CS
is required to
enter an active state and receive an instruction.
SO pin is high impedance.
The "write enable" latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The "write enable" latch is reset upon power-up.
A WREN instruction must be issued to set the "write
enable" latch.
CS
must come HIGH at the proper clock count in
order to start a write cycle.
The "write enable" latch is reset when
WP
is brought LOW.
Figure 2. Set Write Enable Latch Sequence
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22
3843 FHD F04.1
7
6
5
4
3
2
1
0
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
BYTE ADDRESS
0
1
2
3
4
5
6
7
3843 FHD F05.1
CS
SI
SCK
HIGH IMPEDANCE
SO
X25C02
6
Figure 3. Byte Write Operation Sequence
Figure 4. Page Write Operation Sequence
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
CS
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22 23
3843 FHD F07.2
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA BYTE 1
7
6
5
4
3
2
1
0
CS
40 41 42 43 44 45 46 47
DATA BYTE 2
7
6
5
4
3
2
1
0
DATA BYTE 3
7
6
5
4
3
2
1
0
DATA BYTE 4
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22 23
3843 FHD F06.2
CS
SCK
SI
SO
HIGH IMPEDANCE
INSTRUCTION
BYTE ADDRESS
DATA BYTE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X25C02
7
Supply Voltage
Limits
X25C02
5V
10%
3843 PGM T04.1
Notes:
(1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Military
55
C
+125
C
3843 PGM T03.1
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with Respect to V
SS .........
1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300
C
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Units
t
PUR
(1)
Power-up to Read Operation
1
ms
t
PUW
(1)
Power-up to Write Operation
5
ms
3843 PGM T09
CAPACITANCE T
A
= +25
C, f = 1MHz, V
CC
= 5V.
Symbol
Test
Max.
Units
Conditions
C
OUT
(2)
Output Capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
(2)
Input Capacitance (SCK, SI,
CS
,
WP
,
HOLD
)
6
pF
V
IN
= 0V
3843 PGM T06.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
I
CC
V
CC
Supply Current (Active)
2
mA
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 1MHz,
SO = Open
I
SB
V
CC
Supply Current (Standby)
150
A
CS
= V
CC
,
V
IN
= V
SS
or V
CC
0.3V
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
V
IL
(1)
Input LOW Voltage
1
V
CC
x 0.3
V
V
IH
(1)
Input HIGH Voltage
V
CC
x 0.7 V
CC
+ 0.5
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 2mA
V
OH
Output HIGH Voltage
V
CC
0.8
V
I
OH
= 1mA
3843 PGM T05.3
X25C02
8
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
V
CC
x 0.5
3843 PGM T07
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
Parameter
Min.
Max.
Units
f
SCK
Clock Frequency
0
1
MHz
t
CYC
Cycle Time
1000
ns
t
LEAD
CS
Lead Time
500
ns
t
LAG
CS
Lag Time
500
ns
t
WH
Clock HIGH Time
400
ns
t
WL
Clock LOW Time
400
ns
t
SU
Data Setup Time
100
ns
t
H
Data Hold Time
100
ns
t
RI
Data In Rise Time
2
s
t
FI
Data In Fall Time
2
s
t
HD
HOLD
Setup Time
200
ns
t
CD
HOLD
Hold Time
200
ns
t
CS
CS
Deselect Time
500
ns
t
WC
(3)
Write Cycle Time
10
ms
3843 PGM T08.2
Data Output Timing
Symbol
Parameter
Min.
Max.
Units
f
SCK
Clock Frequency
0
1
MHz
t
DIS
Output Disable Time
500
ns
t
V
Output Valid from clock Low
400
ns
t
HO
Output Hold Time
0
ns
t
RO
(1)
Output Rise Time
300
ns
t
FO
(1)
Output Fall Time
300
ns
t
LZ
HOLD
HIGH to Output in Low Z
100
ns
t
HZ
HOLD
LOW to Output in High Z
100
ns
3843 PGM T09.1
Notes: (3) t
WC
is the time from the rising edge of
CS
after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
5V
2.16K
3.07K
OUTPUT
100pF
3843 FHD F12.1
X25C02
9
Serial Output Timing
Serial Input Timing
3843 FHD F10
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
HIGH IMPEDANCE
SCK
CS
SO
SI
MSB OUT
MSB1 OUT
LSB OUT
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
3843 FHD F09.1
t
LAG
X25C02
10
Hold Timing
3843 FHD F11
SCK
CS
SI
SO
t
HD
t
LZ
HOLD
t
CD
t
HZ
t
CD
t
HD
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X25C02
11
PACKAGING INFORMATION
0.118
0.002
(3.00
0.05)
0.040
0.002
(1.02
0.05)
0.150 (3.81)
REF.
0.193 (4.90)
REF.
0.030 (0.76)
0.036 (0.91)
0.032 (0.81)
0.007 (0.18)
0.005 (0.13)
0.008 (0.20)
0.004 (0.10)
0.0216 (0.55)
7
TYP
R 0.014 (0.36)
0.118
0.002
(3.00
0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) TYP
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3926 ILL F49
X25C02
12
PACKAGING INFORMATION
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.020 (0.51)
0.016 (0.41)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.430 (10.92)
0.360 (9.14)
0.300
(7.62) REF.
PIN 1 INDEX
0.145 (3.68)
0.128 (3.25)
0.025 (0.64)
0.015 (0.38)
PIN 1
SEATING
PLANE
0.065 (1.65)
0.045 (1.14)
0.260 (6.60)
0.240 (6.10)
0.060 (1.52)
0.020 (0.51)
TYP. 0.010 (0.25)
0
15
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.015 (0.38)
MAX.
0.325 (8.25)
0.300 (7.62)
X25C02
13
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
PIN 1
PIN 1 INDEX
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0
8
X 45
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050" TYPICAL
0.050"
TYPICAL
0.030"
TYPICAL
8 PLACES
FOOTPRINT
X25C02
14
X25C02
P T
-V
Device
ORDERING INFORMATION
V
CC
Limits
Blank = 5V
10%
Temperature Range
Blank = Commercial = 0
C to +70
C
I = Industrial = 40
C to +85
C
M = Military = 55
C to +125
C
Package
M = 8-Lead MSOP
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
Blank = 5V
10%, 0
C to +70
C
I = 5V
10%, 40
C to +85
C
M = 5V
10%, 55
C to +125
C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Part Mark Convention
X25C02 X
X
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