Document Outline
- Table of Contents
- Product Selection
- Data Sheet Alpha
- Ap Note Alpha
X28LC512/X28LC513
1
512K
X28LC512/X28LC513
64K x 8 Bit
3.3 Volt, Byte Alterable E
2
PROM
Xicor, Inc. 1991, 1995, 1996 Patents Pending
Characteristics subject to change without notice
3005-3.2 8/5/97 T2/C0/D0 EW
FEATURES
Low V
CC
Operation: V
CC
= 3.3V
10%
Access Time: 150ns
Simple Byte and Page Write
--Self-Timed
--No Erase Before Write
--No Complex Programming Algorithms
--No Overerase Problem
Low Power CMOS:
--Active: 25mA
--Standby: 150
A
Software Data Protection
--Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct WriteTM Cell
--Endurance: 10,000 Write Cycles
--Data Retention: 100 Years
Early End of Write Detection
--
DATA
Polling
--Toggle Bit Polling
3005 ILL F04.1
3005 ILL F03
Two PLCC and LCC Pinouts
--X28LC512
--X28LC010 E
2
PROM Pin Compatible
--X28LC513
--Compatible with Lower Density E
2
PROMs
DESCRIPTION
The X28LC512/513 is a low-power 64K x 8 E
2
PROM,
fabricated with Xicor's proprietary, high performance,
floating gate CMOS technology. The X28LC512/513
features the JEDEC approved pinout for bytewide memo-
ries, compatible with industry standard EPROMS.
The X28LC512/513 supports a 128-byte page write
operation, effectively providing a 39
s/byte write cycle
and enabling the entire memory to be written in less than
2.5 seconds. The X28LC512/513 also features
DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28LC512/513 supports the Soft-
ware Data Protection option.
PLCC
X28LC512
(TOP VIEW)
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
OE
A10
CE
I/O7
A14
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
A
12
A
15
NC
NC
V
CC
WE
NC
2
32
6
1
5 4 3
8
7
9
10
11
12
13
15
17
16
18 19 20
22
23
24
25
26
27
28
29
31
14
21
30
X28LC513
(TOP VIEW)
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A9
A11
NC
A10
OE
I/O7
CE
I/O6
A8
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
A
7
A
12
A
14
A
15
V
CC
WE
A
13
2
32
6
1
5 4 3
8
7
9
10
11
12
13
15
17
16
18 19 20
22
23
24
25
26
27
28
29
31
21
14
30
PLCC
PIN CONFIGURATIONS
3005 ILL F02.1
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
X28LC512
PLASTIC DIP
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
X28LC512
TSOP
3005 ILL F22.2
2
X28LC512/X28LC513
PIN DESCRIPTIONS
Addresses (A
0
A
15
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (
OE
)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
I/O
7
)
Data is written to or read from the X28LC512/513
through the I/O pins.
PIN NAMES
Symbol
Description
A
0
A
15
Address Inputs
I/O
0
I/O
7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
V
CC
3.3V
10%
V
SS
Ground
NC
No Connect
3005 PGM T01
Write Enable (
WE
)
The Write Enable input controls the writing of data to the
X28LC512/513.
3005 ILL F01
X BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
512K-BIT
E2PROM
ARRAY
I/O0I/O7
DATA INPUTS/OUTPUTS
CE
OE
VCC
VSS
A7A15
WE
A0A6
FUNCTIONAL DIAGRAM
X28LC512/X28LC513
3
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The X28LC512/513 supports
both a
CE
and
WE
controlled write cycle. That is, the
address is latched by the falling edge of either
CE
or
WE
,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either
CE
or
WE
, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
Page Write Operation
The page write feature of the X28LC512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28LC512/513 prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A
7
through A
15
) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE
HIGH to LOW transition, must begin within 100
s of
the falling edge of the preceding
WE
. If a subsequent
WE
HIGH to LOW transition is not detected within
100
s, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100
s.
Write Operation Status Bits
The X28LC512/513 provides the user two write opera-
tion status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5
TB
DP
4
3
2
1
0
I/O
RESERVED
TOGGLE BIT
DATA POLLING
3005 ILL F11
DATA
Polling (I/O
7
)
The X28LC512/513 features
DATA
Polling as a method
to indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the X28LC512/
513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28LC512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
4
X28LC512/X28LC513
DATA
Polling I/O
7
Figure 2a.
DATA
Polling Bus Sequence
Figure 2b.
DATA
Polling Software Flow
3005 ILL F12
DATA
Polling can effectively halve the time for writing to
the X28LC512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The
software flow diagram in Figure 2b illustrates one method
of implementing the routine.
3005 ILL F13
WRITE DATA
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
X28LC512
READY
NO
YES
WRITES
COMPLETE?
NO
YES
CE
OE
WE
I/O7
X28LC512
READY
LAST
WRITE
HIGH Z
VOL
VIH
A0A15
An
An
An
An
An
An
VOH
An
X28LC512/X28LC513
5
The Toggle Bit I/O
6
Figure 3a. Toggle Bit Bus Sequence
Figure 3b. Toggle Bit Software Flow
3005 ILL F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement
DATA
Polling.
This can be especially helpful in an array comprised of
multiple X28LC512/513 memories that is frequently
updated. Toggle Bit Polling can also provide a method
for status checking in multiprocessor applications. The
timing diagram in Figure 3a illustrates the sequence of
events on the bus. The software flow diagram in Figure
3b illustrates a method for polling the Toggle Bit.
3005 ILL F15
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
X28LC512
READY
COMPARE
OK?
NO
YES
LAST WRITE
CE
OE
WE
I/O6
X28LC512
READY
VOH
VOL
LAST
WRITE
HIGH Z
* Beginning and ending state of I/O6 will vary.
*
*
6
X28LC512/X28LC513
HARDWARE DATA PROTECTION
The X28LC512/513 provides three hardware features
that protect nonvolatile data from inadvertent writes.
Noise Protection--A
WE
pulse typically less than
10ns will not initiate a write cycle.
Write Inhibit--Holding either
OE
LOW,
WE
HIGH,
or
CE
HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
SOFTWARE DATA PROTECTION
The X28LC512/513 offers a software controlled data
protection feature. The X28LC512/513 is shipped from
Xicor with the software data protection NOT ENABLED;
that is, the device will be in the standard operating mode.
In this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
of the device once V
CC
was stable.
The X28LC512/513 can be automatically protected dur-
ing power-up and power-down without the need for
external circuits by employing the software data protec-
tion feature. The internal software data protection circuit
is enabled after the first write operation utilizing the
software algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28LC512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data
to the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 4a and 4b for the sequence.
The three byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle has
been completed, the device will automatically be re-
turned to the data protected state.
X28LC512/X28LC513
7
NOTE: All other timings and control pins are per page write timing requirements.
CE
WE
(VCC)
WRITE
PROTECTED
VCC
0V
DATA
ADDR
AA
5555
55
2AAA
A0
5555
tBLC MAX
WRITES
OK
BYTE
OR
PAGE
tWC
Software Data Protection
Figure 4a. Timing Sequence--Software Data Protect Enable Sequence followed by Byte or Page Write
Figure 4b. Write Sequence for Software Data
Protection
WRITE LAST
BYTE TO
LAST ADDRESS
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
WRITE DATA AA
TO ADDRESS
5555
OPTIONAL
BYTE/PAGE
LOAD OPERATION
Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the
X28LC512/513 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28LC512/513 will be
write protected during power-down and after any subse-
quent power-up. The state of A
15
while executing the
algorithm is don't care.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3005 ILL F16
3005 FHD F17
8
X28LC512/X28LC513
CE
WE
STANDARD
OPERATING
MODE
VCC
DATA
ADDR
AA
5555
55
2AAA
80
5555
NOTE: All other timings and control pins are per page write timing requirements.
tWC
AA
5555
55
2AAA
20
5555
Resetting Software Data Protection
Figure 5a. Reset Software Data Protection Timing Sequence
Figure 5b. Software Sequence to Deactivate
Software Data Protection
3005 ILL F18
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E
2
PROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After t
WC
,
the X28LC512/513 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 20
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
3005 FHD F19
X28LC512/X28LC513
9
SYSTEM CONSIDERATIONS
Because the X28LC512/513 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where mul-
tiple I/O pins share the same bus.
To gain the most benefit it is recommended that
CE
be
decoded from the address bus and be used as the
primary device selection input. Both
OE
and
WE
would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28LC512/513 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling
CE
will cause
transient current spikes. The magnitude of these spikes
is dependent on the output capacitive loading of the I/
Os. Therefore, the larger the array sharing a common
bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1
F high frequency ceramic capacitor
be used between V
CC
and V
SS
at each device. Depend-
ing on the size of the array, the value of the capacitor
may have to be larger.
In addition, it is recommended that a 4.7
F electrolytic
bulk capacitor be placed between V
CC
and V
SS
for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Active Supply Current vs. Ambient Temperature
I
CC
(RD) by Temperature over Frequency
Standby Supply Current vs. Ambient Temperature
55
10
+125
0.1
0.11
0.12
0.13
0.14
AMBIENT TEMPERATURE (
C)
I
SB
(mA)
3005 ILL F26
0.08
+35
+80
V
CC
= 3.3V
0.09
55
10
+125
5
5.5
6
6.5
7.5
AMBIENT TEMPERATURE (
C)
I
CC
(mA)
3005 ILL F25
4
+35
+80
7
V
CC
= 3.3V
4.5
0
15
20
25
30
35
FREQUENCY (MHz)
I
CC
RD (mA)
3005 ILL F24
10
5
10
55C
+25C
+125C
15
40
3.3 V
CC
10
X28LC512/X28LC513
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Active)
25
mA
CE
=
OE
= V
IL
,
WE
= V
IH
,
(CMOS Inputs)
All I/O's = Open, Address Inputs =
0.1xV
CC
/0.9xV
CC
Levels
@ f = 5MHz
I
SB
V
CC
Current (Standby)
150
A
OE
= V
IL
,
CE
= V
CC
0.3V
(CMOS Inputs)
All I/O's = Open, Other Inputs = V
IH
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
,
CE
= V
CC
V
lL
(1)
Input LOW Voltage
1
0.6
V
V
IH
(1)
Input HIGH Voltage
2
V
CC
+ 0.5
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 1mA
V
OH
Output HIGH Voltage
2.4
V
I
OH
= 200
A
3005 PGM T04.2
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28LC512/513 ............................. 10
C to +85
C
X28LC512I/X28LC513I .............. 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to V
SS .......................................
1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300
C
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMEND OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
3005 PGM T02
Supply Voltage
Limits
X28LC512/513
3.3V
10%
3005 PGM T03.1
Notes: (1) V
IL
min. and V
IH
max. are for reference only and are not tested.
X28LC512/X28LC513
11
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR
(2)
Power-up to Read Operation
100
s
t
PUW
(2)
Power-up to Write Operation
5
ms
3005 PGM T05
CAPACITANCE T
A
= +25
C, f = 1MHz, V
CC
= 3.3V
Symbol
Parameter
Max.
Units
Test Conditions
C
I/O
(2)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(2)
Input Capacitance
10
pF
V
IN
= 0V
3005 PGM T06.1
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Units
Endurance
10,000
Cycles per Byte
Data Retention
100
Years
3005 PGM T11
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
10ns
Input and Output
Timing Levels
1.5V
3856 PGM T07.1
MODE SELECTION
CE
OE
WE
Mode
I/O
Power
L
L
H
Read
D
OUT
Active
L
H
L
Write
D
IN
Active
H
X
X
Standby and
High Z
Standby
Write Inhibit
X
L
X
Write Inhibit
--
--
X
X
H
Write Inhibit
--
--
3005 PGM T08
Note:
(2) This parameter is periodically sampled and not 100%
tested.
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
3005 ILL F21.3
5V
2.66K
30pF
4.46K
OUTPUT
12
X28LC512/X28LC513
Read Cycle Limits
X28LC512-15
X28LC512-20
X28LC512-25
X28LC513-15
X28LC513-20
X28LC513-25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
RC
Read Cycle Time
150
200
250
ns
t
CE
Chip Enable Access Time
150
200
250
ns
t
AA
Address Access Time
150
200
250
ns
t
OE
Output Enable Access Time
80
80
80
ns
t
LZ
(3)
CE
LOW to Active Output
0
0
0
ns
t
OLZ
(3)
OE
LOW to Active Output
0
0
0
ns
t
HZ
(3)
CE
HIGH to High Z Output
50
50
50
ns
t
OHZ
(3)
OE
HIGH to High Z Output
50
50
50
ns
t
OH
Output Hold from
0
0
0
ns
Address Change
3005 PGM T09.2
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle
Notes: (3) t
LZ
min., t
HZ
, t
OLZ
min., and tOHZ are periodically sampled and not 100% tested. t
HZ
max. and t
OHZ
max. are measured, with
C
L
= 5pF from the point when
CE
or
OE
return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
3005 FHD F05
tCE
tRC
ADDRESS
CE
OE
WE
DATA VALID
DATA VALID
tOE
tLZ
tOLZ
tOH
tAA
tHZ
tOHZ
DATA I/O
VIH
HIGH Z
X28LC512/X28LC513
13
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Max.
Units
t
WC
(4)
Write Cycle Time
5
ms
t
AS
Address Setup Time
0
ns
t
AH
Address Hold Time
50
ns
t
CS
Write Setup Time
0
ns
t
CH
Write Hold Time
0
ns
t
CW
CE
Pulse Width
100
ns
t
OES
OE
HIGH Setup Time
10
ns
t
OEH
OE
HIGH Hold Time
10
ns
t
WP
WE
Pulse Width
100
ns
t
WPH
WE
HIGH Recovery
100
ns
t
DV
Data Valid
1
s
t
DS
Data Setup
50
ns
t
DH
Data Hold
0
ns
t
DW
Delay to Next Write
10
s
t
BLC
Byte Load Cycle
0.20
100
s
3005 PGM T10.1
WE
Controlled Write Cycle
Notes: (4) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to complete the internal write operation.
3005 ILL F06
ADDRESS
tAS
tWC
tAH
tOES
tDV
tDS
tDH
tOEH
CE
WE
OE
DATA IN
DATA OUT
HIGH Z
tCS
tCH
tWP
DATA VALID
14
X28LC512/X28LC513
CE
Controlled Write Cycle
3005 ILL F07
Notes: (5) Between successive byte writes within a page write operation,
OE
can be strobed LOW: e.g. this can be done with
CE
and
WE
HIGH
to fetch data from another memory device within the system for the next write; or with
WE
HIGH and
CE
LOW effectively performing
a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the
CE
or
WE
controlled write cycle timing.
Page Write Cycle
ADDRESS
tAS
tOEH
tWC
tAH
tOES
tWPH
tCS
tDV
tDS
tDH
tCH
CE
WE
OE
DATA IN
DATA OUT
HIGH Z
tCW
DATA VALID
WE
OE
(5)
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
tWP
tWPH
tBLC
tWC
CE
*ADDRESS
(6)
I/O
*For each successive write within the page write operation, A7A15 should be the same or
writes to an unknown address could occur.
LAST BYTE
3005 ILL F08.1
X28LC512/X28LC513
15
DATA
Polling Timing Diagram
(7)
ADDRESS
An
DIN=X
DOUT=X
DOUT=X
tWC
tOEH
tOES
An
An
CE
WE
OE
I/O7
tDW
3005 ILL F09
Toggle Bit Timing Diagram
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z
*
*
* Starting and ending state of I/O6 will vary, depending upon actual tWC.
3005 ILL F10
Note:
(7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
16
X28LC512/X28LC513
PACKAGING INFORMATION
0.021 (0.53)
0.013 (0.33)
0.420 (10.67)
0.050 (1.27) TYP.
TYP. 0.017 (0.43)
0.045 (1.14) x 45
0.300 (7.62)
REF.
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
PIN 1
0.400
(10.16)
REF.
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
3
TYP.
0.048 (1.22)
0.042 (1.07)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.095 (2.41)
0.060 (1.52)
--
0.015 (0.38)
SEATING PLANE
0.004 LEAD
CO PLANARITY
3926 FHD F13
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
X28LC512/X28LC513
17
PACKAGING INFORMATION
3926 FHD F25
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.022 (0.56)
0.014 (0.36)
0.160 (4.06)
0.125 (3.17)
0.625 (15.88)
0.590 (14.99)
0.110 (2.79)
0.090 (2.29)
1.665 (42.29)
1.644 (41.76)
1.500 (38.10)
REF.
PIN 1 INDEX
0.160 (4.06)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
PIN 1
SEATING
PLANE
0.070 (17.78)
0.030 (7.62)
0.557 (14.15)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
0
15
32-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
TYP. 0.010 (0.25)
18
X28LC512/X28LC513
PACKAGING INFORMATION
3926 ILL F39.2
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
0.50
0.04
(0.0197
0.0016)
0.30
0.05
(0.012
0.002)
14.80
0.05
(0.583
0.002)
1.30
0.05
(0.051
0.002)
0.17 (0.007)
0.03 (0.001)
TYPICAL
40 PLACES
15 EQ. SPC. @ 0.50
0.04
0.0197
0.016 = 9.50
0.06
(0.374
0.0024) OVERALL
TOL. NON-CUMULATIVE
SOLDER PADS
FOOTPRINT
10.058 (0.396)
9.957 (0.392)
12.522 (0.493)
12.268 (0.483)
PIN #1 IDENT.
O 1.016 (0.040)
O 0.762 (0.030)
1
0.965
(0.038)
1.143 (0.045)
0.889 (0.035)
0.127 (0.005) DP.
0.076 (0.003) DP.
X
0.065 (0.0025)
14.148 (0.557)
13.894 (0.547)
SEATING
PLANE
A
0.178 (0.007)
1.016 (0.040)
SEATING
PLANE
15
TYP.
0.500 (0.0197)
1.219 (0.048)
0.254 (0.010)
0.152 (0.006)
0.432 (0.017)
0.813 (0.032) TYP.
0.432 (0.017)
0.508 (0.020) TYP.
0.152 (0.006)
TYP.
4
TYP.
DETAIL A
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
X28LC512/X28LC513
19
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976.
Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
ORDERING INFORMATION
Device
Access Time
15 = 150ns
20 = 200ns
25 = 250ns
Temperature Range
Blank = Commercial = 0
C to +70
C
I = Industrial = 40
C to +85
C
Package
J = 32-Lead PLCC
X28LC513 X X -X
Device
Access Time
15 = 150ns
20 = 200ns
25 = 250ns
Temperature Range
Blank = Commercial = 0
C to +70
C
I = Industrial = 40
C to +85
C
Package
J = 32-Lead PLCC
P = 32-Lead Plastic Dip
T = 40-Lead TSOP
X28LC512 X X -X
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