X28VC256

©Xicor, Inc. 1991, 1995 Patents Pending

Characteristics subject to change without notice

3869-2.6 4/2/96 T4/C4/D0 NS

5 Volt, Byte Alterable E

PROM

FEATURES

Access Time: 45ns

Simple Byte and Page Write
--Single 5V Supply

-- No External High Voltages or V

Control

Circuits

--Self-Timed

-- No Erase Before Write
-- No Complex Programming Algorithms
--No Overerase Problem

Low Power CMOS:
--Active: 80mA
--Standby: 10mA

Software Data Protection
--Protects Data Against System Level

Inadvertent Writes

High Speed Page Write Capability

Highly Reliable Direct Write

Cell

--Endurance: 100,000 Write Cycles
--Data Retention: 100 Years

Early End of Write Detection
--

DATA

Polling

--Toggle Bit Polling

DESCRIPTION

The X28VC256 is a second generation high perfor-
mance CMOS 32K x 8 E

PROM. It is fabricated with

Xicor's proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvolatile
memory.

The X28VC256 supports a 128-byte page write opera-
tion, effectively providing a 24

s/byte write cycle and

enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28VC256 also features

DATA

Polling and Toggle Bit Polling, two methods of

providing early end of write detection. The X28VC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.

Endurance for the X28VC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.

256K

X28VC256

32K x 8 Bit

PIN CONFIGURATION

A14

A12

A7
A6
A5
A4
A3
A2
A1
A0

I/O0
I/O1
I/O2

VSS

VCC
WE

A13
A8
A9
A11
OE

A10
CE

I/O7
I/O6
I/O5
I/04
I/O3

X28VC256

3869 FHD F02

PLASTIC DIP

CERDIP

FLAT PACK

SOIC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

X28VC256

A3
A4
A5
A6
A7
A12
A14
NC
VCC
NC
WE
A13
A8
A9
A11
OE

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A2
A1
A0

I/O0
I/O1
I/O2

VSS

I/O3
I/O4
I/O5
I/O6
I/O7

A10

TSOP

A6
A5
A4
A3
A2
A1
A0

I/O0

A8
A9
A11
NC

A10
CE

I/O7
I/O6

1 32 31 30

14 15 16 17 18 19 20

X28VC256

I/O

LCC

PLCC

3869 FHD F03

3869 ILL F22

X28VC256

PIN DESCRIPTIONS

Addresses (A

)

The Address inputs select an 8-bit memory location
during a read or write operation.

Chip Enable (

)

The Chip Enable input must be LOW to enable all read/
write operations. When

is HIGH, power consumption

is reduced.

Output Enable (

)

The Output Enable input controls the data output buffers
and is used to initiate read operations.

Data In/Data Out (I/O

I/O

)

Data is written to or read from the X28VC256 through the
I/O pins.

Write Enable (

)

The Write Enable input controls the writing of data to the
X28VC256.

X BUFFERS

LATCHES AND

DECODER

I/O BUFFERS

AND LATCHES

3869 FHD F01

Y BUFFERS

LATCHES AND

DECODER

CONTROL

LOGIC AND

TIMING

256K-BIT
E2PROM

ARRAY

I/O0I/O7

DATA INPUTS/OUTPUTS

VCC

VSS

A0A14

ADDRESS

INPUTS

3869 FHD F01

FUNCTIONAL DIAGRAM

PIN NAMES

Symbol

Description

Address Inputs

I/O

Data Input/Output

Write Enable

Chip Enable

Output Enable

+5V

Ground

No Connect

3869 PGM T01

PGA

3869 FHD F04

PIN CONFIGURATION

I/O0

VSS

A12

VCC

I/O1

I/O2

I/O3

I/O4

I/O5

I/O7

A10

A11

I/O6

A13

X28VC256

(BOTTOM VIEW)

A14

X28VC256

DEVICE OPERATION

Read

Read operations are initiated by both

and

LOW.

The read operation is terminated by either

returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either

is HIGH.

Write

Write operations are initiated when both

and

are

LOW and

is HIGH. The X28VC256 supports both a

and

controlled write cycle. That is, the address

is latched by the falling edge of either

whichever occurs last. Similarly, the data is latched
internally by the rising edge of either

whichever occurs first. A byte write operation, once
initiated, will automatically continue to completion, typi-
cally within 3ms.

Page Write Operation

The page write feature of the X28VC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight bytes
of data to be consecutively written to the X28VC256
prior to the commencement of the internal programming
cycle. The host can fetch data from another device
within the system during a page write operation (change
the source address), but the page address (A

through

) for each subsequent valid write cycle to the part

during this operation must be the same as the initial
page address.

The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the

HIGH to LOW transition, must begin within 100

s of

the falling edge of the preceding

. If a subsequent

HIGH to LOW transition is not detected within

100

s, the internal automatic programming cycle will

commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100

Write Operation Status Bits

The X28VC256 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus as
shown in Figure 1.

Figure 1. Status Bit Assignment

3869 FHD F11

DATA

Polling (I/O

)

The X28VC256 features

DATA

Polling as a method to

indicate to the host system that the byte write or page
write cycle has completed.

DATA

Polling allows a simple

bit test operation to determine the status of the
X28VC256, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will
produce the complement of that data on I/O

(i.e., write

data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O

will reflect true

data.

Toggle Bit (I/O

)

The X28VC256 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O

will toggle from

HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read and write operations.

I/O

RESERVED

TOGGLE BIT

DATA POLLING

X28VC256

THE TOGGLE BIT I/O

Figure 4. Toggle Bit Bus Sequence

3869 FHD F14

Figure 5. Toggle Bit Software Flow

The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement

DATA

Polling.

This can be especially helpful in an array comprised of
multiple X28VC256 memories that is frequently up-
dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for polling the
Toggle Bit.

3869 FHD F15

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

X28VC256

READY

COMPARE

OK?

YES

LAST WRITE

YES

I/O6

X28VC256
READY

VOH

VOL

LAST

WRITE

HIGH Z

* I/O6 beginning and ending state of I/O6 will vary.

X28VC256

circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.

Once the software protection is enabled, the X28VC256
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.

SOFTWARE ALGORITHM

Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle has
been completed, the device will automatically be re-
turned to the data protected state.

HARDWARE DATA PROTECTION

The X28VC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.

Default V

Sense--All write functions are inhibited

when V

3.5V typically.

Write Inhibit--Holding either

LOW,

HIGH, or

HIGH will prevent an inadvertent write cycle during

power-up and power-down, maintaining data integrity.

SOFTWARE DATA PROTECTION

The X28VC256 offers a software controlled data protec-
tion feature. The X28VC256 is shipped from Xicor with
the software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/down
operations through the use of external circuits. The host
would then have open read and write access of the
device once V

was stable.

The X28VC256 can be automatically protected during
power-up and power-down without the need for external

X28VC256

SOFTWARE DATA PROTECTION

Figure 6. Timing Sequence--Byte or Page Write

3869 FHD F16

Figure 7. Write Sequence for
Software Data Protection

Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28VC256 will automatically disable further writes un-
less another command is issued to cancel it. If no further
commands are issued the X28VC256 will be write
protected during power-down and after any subsequent
power-up.

Note:

Once initiated, the sequence of write operations
should not be interrupted.

3869 FHD F17

(VCC)

WRITE
PROTECTED

VCC

DATA
ADDRESS

5555

2AAA

5555

tBLC MAX

WRITES

BYTE

PAGE

tWC

tBLC MAX

WRITE LAST

BYTE TO

LAST ADDRESS

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA A0

TO ADDRESS

5555

WRITE DATA XX

TO ANY

ADDRESS

AFTER tWC

RE-ENTERS DATA

PROTECTED STATE

WRITE DATA AA

TO ADDRESS

5555

BYTE/PAGE
LOAD ENABLED

OPTIONAL
BYTE OR
PAGE WRITE
ALLOWED

X28VC256

Figure 9. Write Sequence for Resetting
Software Data Protection

RESETTING SOFTWARE DATA PROTECTION

Figure 8. Reset Software Data Protection Timing Sequence

3869 FHD F18

In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E

PROM programmer, the following six step algo-

rithm will reset the internal protection circuit. After t

the X28VC256 will be in standard operating mode.

Note:

Once initiated, the sequence of write operations
should not be interrupted.

3869 FHD F19

STANDARD
OPERATING
MODE

VCC

DATA
ADDRESS

5555

2AAA

5555

tWC

5555

2AAA

5555

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA 80

TO ADDRESS

5555

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 20

TO ADDRESS

5555

WRITE DATA AA

TO ADDRESS

5555

AFTER tWC,

RE-ENTERS

UNPROTECTED

STATE

X28VC256

prime concern. Enabling

will cause transient current

spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the l/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1

F high fre-

quency ceramic capacitor be used between V

and

at each device. Depending on the size of the array,

the value of the capacitor may have to be larger.

In addition, it is recommended that a 4.7

F electrolytic

bulk capacitor be placed between V

and V

for each

eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.

SYSTEM CONSIDERATIONS

Because the X28VC256 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where mul-
tiple I/O pins share the same bus.

To gain the most benefit it is recommended that

decoded from the address bus and be used as the
primary device selection input. Both

and

would

then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.

Because the X28VC256 has two power modes, standby
and active, proper decoupling of the memory array is of

X28VC256

*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias

X28VC256 .................................. 10

C to +85

X28VC256I, X28VC256M .......... 65

C to +135

Storage Temperature ....................... 65

C to +150

Voltage on any Pin with

Respect to V

.................................. 1V to +7V

D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds) ...... 300

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

+70

Industrial

+85

Military

+125

3869 PGM T02.1

Supply Voltage

Limits

X28VC256

10%

3869 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

(1)

Max.

Units

Test Conditions

Active Current

= V

All I/O's = Open, Address Inputs =
0.4V/2.4V Levels @ f = 10MHz

Standby Current

= V

, All I/O's =

Open, Other Inputs = V

Input Leakage Current

= V

to V

Output Leakage Current

OUT

= V

to V

= V

lL(2)

Input LOW Voltage

0.8

IH(2)

Input HIGH Voltage

+ 1

Output LOW Voltage

0.4

= 6mA

Output HIGH Voltage

2.4

= 4mA

3869 PGM T04.2

Notes: (1) Typical values are for T

= 25

C and nominal supply voltage.

(2) V

min. and V

max. are for reference only and are not tested.

X28VC256

POWER-UP TIMING

Symbol

Parameter

Max.

Units

PUR(3)

Power-Up to Read

100

PUW(3)

Power-Up to Write

3869 PGM T05

CAPACITANCE T

= +25

C, f = 1MH

, V

= 5V.

Symbol

Test

Max.

Units

Conditions

I/O(3)

Input/Output Capacitance

I/O

= 0V

IN(3)

Input Capacitance

= 0V

3869 PGM T06.1

ENDURANCE AND DATA RETENTION

Parameter

Min.

Max.

Units

Endurance

100,000

Cycles

Data Retention

100

Years

3869 PGM T07.3

MODE SELECTION

Mode

I/O

Power

Read

OUT

Active

Write

Active

Standby and Write Inhibit

High Z Standby

Write Inhibit

3869 PGM T09

A.C. CONDITIONS OF TEST

Input Pulse Levels

0V to 3V

Input Rise and
Fall Times

5ns

Input and Output
Timing Levels

1.5V

3869 PGM T08.1

EQUIVALENT A.C. LOAD CIRCUIT

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

Note:

(3) This parameter is periodically sampled and not 100%

tested.

3869 FHD F20.3

1.92K

30pF

OUTPUT

1.37K

X28VC256

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Read Cycle Limits

X28VC256-45

X28VC256-55

X28VC256-70 X28VC256-90

40

C to 85

55

C to 125

C 55

C to 125

C 55

C to 125

Symbol

Parameter

Min. Max.

Min.

Max. Units

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

(4)

LOW to Active Output

OLZ (4)

LOW to Active Output

(4)

HIGH to High Z Output

OHZ (4)

HIGH to High Z Output

Output Hold From Address Change

3869 PGM T10.1

Read Cycle

3869 FHD F05

Notes: (4)

min., t

, t

OLZ

min. and t

OHZ

are periodically sampled and not 100% tested, t

and t

OHZ

are measured, with CL = 5pF,

from the point whin

return HIGH (whichever occurs first) to the time when the outputs are no longer driven.

tCE

tRC

ADDRESS

DATA VALID

tOE

tLZ

tOLZ

tOH

tAA

tHZ

tOHZ

DATA I/O

VIH

HIGH Z

X28VC256

Write Cycle Limits

Symbol

Parameter

Min.

Typ.

(5)

Max.

Units

WC(6)

Write Cycle Time

Address Setup Time

Address Hold Time

Write Setup Time

Write Hold Time

Pulse Width

OES

HIGH Setup Time

OEH

HIGH Hold Time

Pulse Width

WPH(7)

HIGH Recovery (page write only)

Data Valid

Data Setup

Data Hold

DW(7)

Delay to Next Write after Polling is True

BLC

Byte Load Cycle

0.150

100

3869 PGM T11.2

Controlled Write Cycle

3869 FHD F06

Notes: (5) Typical values are for T

= 25

C and nominal supply voltage.

(6) t

is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum

time the device requires to automatically complete the internal write operation.

(7) t

WPH

and t

are periodically sampled and not 100% tested.

ADDRESS

tAS

tWC

tAH

tOES

tDS

tDH

tOEH

DATA IN

DATA OUT

HIGH Z

DATA VALID

tCS

tCH

tWP

X28VC256

Controlled Write Cycle

3869 FHD F07

Page Write Cycle

3869 FHD F08

Notes: (8) Between successive byte writes within a page write operation,

can be strobed LOW: e.g. this can be done with

and

HIGH to fetch data from another memory device within the system for the next write; or with

HIGH and

LOW effectively

performing a polling operation.

(9) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform

to either the

controlled write cycle timing.

ADDRESS

tAS

tWC

tAH

tOES

tCS

tDS

tDH

tCH

DATA IN

DATA OUT

HIGH Z

DATA VALID

tCW

tOEH

(8)

BYTE 0

BYTE 1

BYTE 2

BYTE n

BYTE n+1

BYTE n+2

tWP

tWPH

tBLC

tWC

ADDRESS*

(9)

I/O

*For each successive write within the page write operation, A7A14 should be the same or

writes to an unknown address could occur.

LAST BYTE

X28VC256

0.021 (0.53)

0.013 (0.33)

0.420 (10.67)

0.050 (1.27) TYP.

TYP. 0.017 (0.43)

0.045 (1.14) x 45

0.300 (7.62)

REF.

0.453 (11.51)

0.447 (11.35)

TYP. 0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

TYP. 0.490 (12.45)

PIN 1

0.400

(10.16)

REF.

0.553 (14.05)

0.547 (13.89)

TYP. 0.550 (13.97)

0.595 (15.11)

0.585 (14.86)

TYP. 0.590 (14.99)

TYP.

0.048 (1.22)

0.042 (1.07)

0.140 (3.56)

0.100 (2.45)

TYP. 0.136 (3.45)

0.095 (2.41)

0.060 (1.52)

0.015 (0.38)

SEATING PLANE

0.004 LEAD

CO PLANARITY

3926 Fhd F13

32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J

NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY

3926 FHD F13

PACKAGING INFORMATION

X28VC256

0.2980 (7.5692)

0.2920 (7.4168)

0.4160 (10.5664)

0.3980 (10.1092)

0.0192 (0.4877)

0.0138 (0.3505)

0.0160 (0.4064)

0.0100 (0.2540)

0.050 (1.270)

BSC

0.7080 (17.9832)

0.7020 (17.8308)

0.0110 (0.2794)

0.0040 (0.1016)

0.1040 (2.6416)

0.0940 (2.3876)

0.0350 (0.8890)

0.0160 (0.4064)

0.0125 (0.3175)

0.0090 (0.2311)

X 45

3926 FHD F17

28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED "KOREA"
4. CONTROLLING DIMENSION: INCHES (MM)

SEATING PLANE

BASE PLANE

PACKAGING INFORMATION

X28VC256

0.150 (3.81) BSC

0.458 (11.63)

0.442 (11.22)

PIN 1

3926 FHD F14

0.020 (0.51) x 45

REF.

0.095 (2.41)

0.075 (1.91)

0.022 (0.56)

0.006 (0.15)

0.055 (1.39)

0.045 (1.14)

TYP. (4) PLCS.

0.040 (1.02) x 45

REF.

TYP. (3) PLCS.

0.050 (1.27) BSC

0.028 (0.71)

0.022 (0.56)

(32) PLCS.

0.200 (5.08)

BSC

0.558 (14.17)

0.088 (2.24)

0.050 (1.27)

0.120 (3.05)

0.060 (1.52)

PIN 1 INDEX CORNER

32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E

NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE:

1% NLT

0.005 (0.127)

0.300 (7.62)

BSC

0.015 (0.38)

MIN.

0.400 (10.16)

BSC

0.560 (14.22)

0.540 (13.71)

DIA.

0.015 (0.38)

0.003 (0.08)

PACKAGING INFORMATION

X28VC256

PACKAGING INFORMATION

3926 ILL F38.1

8.02 (0.315)

7.98 (0.314)

1.18 (0.046)
1.02 (0.040)

0.17 (0.007)
0.03 (0.001)

0.26 (0.010)

0.14 (0.006)

0.50 (0.0197) BSC

0.58 (0.023)
0.42 (0.017)

14.15 (0.557)
13.83 (0.544)

12.50 (0.492)

12.30 (0.484)

PIN #1 IDENT.
O 0.76 (0.03)

SEATING
PLANE

SEE NOTE 2

0.50 ± 0.04

(0.0197 ± 0.0016)

0.30 ± 0.05

(0.012 ± 0.002)

14.80 ± 0.05

(0.583 ± 0.002)

1.30 ± 0.05

(0.051 ± 0.002)

0.17 (0.007)
0.03 (0.001)

TYPICAL

32 PLACES

15 EQ. SPC. 0.50 ± 0.04

0.0197 ± 0.016 = 7.50 ± 0.06

(0.295 ± 0.0024) OVERALL

TOL. NON-CUMULATIVE

SOLDER PADS

FOOTPRINT

NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T

X28VC256

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.

U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

ORDERING INFORMATION

Device

Access Time
45 = 45ns
55 = 55ns
70 = 70ns
90 = 90ns

Temperature Range
Blank = Commercial = 0

C to +70

I = Industrial = 40

C to +85

M = Military = 55

C to +125

MB = MIL-STD-883

Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Lead Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP

X28VC256 X X -X

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X28VC256DI-45

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X28VC256DI-45