Preliminary Information

Characteristics subject to change without notice.

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X3100/X3101

FUNCTIONAL DIAGRAM

Protection Circuit

Timing Control

& Configuration

OVT UVT OCT

FET Control

Circuitry

4 kbit

EEPROM

Analog

MUX

SPI

I/F

5VDC

Regulator

Internal Voltage Regulator

Power On reset &

Status Register

VSS

VCELL1

CB1

VCC

RGP

OVP/LMON

UVP/OCP

AS0
AS1
AS2

SCK

CB3

CB2

CB4

VCELL2

VCELL3

VCELL4/VSS

Protection

Sample Rate

Timer

RGC RGO

Configuration

Over-current

Protection &

Current Sense

VCS1 VCS2

Over-charge

Over-discharge

Protection

Sense

Circuits

Control

FEATURE

· Software Selectable Protection Levels and

Variable Protect Detection/Release Times

· Integrated FET Drive Circuitry
· Cell Voltage and Current Monitoring
· 0.5% Accurate Voltage Regulator
· Integrated 4kbit EEPROM
· Flexible Power Management with 1µA Sleep

Mode

· Cell Balancing Control

BENEFIT

· Optimize protection for chosen cells to allow

maximum use of pack capacity.

· Reduce component count and cost
· Simplify implementation of gas gauge
· Accurate voltage and current measurements
· Record battery history to optimize gas gauge,

track pack failures and monitor system use

· Reduce power to extend battery life
· Increase battery capacity and improve cycle life

battery life

PPLICATION

OTE

A V A I L A B L E

3 or 4 Cell Li-Ion BATTERY PACKS

DESCRIPTION

The X3100 is a protection and monitor IC for use in
battery packs consisting of 4 series Lithium-Ion
battery cells. The X3101 is designed to work in 3 cell
applications. Both devices provide internal over-
charge, over-discharge, and over-current protection
circuitry, internal EEPROM memory, an internal
voltage regulator, and internal drive circuitry for
external FET devices that control cell charge,
discharge, and cell voltage balancing.

Over-charge, over-discharge, and over-current
thresholds reside in an internal EEPROM memory
register and are selected independently via software
using a 3MHz SPI serial interface. Detection and time-
out delays can also be individually varied using
external capacitors.

Using an internal analog multiplexer, the X3100 or
X3101 allow battery parameters such as cell voltage
and current (using a sense resistor) to be monitored
externally by a separate microcontroller with A/D
converter. Software on this microcontroller implements
gas gauge and cell balancing functionality in software.

The X3100 and X3101 contain a current sense
amplifier. Selectable gains of 10, 25, 80 and 160 allow
an external 10 bit A/D converter to achieve better
resolution than a more expensive 14 bit converter.

An internal 4kbit EEPROM memory featuring
IDLock

, allows the designer to partition and "lock in"

written battery cell/pack data.

The X3100 and X3101 are each housed in a 28 Pin
TSSOP package.

Preliminary

3 or 4 Cell Li-Ion Battery Protection and Monitor IC

4 cell / 3 cell

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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PRINCIPLES OF OPERATION

The X3100 and X3101 provide two distinct levels of
functionality and battery cell protection:

First, in Normal mode, the device periodically checks
each cell for an over-charge and over-discharge state,
while continuously watching for a pack over-current
condition. A protection mode violation results from an
over-charge, over-discharge, or over-current state. The
thresholds for these states are selected by the user
through software. When one of these conditions occur, a
Discharge FET or a Charge FET or both FETs are
turned off to protect the battery pack. In an over-
discharge condition, the X3100 and X3101 devices go
into a low power sleep mode to conserve battery power.
During sleep, the voltage regulator turns off, removing
power from the microcontroller to further reduce pack
current.

Second, in Monitor mode, a microcontroller with A/D
converter measures battery cell voltage and pack current
via pin AO and the X3100 or X3101 on-board MUX. The
user can thus implement protection, charge/discharge,
cell balancing or gas gauge software algorithms to suit
the specific application and characteristics of the cells
used. While monitoring these voltages, all protection
circuits are on continuously.

In a typical application, the microcontroller is also
programmed to provide an SMBus interface along with
the Smart Battery System interface protocols. These
additions allow an X3100 or X3101 based module to
adhere to the latest industry battery pack standards.

PIN CONFIGURATION

PIN NAMES

PIN DESCRIPTIONS

Battery Cell Voltage (VCELL1-VCELL4):

These pins are used to monitor the voltage of each
battery cell internally. The voltage of an individual cell
can also be monitored externally at pin AO.

The X3100 monitors 4 battery cells. The X3101 monitors
3 battery cells. For the X3101 device connect the
VCELL4/VSS pin to ground.

VCC

RGP

RGC

RGO

VCELL1

CB1

VCELL2

CB2

28 Lead TSSOP

UVP/OCP

OVP/LMON

SCK

VCELL3

CB3

VCELL4/VSS*

CB4

X3100/

AS2

AS1

VSS

VCS1

VCS2

OVT

AS0

UVT

OCT

X3101

*For X3101, Connect to ground.

Pin

Symbol

Description

VCELL1 Battery cell 1 voltage input

CB1

Cell balancing FET control output 1

VCELL2 Battery cell 2 voltage

CB2

Cell balancing FET control output 2

VCELL3 Battery cell 3 voltage

CB3

Cell balancing FET control output 3

VCELL4/

VSS

Battery cell 4 voltage (X3100)
Ground (X3101)

CB4

Cell balancing FET control output 4

Ground

VCS1

Current sense voltage pin 1

VCS2

Current sense voltage pin 2

OVT

Over-charge detect/release time input

UVT

Over-discharge detect/release time input

OCT

Over-current detect/release time input

Analog multiplexer output

AS0

Analog output select pin 0

AS1

Analog output select pin 1

AS2

Analog output select pin 2

Serial data input

Serial data output

SCK

Serial data clock input

Chip select input pin

OVP/

LMON

Over-charge Voltage Protection output/
Load Monitor output

UVP/

OCP

Over-discharge protection output/
Over-current protection output

RGO

Voltage regulator output pin

RGC

Voltage regulator control pin

RGP

Voltage regulator protection pin

Power supply

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Cell Voltage Balancing Control (CB1-CB4):

These outputs are used to switch external FETs in order
to perform cell voltage balancing control. This function
can be used to adjust individual cell voltages (e.g.
during cell charging). CB1CB4 can be driven high
(Vcc) or low (Vss) to switch external FETs ON/OFF. When
using the X3101, the CB4 pin can be left unconnected,
or the FET control can be used for other purposes.

Current Sense Inputs (VCS1VCS2):

A sense resistor (R

SENSE

) is connected between VCS1

and VCS2 (Figure 1). R

SENSE

has a resistance in the

order of 20m

to 100m

, and is used to monitor current

flowing through the battery terminals, and protect
against over-current conditions. The voltage at each end
of R

SENSE

can also be monitored at pin AO.

Over-charge Voltage detect Time control (OVT):

This pin is used to control the delay time (T

)

associated with the detection of an over-charge
condition (see section "Over-charge Protection" on page
13).

Over-discharge detect/release time control (UVT):

This pin is used to control the delay times associated
with the detection (T

) and release (T

UVR

) of an over-

discharge (under-voltage) condition (see section "Over-
discharge Protection" on page 15).

Over-current detect/release time control (OCT):

This pin is used to control the delay times associated
with the detection (T

) and release (T

OCR

) of an over-

current condition (see section "Over-Current Protection"
on page 18).

Analog Output (AO):

The analog output pin is used to externally monitor
various battery parameter voltages. The voltages which
can be monitored at AO (see section "Analog
Multiplexer Selection" on page 20) are:

Individual cell voltages

Voltage across the current sense resistor (R

SENSE

)

This voltage is amplified with a gain set by the user in
the control register (see section "Current Monitor
Function" on page 20.)

The analog select pins pins AS0AS2 select the desired
voltage to be monitored on the AO pin.

Analog Output Select (AS0AS2):

These pins select which voltage is to be multiplexed to
the output AO (see section "Sleep Control (SLP)" on
page 10 and section "Current Monitor Function" on
page 20)

Serial Input (SI):

SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the device are input
on this pin.

Serial Output (SO):

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock. While CS is HIGH,
SO will be in a High Impedance state.

Note:

SI and SO may be tied together to form one line

(SI/SO). In this case, all serial data communication with
the X3100 or X3101 is undertaken over one I/O line.
This is permitted ONLY if no simultaneous read/write
operations occur.

Serial Clock (SCK):

The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.

Chip Select (CS):

When CS is HIGH, the device is deselected and the SO
output pin is at high impedance. CS LOW enables the
SPI serial bus.

Over-charge Voltage Protection/Load Monitor
(OVP/LMON):

This one pin performs two functions depending upon
the present mode of operation of the X3100 or X3101.

--Over-charge Voltage Protection (OVP)

This pin controls the switching of the battery pack charge
FET. This power FET is a P-channel device. As such,
cell charge is possible when OVP/LMON=V

, and cell

charge is prohibited when OVP/LMON=V

. In this

configuration the X3100 and X3101 turn off the charge
voltage when the cells reach the over-charge limit. This
prevents damage to the battery cells due to the
application of charging voltage for an extended period of
time (see section "Over-charge Protection" on page 13).

X3100/X3101 Preliminary Information

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--Load Monitor (LMON)

In Over-current Protection mode, a small test current
(7.5µA typ.) is passed out of this pin to sense the load
resistance. The measured load resistance determines
whether or not the X3100 or X3101 returns from an
over-current protection mode (see section "Over-Current
Protection" on page 18).

Over-discharge (Under Voltage) Protection/
Over-current Protection (UVP/OCP):

Pin UVP/OCP controls the battery cell discharge via an
external power FET. This P-channel FET allows cell
discharge when UVP/OCP=Vss, and prevents cell
discharge when UVP/OCP=Vcc. The X3100 and X3101
turn the external power FET off when the X3100 or
X3101 detects either:

--Over-discharge Protection (UVP)

In this case, pin 24 is referred to as "Over-discharge
(Under-Voltage) protection (UVP)" (see section "Over-
discharge Protection" on page 15). UVP/OCP turns off
the FET to prevent damage to the battery cells by being
discharged to excessively low voltages.

--Over-current protection (OCP)

In this case, pin 24 is referred to as "Over-current
protection (OCP)" (see section "Over-Current Protection"
on page 18). UVP/OCP turns off the FET to prevent
damage to the battery pack caused by excessive current
drain (e.g. as in the case of a surge current resulting
from a stalled disk drive).

TYPICAL APPLICATION CIRCUIT

The X3100 and X3101 have been designed to operate
correctly when used as connected in the Typical
Application Circuit (see Figure 1 on page 5).

The power MOSFET's Q1 and Q2 are referred to as the
"Discharge FET" and "Charge FET," respectively. Since
these FETs are p-channel devices, they will be ON when
the gates are at V

, and OFF when the gates are at

. As their names imply, the discharge FET is used to

control cell discharge, while the charge FET is used to
control cell charge. Diode D1 allows the battery cells to
receive charge even if the Discharge FET is OFF, while
diode D2 allows the cells to discharge even if the charge
FET is OFF. D1 and D2 are integral to the Power FETs. It
should be noted that the cells can neither charge nor
discharge if both the charge FET and discharge FET are
OFF.

Power to the X3100 or X3101 is applied to pin VCC via
diodes D6 and D7. These diodes allow the device to be

powered by the Li-Ion battery cells in normal operating
conditions, and allow the device to be powered by an
external source (such as a charger) via pin P+ when the
battery cells are being charged. These diodes should
have sufficient current and voltage ratings to handle both
cases of battery cell charge and discharge.

The operation of the voltage regulator is described in
section "Voltage Regulator" on page 21. This regulator
provides a 5VDC±0.5% output. The capacitor (C1)
connected from RGO to ground provides some noise
filtering on the RGO output. The recommended value is
0.1µF or less. The value chosen must allow V

RGO

decay to 0.1V in 170ms or less when the X3100 or
X3101 enter the sleep mode. If the decay is slower than
this, a resistor (R1) can be placed in parallel with the
capacitor.

During an initial turn-on period (T

PUR

+ T

), V

RGO

has

a stable, regulated output in the range of 5VDC ± 10%
(see Figure 2). The selection of the microcontroller
should take this into consideration. At the end of this turn
on period, the X3100 and X3101 "self-tunes" the output
of the voltage regulator to 5V+/-0.5%. As such, V

RGO

can be used as a reference voltage for the A/D converter
in the microcontroller. Repeated power up operations,
consistently re-apply the same "tuned" value for V

RGO

Figure 1 shows a battery pack temperature sensor
implemented as a simple resistive voltage divider,
utilizing a thermistor (R

) and resistor (R

'). The voltage

can be fed to the A/D input of a microcontroller and

used to measure and monitor the temperature of the
battery cells. R

' should be chosen with consideration of

the dynamic resistance range of R

as well as the input

voltage range of the microcontroller A/D input. An output
of the microcontroller can be used to turn on the
thermistor divider to allow periodic turn-on of the sensor.
This reduces power consumption since the resistor
string is not always drawing current.

Diode D3 is included to facilitate load monitoring in an
Over-current protection mode (see section "Over-
Current Protection" on page 18), while preventing the
flow of current into pin OVP/LMON during normal
operation. The N-Channel transistor turns off this
function during the sleep mode.

Resistor R

is connected across the gate and drain of

the charge FET (Q2). The discharge FET Q1 is turned
off by the X3100 or X3101, and hence the voltage at pin
OVP/LMON will be (at maximum) equal to the voltage of
the battery terminal, minus one forward biased diode
voltage drop (V

P+

). Since the drain of Q2 is

connected to a higher potential (V

P+

) a pull-up resistor

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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VCS1

VCS2

UVT

OCT

VCELL1

CB1

CB3

VCELL4/V

VCELL3

X3100/X3101

CB2

RGP

RGC

RGO

VP/

UVP/

µC

ASIC

100

0.01uF

LMT

LMON

P+

P-

VCELL2

SENSE

3 or 4

Li-Ion cells

Discharge FET

Charge FET

RGO

CB4

B+

B-

OCP

0.1µF

1µF

r
ansistor Recommendations

Q1, Q2 = Si4435

Q3 = 2N3906

Q4 - Q10 = 2N7002

POR

AS0

AS1

AS2

SCK

LMON

SMBCLK

SMBD

100

FETs Q4 and Q5 are needed

only if e

xter

nal pull-ups on

the SMBus lines cause

oltage to appear at the uC

Vcc pin dur

ing sleep mode

T54

A/D

A/D Input

Reset

I/O

Set High

after power

up to enable

SMBus and

LMON

Choose R1 and

C1 such that

RGO

goes to

0.1V (or less) in

170ms (or less)

when entering

the Sleep Mode

(at 25

C).

or the X3101, or X3100

when 3 cells are used,

VCELL4/V

MUST be

tied to Ground (Vss).

CB4

is left unconnected.

Ref

(Optional)

Figure 1. Typical Application Circuit

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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) in the order of 1M

should be used to ensure that

the charge FET is completely turned OFF when OVP/
LMON=V

The capacitors on the V

CELL1

to V

CELL4

inputs are used

in a first order low pass filter configuration, at the battery
cell voltage monitoring inputs (VCELL1VCELL4) of the
X3100 or X3101. This filter is used to block any
unwanted interference signals from being inadvertently
injected into the monitor inputs. These interference
signals may result from:

Transients created at battery contacts when the bat-

tery pack is being connected/disconnected from the
charger or the host.

Electrostatic discharge (ESD) from something/some-

one touching the battery contacts.

Unfiltered noise that exists in the host device.

RF signals which are induced into the battery pack

from the surrounding environment.

Such interference can cause the X3100 or X3101 to
operate in an unpredictable manner, or in extreme
cases, damage the device. As a guide, the capacitor
should be in the order of 0.01µF and the resistor, should
be in the order of 10K

The capacitors should be of the

ceramic type. In order to minimize interference, PCB
tracks should be made as short and as wide as possible
to reduce their impedance. The battery cells should also
be placed as close to the X3100 or X3101 monitor inputs
as possible.

Resistors R

and the associated n-channel MOSFET's

) are used for battery cell voltage balancing. The

X3100 and X3101 provide internal drive circuitry which
allows the user to switch FETs Q

ON or OFF via

the microcontroller and SPI port (see section "Cell
Voltage Balance Control (CBC1-CBC4)" on page 11).
When any of the these FETs are switched ON, a
current, limited by resistor R

, flows across the

particular battery cell. In doing so, the user can control
the voltage across each individual battery cell. This is
important when using Li-Ion battery cells since
imbalances in cell voltages can, in time, greatly reduce
the usable capacity of the battery pack. Cell voltage
balancing may be implemented in various ways, but is
usually performed towards the end of cell charging
("Top-of-charge method"). Values for R

will vary

according to the specific application.

The internal 4kbit EEPROM memory can be used to
store the cell characteristics for implementing such
functions as gas gauging, battery pack history, charge/

discharge cycles, and minimum/maximum conditions.
Battery pack manufacturing data as well as serial
number information can also be stored in the EEPROM
array. An SPI serial bus provides the communication link
to the EEPROM.

A current sense resistor (R

SENSE

) is used to measure

and monitor the current flowing into/out of the battery
terminals, and is used to protect the pack from over-
current conditions (see section "Over-Current
Protection" on page 18). R

SENSE

is also used to

externally monitor current via a microcontroller (see
section "Current Monitor Function" on page 20).

FETs Q4 and Q5 may be required on general purpose
I/Os of the microcontroller that connect outside of the
package. In some cases, without FETs, pull-up resistors
external to the pack force a voltage on the V

pin of the

microcontroller during a pack sleep condition. This
voltage can affect the proper tuned voltage of the
X3100/X3101 regulator. These FETs should be turned-
on by the microcontroller. (See Figure 1.)

POWER ON SEQUENCE

Initial connection of the Li-Ion cells in the battery pack
will not normally power up the battery pack. Instead, the
X3100 or X3101 enters and remains in the SLEEP
mode. To exit the SLEEP mode, after the initial power up
sequence, or following any other SLEEP MODE, a
minimum of 16V (X3100 V

SLR

) or 12V (X3101 V

SLR

) is

applied to the VCC pin, as would be the case during a
battery charge condition. (See Figure 2.)

When V

SLR

is applied to VCC, the analog select pins

(AS2-AS0) and the SPI communication pins (CS, CLK,
SI, SO) must be low, so the X3100 and X3101 power up
correctly into the normal operating mode. This can be
done by using a power-on reset circuit.

When entering the normal operating mode, either from
initial power up or following the SLEEP MODE, all bits in
the control register are zero. With UVPC and OVPC bits
at zero, the charge and discharge FETs are off. The
microcontroller must turn these on to activate the pack.
The microcontroller would typically check the voltage
and current levels prior to turning on the FETs via the
SPI port. The software should prevent turning on the
FETs throughout an initial measurement/calibration
period. The duration of this period is T

+200ms or

+200ms, whichever is longer.

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Figure 2. Power Up Timing (Initial Power Up or after Sleep Mode)

VCC

RGO

2ms (Typ.)

PUR

5V±10% (Stable and Repeatable)

RGO

Tuned to 5V±0.5%

VRGS

Voltage Regulator Output Status

OCDS

Over-current Detection Status

VRGS+OCDS

1 = X3100/1 in Over-Current Protection Mode

0 = X3100/1 NOT in Over-Current Protection Mode

0 = X3100/1 NOT in Over-Current Protection Mode AND VRGO Tuned

1 = X3100/1 in Over-Current Protection Mode OR VRGO Not Yet Tuned

Status Register Bit 0

SLR

AS2_AS0

(Internal Signal)

CCES+OVDS

Status Register Bit 2

(SWCEN=0)

OVDS

Status Register Bit 2

(SWCEN=1)

+200ms

SPI PORT

+200ms OR T

+200ms (whichever is longer)

0 = V

CELL

> V

OR X3100/1 NOT in Over-charge Protection Mode

1 = V

CELL

< V

OR X3100/1 in Over-charge Protection Mode

0 = X3100/1 NOT in Over-charge Protection Mode

1 = X3100/1 in Over-charge Protection Mode

Microcontroller

Charge, Discharge FETs can be

turned on here.

Any Read or Write Operation, except

turn-on of FETs can start here.

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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CONFIGURATION REGISTER

The X3100 and X3101 can be configured for specific
user requirements using the Configuration Register.

Table 1. Configuration Register Functionality

Table 2. Configuration Register--Upper Byte

Table 3. Configuration Register--Lower Byte

Over-charge Voltage Settings

VOV1 and VOV0 control the cell over-charge level. See
section "Over-charge Protection" on page 13.

Table 4.

Over-charge Voltage Threshold Selection

Over-discharge Settings

VUV1 and VUV0 control the cell over-discharge (under
voltage threshold) level. See section "Over-discharge
Protection" on page 15.

Over-current Settings

VOC1 and VOC0 control the pack over-current level.
See section "Over-Current Protection" on page 18.

Table 6.

Over-Current Threshold Voltage Selection.

Cell Charge Enable Settings

VCE1, VCE0 and SWCEN control the pack charge
enable function. SWCEN enables or disables a circuit
that prevents charging if the cells are at too low a
voltage. VCE1 and VCE0 select the voltage that is
recognized as too low. See section "Sleep Mode" on
page 15.

Table 7. Cell Charge Enable Function

Bit(s)

Name

Function

0-5

(don't care)

SWCEN

Switch Cell Charge Enable
threshold function ON/OFF

CELLN

Set the number of Li-Ion battery
cells used (3 or 4)

8-9

VCE1-VCE0

Select Cell Charge Enable
threshold

10-11

VOC1-VOC0 Select over-current threshold

12-13

VUV1-VUV0

Select over-discharge (under
voltage) threshold

14-15

VOV1-VOV0

Select over-charge voltage
threshold

VOV1

VOV0

VUV1

VUV0

VOC1

VOC0

VCE1

VCE0

X3100 Default = 30H; X3101 Default = 00H.

CELLN

SWCEN

X3100 Default = C0H; X3101 Default = 40H.

Configuration Register

Bits

Operation

VOV1

VOV0

= 4.20V (Default)

= 4.25V

= 4.30V

= 4.35V

Table 5. Over-discharge Threshold Selection.

Configuration

Register Bits

Operation

VUV1

VUV0

X3100

X3101

=1.95V

=2.25V

(X3101 default)

=2.05V

=2.35V

=2.15V

=2.45V

=2.25V

(X3100 default)

=2.55V

Configuration Register Bits

Operation

VOC1

VOC0

=0.075V (Default)

=0.100V

=0.125V

=0.150V

Configuration

Register Bit

Operation

SWCEN

Charge enable function: ON

Charge enable function: OFF

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Table 8.

Cell Charging Threshold Voltage Selection.

Cell Number Selection

The X3100 is designed to operate with four (4) Li-Ion
battery cells. The X3101 is designed to operate with
three (3) Li-Ion battery cells. The CELLN bit of the
configuration register (Table 9) sets the number of cells
recognized. For the X3101, the value for CELLN should
always be zero.

Table 9. Selection of Number of Battery Cells

The configuration register consists of 16 bits of
NOVRAM memory (Table 2, Table 3). This memory
features a high-speed static RAM (SRAM) overlaid bit-
for-bit with non-volatile "Shadow" EEPROM. An
automatic array recall operation reloads the contents of
the shadow EEPROM into the SRAM configuration
register upon power-up (Figure 3).

Figure 3. Power up of

Configuration Register

The configuration register is designed for unlimited write
operations to SRAM, and a minimum of 1,000,000 store
operations to the EEPROM. Data retention is specified
to be greater than 100 years.

It should be noted that the bits of the shadow EEPROM
are for the dedicated use of the configuration register,
and are NOT part of the general purpose 4kbit
EEPROM array.

he WCFIG command writes to the configuration

After writing to this register using a WCFIG instruction,
data will be stored only in the SRAM of the configuration
register. In order to store data in shadow EEPROM, a
WREN instruction, followed by a EEWRITE to any
address of the 4kbit EEPROM memory array must
occur, see Figure 4. This sequence initiates an internal
nonvolatile write cycle which permits data to be stored
in the shadow EEPROM cells. It must be noted that
even though a EEWRITE is made to the general
purpose 4kbit EEPROM array, the value and address to
which it is written, is unimportant. If this procedure is not
followed, the configuration register will power up to the
last previously stored values following a power down
sequence.

Configuration Register Bits

Operation

VCE1

VCE0

= 0.5V

= 0.80V

= 1.10V

= 1.40V

Configuration

Register Bit

Operation

CELLN

4 Li-Ion battery cells (X3100 default)

3 Li-Ion battery cells (X3100 or X3101)

In the case that the X3100 or X3101 is configured for use with
only three Li-Ion battery cells (i.e. CELLN=0), then VCELL4 (pin
7) MUST be tied to Vss (pin 9) to ensure correct operation.

Configuration Register (SRAM)

Shadow EEPROM

Recall

Upper Byte

Lower Byte

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Figure 4. Writing to Configuration Register

CONTROL REGISTER

The Control Register is realized as two bytes of volatile
RAM (Table 10, Table 11). This register is written using
the WCNTR instruction, see Table 30 and section "X3100/
X3101 SPI Serial Communication" on page 22.

Table 10. Control Register--Upper Byte

Table 11. Control Register--Lower Byte

Since the control register is volatile, data will be lost
following a power down and power up sequence. The
default value of the control register on initial power up
or when exiting the SLEEP MODE is 00h (for both
upper and lower bytes respectively). The functions that
can be manipulated by the Control Register are shown
in Table 12.

Table 12. Control Register Functionality

Sleep Control (SLP)

Setting the SLP bit to `1' forces the X3100 or X3101 into
the sleep mode, if V

< V

SLP

. See section "Sleep

Mode" on page 15.

Table 13. Sleep Mode Selection

CBC4

CBC3

CBC2

CBC1

UVPC

OVPC

CSG1

CSG0

SLP

Configuration Register

(SRAM=old value)

Write

Enable

Write to

4kbit EEPROM

Power Down

Power Up

Store

(New Value)

in Shadow

EEPROM

Configuration Register

(SRAM=Old Value)

WCFIG (New Value)

Data Recalled

YES

WREN

EEWRITE

Configuration Register

(SRAM=New Value)

Power Up

Configuration Register

(Sram=New Value)

from Shadow

EEPROM to SRAM

Data Recalled
from Shadow
EEPROM to SRAM

Power Down

Power Up

Bit(s)

Name

Function

0-4

(don't care)

5,6

0, 0

Reserved--write 0 to these locations.

SLP

Select sleep mode.

8,9

CSG1,

CSG0

Select current sense voltage gain

OVPC

OVP control: switch pin OVP = V

UVPC

UVP control: switch pin UVP = V

CBC1

CB1 control: switch pin CB1 = V

CBC2

CB2 control: switch pin CB2 = V

CBC3

CB3 control: switch pin CB3 = V

CBC4

CB4 control: switch pin CB4 = V

Control Register Bits

Operation

SLP

Normal operation mode

Device enters Sleep mode

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Current Sense Gain (CSG1, CSG0)

These bits set the gain of the current sense amplifier.
These are x10, x25, x80 and x160. For more detail, see
section "Current Monitor Function" on page 20.

Table 14. Current Sense Gain Control

Charge/Discharge Control (OVPC, UVPC)

The OVPC and UVPC bits allow control of cell charge
and discharge externally, via the SPI port. These bits
control the OVP/LMON and UVP/OCP pins, which in turn
control the external power FETs.

Using P-channel power FETs ensures that the FET is
on when the pin voltage is low (Vss), and off when the
pin voltage is high (Vcc).

OVP/LMON and UVP/OCP can be controlled by using
the WCNTR Instruction to set bits OVPC and UVPC in
the Control register (See page 10).

Table 15. UVP/OVP Control

It is possible to set/change the values of OVPC and
UVPC during a protection mode. A change in the state
of the pins OVP/LMON and UVP/OCP, however, will not
take place until the device has returned from the
protection mode.

Cell Voltage Balance Control (CBC1-CBC4)

This function can be used to adjust individual battery
cell voltage during charging. Pins CB1CB4 are used to
control external power switching devices. Cell voltage
balancing is achieved via the SPI port.

Table 16. CB1--CB4 Control

CB1CB4 can be controlled by using the WCNTR In-
struction to set bits CBC1CBC4 in the control register
(Table 16).

STATUS REGISTER

The status of the X3100 or X3101 can be verified by
using the RDSTAT command to read the contents of the
Status Register (Table 17).

Table 17. Status Register.

The function of each bit in the status register is shown
in Table 18.

Bit 0 of the status register (VRGS+OCDS) actually
indicates the status of two conditions of the X3100 or
X3101. Voltage Regulator Status (VRGS) is an
internally generated signal which indicates that the
output of the Voltage Regulator (VRGO) has reached an
output of 5VDC ± 0.5%. In this case, the voltage
regulator is said to be "tuned". Before the signal VRGS
goes low (i.e. before the voltage regulator is tuned), the
voltage at the output of the regulator is nominally 5VDC
± 10% (See section "Voltage Regulator" on page 21.)
Over-current Detection Status (OCDS) is another
internally generated signal which indicates whether or
not the X3100 or X3101 is in over-current protection
mode.

Signals VRGS and OCDS are logically OR'ed together
(VRGS+OCDS) and written to bit 0 of the status register
(See Table 18, Table 17 and Figure 2).

Control Register Bits

Operation

CSG1

CSG0

Set current sense gain=x10

Set current sense gain=x25

Set current sense gain=x80

Set current sense gain=x160

Control Register Bits

Operation

OVPC

UVPC

Pin OVP=V

(FET ON)

Pin OVP=V

(FET OFF)

Pin UVP=V

(FET ON)

Pin UVP=V

(FET OFF)

Control Register Bits

Operation

CBC4

CBC3

CBC2

CBC1

Set CB1=V

(ON)

Set CB1=V

(OFF)

Set CB2=V

(ON)

Set CB2=V

(OFF)

Set CB3=V

(ON)

Set CB3=V

(OFF)

Set CB4=V

(ON)

Set CB4=V

(OFF)

CCES+

OVDS

UVDS

VRGS+

OCDS

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Bit 1 of the status register simply indicates whether or
not the X3100 or X3101 is in over-discharge protection
mode.

Bit 2 of the status register (CCES+OVDS) indicates the
status of two conditions of the X3100 or X3101. Cell
Charge Enable Status (CCES) is an internally generated
signal which indicates the status of any cell voltage
(V

CELL

) with respect to the Cell Charge Enable Voltage

). Over-charge Voltage Detection Status (OVDS) is

an internally generated signal which indicates whether

or not the X3100 or X3101 is in over-charge protection
mode.

When the cell charge enable function is switched ON
(configuration bit SWCEN=0), the signals CCES and
OVDS are logically OR'ed (CCES+OVDS) and written to
bit 2 of the status register. If the cell charge enable
function is switched OFF (configuration bit SWCEN=1),
then bit 2 of the status register effectively only represents
information about the over-charge status (OVDS) of the
X3100 or X3101 (See Table 18, Table 17 and Figure 2).

Table 18. Status Register Functionality.

Notes:

This bit is set in the configuration register.

X3100/X3101 INTERNAL PROTECTION FUNCTIONS

The X3100 and the X3101 provide periodic monitoring
(see section "Periodic Protection Monitoring" on page
12) for over-charge and over-discharge states and
continuous monitoring for an over-current state. It has
automatic shutdown when a protection mode is
encountered, as well as automatic return after the
device is released from a protection mode. When
sampling voltages through the analog port (Monitor
Mode), over-charge and over-discharge protection
monitoring is also performed on a continuous basis.

Voltage thresholds for each of these protection modes
(V

, V

, and V

respectively) can be individually

selected via software and stored in an internal non-
volatile register. This feature allows the user to avoid the
restrictions of mask programmed voltage thresholds, and
is especially useful during prototype/evaluation design

stages or when cells with slightly different
characteristics are used in an existing design.

Delay times for the detection of, and release from
protection modes (T

, T

UVR

, and T

OCR

respectively) can be individually varied by setting the
values of external capacitors connected to pins OVT,
UVT, OCT.

Periodic Protection Monitoring

In normal operation, the analog select pins are set such
that AS2=L, AS1=L, AS0=L. In this mode the X3100 and
X3101 conserve power by sampling the cells for over or
over-discharge conditions.

In this state over-charge and over-discharge protection
circuitry are usually off, but are periodically switched on
by the internal Protection Sample Rate Timer (PSRT). The

Bit(s)

Name

Description

Case

Status

Interpretation

VRGS+OCDS

Voltage regulator

status

Over-current

detection status

RGO

not yet tuned (V

RGO

=5V ± 10%) OR

X3100/X3101 in over-current protection mode.

RGO

tuned (V

RGO

=5V ± 0.5%) AND

X3100/X3101 NOT in over-current protection mode.

UVDS

Over-discharge

detection status

X3100/X3101 in over-discharge protection mode

X3100/X3101 NOT in over-discharge protection mode

CCES+OVDS

Cell charge

enable status

Over-charge

detection status

SWCEN =0

CELL

< V

X3100/X3101 in over-charge protection mode

CELL

> V

AND

X3100/X3101 NOT in over-charge protection mode

SWCEN =1

X3100/X3101 in over-charge protection mode

X3100/X3101 NOT in over-charge protection mode

Not used (always return zero)

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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over-charge and over-discharge protection circuitry is on
for approximately 2ms in each 125ms period. Over-
current monitoring is continuous. In monitor mode (see
page 20) over-charge and over-discharge monitoring is
also continuous.

Over-charge Protection

The X3100 and X3101 monitor the voltage on each
battery cell (V

CELL

). If for any cell, V

CELL

> V

for a

time exceeding T

, then the Charge FET will be

switched OFF (OVP/LMON=V

). The device has now

entered Over-charge protection mode (Figure 5). The
status of the discharge FET (via pin UVP) will remain
unaffected.

While in over-charge protection mode, it is possible to
change the state of the OVPC bit in the control register
such that OVP/LMON=Vss (Charge FET=ON).
Although the OVPC bit in the control register can be
changed, the change will not be seen at pin OVP until
the X3100 or X3101 returns from over-charge
protection mode.

The over-charge detection delay T

, is varied using a

capacitor (C

) connected between pin OVT and GND.

A typical delay time is shown in Table 10. The delay T

that results from a particular capacitance C

, can be

approximated by the following linear equation:

(s)

10 x C

(µF).

Table 19. Typical over-charge detection time

The device further continues to monitor the battery cell
voltages, and is released from over-charge protection
mode when V

CELL

< V

OVR

, for all cells. When the X3100

or X3101 is released from over-charge protection
mode, the charge FET is automatically switched ON
(OVP/LMON=V

). When the device returns from over-

charge protection mode, the status of the discharge
FET (pin UVP/OCP) remains unaffected.

The value of V

can be selected from the values

shown in Table 4 by setting bits VOV1, VOV0. These bits
are set by using the WCFIG instruction to write to the
configuration register.

Figure 5. Over-charge Protection Mode--Event Diagram

Symbol

Delay

0.1µF

1.0s (Typ)

CELL

OVP/LMON

Normal Operation Mode

Over-charge

OVR

Protection

Mode

Normal Operation Mode

Event

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Table 20. Over-charge Protection Mode--Event Diagram Description

Event

Event Description

[0,1)

-- Discharge FET is ON (UVP/OCP=V

-- Charge FET is ON (OVP/LMON=V

), and hence battery cells are permitted to receive charge.

-- All cell voltages (V

CELL

-V

CELL4

) are below the over-charge voltage threshold (V

-- The device is in normal operation mode (i.e. not in a protection mode).

[1]

-- The voltage of one or more of the battery cells (V

CELL

), exceeds V

-- The internal over-charge detection delay timer begins counting down.
-- The device is still in normal operation mode

(1,2)

The internal over-charge detection delay timer continues counting for T

seconds.

[2]

The internal over-charge detection delay timer times out

AND

CELL

still exceeds V

OV.

-- Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc).
-- The device has now entered over-charge protection mode.

(2,3)

While in over-charge protection mode:

-- The battery cells are permitted to discharge via the discharge FET, and diode D

across the charge FET

-- The X3100 or X3101 monitors the voltages V

CELL1

-V

CELL4

to determine whether or not they have all fallen

below the "Return from over-charge threshold" (V

OVR

-- (It is possible to change the status of UVP/OCP or OVP/LMON using the control register)

[3]

-- All cell voltages fall below V

OVR

--The device is now in normal operation mode.

-- The X3100/X3101 automatically switches charge FET=ON (OVP/LMON=Vss)
-- The status of the discharge FET remains unaffected.
-- Charging of the battery cells can now resume.

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Over-discharge Protection

If V

CELL

< V

, for a time exceeding T

, the cells are

said to be in a over-discharge state (Figure 6). In this
instance, the X3100 and X3101 automatically switch
the discharge FET OFF (UVP/OCP=Vcc), and then
enter sleep mode.

The over-discharge (under-voltage) value, V

, can be

selected from the values shown in Table 5 by setting
bits VUV1, VUV0 in the configuration register. These
bits are set using the WCFIG command. Once in the
sleep mode, the following steps must occur before the
X3100 or X3101 allows the battery cells to discharge:

The X3100 and X3101 must wake from sleep mode

(see section "Voltage Regulator" on page 21).

The charge FET must be switched ON by the micro-

controller (OVP/LMON=V

), via the control register

(see section "Control Register Functionality" on page
10).

All battery cells must satisfy the condition: V

CELL

UVR

for a time exceeding T

UVR

The discharge FET must be switched ON by the micro-

controller (UVP/OCP=V

), via the control register

(see section "Control Register Functionality" on page
10)

The times T

UVR

are varied using a capacitor (C

)

connected between pin UVT and GND (Table 13). The
delay T

that results from a particular capacitance C

can be approximated by the following linear equation:

(s)

10 x C

(µF)

UVR

(ms)

70 x C

(µF)

Sleep Mode

The X3100 or X3101 can enter sleep mode in two
ways:

i) The device enters the over-discharge protection mode.

ii) The user sends the device into sleep mode using the

control register.

A sleep mode can be induced by the user, by setting
the SLP bit in the control register (Table 13) using the
WCNTR Instruction.

In sleep mode, power to all internal circuitry is switched
off, minimizing the current drawn by the device to 1µA
(max). In this state, the discharge FET and the charge
FET are switched OFF (OVP/LMON=V

and UVP/

OCP=V

), and the 5VDC regulated output (V

RGO

) is

0V. Control of UVP/OCP and OVP/LMON via bits UVPC
and OVPC in the control register is also prohibited.

The device returns from sleep mode when V

SLR

(e.g. when the battery terminals are connected to a
battery charger). In this case, the X3100 or the X3101
restores the 5VDC regulated output (section "Voltage
Regulator" on page 21), and communication via the SPI
port resumes.

If the Cell Charge Enable function is enabled when V

rises above V

SLR

, the X3100 and X3101 internally

verifies that the individual battery cell voltages (V

CELL

)

are larger than the

cell charge enable voltage (V

)

before allowing the FETs to be turned on. The value
of V

is selected by using the WCFIG command to set

bits VCE1VCE0 in the configuration register.

Only if the condition "V

CELL

" is satisfied can

the state of charge and discharge FETs be changed
via the control register

. Otherwise, if V

CELL

for

any battery cell then both the Charge FET and the
discharge FET are OFF (OVP/LMON=Vcc and UVP/
OCP=V

). Thus both charge and discharge of the

battery cells via terminals P+ / P- is prohibited

The cell charging threshold function can be switched
ON or OFF by the user, by setting bit SWCEN in the
configuration register (Table 7) using the WCFIG
command. In the case that this cell charge enable
function is switched OFF, then

is effectively set to

0V.

Neither the X3100 nor the X3101 enter sleep mode
(automatically or manually, by setting the SLP bit) if V

SLR

. This is to ensure that the device does not go

into a sleep mode while the battery cells are at a high
voltage (e.g. during cell charging).

Table 21. Typical Over-discharge Delay Times

Symbol

Description

Delay

Over-discharge
detection delay

0.1µF

1.0s (Typ)

UVR

Over-discharge
release time

0.1µF

7ms (Typ)

In this case, charging of the battery may resume ONLY if the cell
charge enable function is switched OFF by setting bit SWCEN =
1 in the configuration register (See Above, "Configuration
Register Functionality" on page 8).

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Figure 6. Over-discharge Protection Mode--Event Diagram

UVR

VCELL

UVP/OCP

RGO

Over-discharge Protection Mode

Sleep Mode

UVR

Event

VCC

SLR

Cell Charge Prohibited if SWCEN=0

AND V

CELL

< V

Note 1: If SWEN=0 and V

CELL

< V

, then OVP/LMON stays high and charging is prohibited.

OVP/LMON

Note 1, 2

Note 2: OVP/LMON stays high until the microcontroller writes a "1" to the OVPC bit in the control register. This sets the signal low, which turns on the

charge FET. It cannot be turned on prior to this time.

Note 3: UVP/OCP stays high until the microcontroller writes a "1" to the UVPC bit in the control register. This sets the signal low, which turns on the

discharge FET. The FET cannot be turned on prior to this time.

Note 3

The Longer of TOV+200ms OR TUV+200ms

0.7V

Table 22. Over-discharge Protection Mode--Event Diagram Description

Event

Event Description

[0,1)

-- Charge FET is ON (OVP/LMON=V

)

-- Discharge FET is ON (UVP/OCP=V

), and hence battery cells are permitted to discharge.

-- All cell voltages (VCELL

-VCELL

) are above the Over-discharge threshold voltage (V

-- The device is in normal operation mode (i.e. not in a protection mode).

[1]

-- The voltage of one or more of the battery cells (V

CELL

), falls below V

-- The internal over-discharge detection delay timer begins counting down.
-- The device is still in normal operation mode

(1,2)

The internal over-discharge detection delay timer continues counting for T

seconds.

[2]

-- The internal over-discharge detection delay timer times out, AND V

CELL

is still below V

UV.

-- The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP=Vcc).
-- The charge FET is switched OFF (OVP/LMON=V

-- The device has now entered over-discharge protection mode.
-- At the same time, the device enters sleep mode (See section "Voltage Regulator" on page 21).

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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(2,3)

While device is in sleep (in over-discharge protection) mode:

-- The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.
-- The output of the 5VDC voltage regulator (RGO) is 0V.
-- Access to the X3100/X3101 via the SPI port is NOT possible.

[3]

Return from sleep mode (but still in over-discharge protection mode):

-- Vcc rises above the "Return from Sleep mode threshold Voltage" (V

SLR

)--This would normally occur in the

case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and
not the battery pack cells.

-- Power is returned to ALL internal circuitry
-- 5VDC output is returned to the regulator output (RGO).
-- Access is enabled to the X3100/X3101 via the SPI port.
-- The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control reg-

ister, although it will have no effect at this time).

(3,4)

If the cell charge enable func-

tion is switched ON

AND V

CELL

> V

Charge enable function is

switched OFF

-- The X3100/X3101 initiates a reset operation that takes the longer of

+200ms or T

+200ms to complete. Do not write to the FET control bits

during this time.

-- The charge FET is switched On (OVP/LMON=Vss) by the microcontroller by

writing a "1" to the OVPC bit in the control register.

-- The battery cells now receive charge via the charge FET and diode D1 across

the discharge FET (which is OFF).

-- The X3100/X3101 monitors the V

CELL

voltage to determine whether or not it

has risen above V

UVR

If the cell charge enable func-

tion is switched ON

AND

CELL

< V

-- Charge/discharge of the battery cells via P+ is no longer permitted (Charge

FET and discharge FET are held OFF).

-- (Charging may re-commence only when the Cell Charge Enable function is

switched OFF - See Sections: "Configuration Register" page 4, and "Sleep
mode" page 17.)

[4]

-- The voltage of all of the battery cells (V

CELL

), have risen above V

UVR

-- The internal Over-discharge release timer begins counting down.
-- The X3100/X3101 is still in over-discharge protection mode.

(4,5)

-- The internal over-discharge release timer continues counting for t

UVR

seconds.

-- The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t

UVR

. Other-

wise recovery is based on two successive samples about 120ms apart.

[5]

-- The internal over-discharge release timer times out, AND V

CELL

is still above V

UVR.

-- The device returns from over-discharge protection mode, and is now in normal operation mode.
-- The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep.
-- The discharge FET is can now be switched ON (UVP/OCP=V

) by the microcontroller by writing a "1" to

the UVPC bit of the control register.

-- The status of the charge FET remains unaffected (ON)
-- The battery cells continue to receive charge via the charge FET and discharge FET (both ON).

Table 22. Over-discharge Protection Mode--Event Diagram Description (Continued)

Event

Event Description

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Over-Current Protection

In addition to monitoring the battery cell voltages, the
X3100 and X3101 continually monitor the voltage VCS

(VCS

VCS

) across the current sense resistor

SENSE

). If VCS

> V

for a time exceeding T

then the device enters over-current protection mode
(Figure 7). In this mode, the X3100 and X3101
automatically switch the discharge FET OFF (UVP/
OCP=Vcc) and hence prevent current from flowing
through the terminals P+ and P-.

Figure 7. Over-Current Protection

The 5VDC voltage regulator output (V

RGO

) is always

active during an over-current protection mode.

Once the device enters over-current protection mode,
the X3100 and X3101 begin a load monitor state. In the
load monitor state, a small current (I

LMON

=7.5µA typ.) is

passed out of pin OVP/LMON in order to determine the
load resistance. The load resistance is the impedance
seen looking out of pin OVP/LMON, between terminal
P+ and pin VSS (See Figure 7.)

If the load resistance >

150k

LMON

=0µA) for a time

exceeding T

OCR

, then the X3100 or X3101 is released

from over-current protection mode. The discharge FET
is then automatically switched ON (UVP/OCP=Vss) by
the X3100 or X3101, unless the status of UVP/OCP has
been changed in control register (by manipulating bit
UVPC) during the over-current protection mode.

OCR

are varied using a capacitor (C

) connected

between pin OCT and VSS. A list of typical delay times
is shown in Table 23. Note that the value C

should be

larger than 1nF.

The delay T

and T

OCR

that results from a particular

capacitance C

can be approximated by the following

equations:

(ms)

10,000 x C

(µF)

OCR

(ms)

10,000 x C

(µF)

Table 23. Typical Over-Current Delay Times

The value of V

can be selected from the values

shown in Table 6, by setting bits VOC1, VOC0 in the
configuration register using the WCFIG command.

Note: If the Charge FET is turned off, due to an
overcharge condition or by direct command from the
microcontroller, the cells are not in an undervoltage
condition and the pack has a load, then excessive
current may flow through Q10 and diode D1. To
eliminate this effect, the gate of Q10 can be turned off by
the microcontroller through an unused X3101 cell
balance output, or directly from a microcontroller port
instead of connecting to V

RGO

FET Control

Circuitry

OVP/LMON

LMON

X3100/X3101

P+

P-

Load

VCS1

VCS2

VSS

SENSE

RGO

Q10

Symbol

Description

Delay

Over-current
detection delay

0.001

10ms (Typ)

OCR

Over-current
release time

0.001

10ms (Typ)

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Figure 8. Over-Current Protection Mode--Event Diagram

P+

VCS

UVP/OCP

OCR

Over-Current Protection Mode

Voc

Normal Operation Mode

P+ = (RLOAD+RSENSE) x ILMON

Normal Operation Mode

Event

B+

Table 24. Over-Current Protection Mode--Event Diagram Description

Event

Event Description

[0,1)

-- Discharge FET is ON (OCP=Vss). Battery cells are permitted to discharge.
-- VCS

(VCS

VCS

) is less than the over-current threshold voltage (V

-- The device is in normal operation mode (i.e. not in a protection mode).

[1]

-- Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 8.).
-- The positive battery terminal voltage (P+) falls, and VCS

exceeds V

-- The internal over-current detection delay timer begins counting down.
-- The device is still in Normal Operation Mode

(1,2)

The internal Over-current detection delay timer continues counting for T

seconds.

[2]

-- The internal over-current detection delay timer times out, AND VCS

is still above V

OC.

-- The internal over-current sense circuitry switches the discharge FET OFF (UVP/OCP=Vcc).
-- The device now begins a load monitor state by passing a small test current (I

LMON

=7.5µA) out of pin

OVP/LMON. This senses if an over-current condition (i.e. if the load resistance < 150k

) still exists

across P+/P-.

-- The device has now entered over-current protection mode.
-- It is possible to change the status of UVPC and OVPC in the control register, although the status of pins

UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection
mode.

(2,3)

-- The X3100/X3101 now continuously monitors the load resistance to detect whether or not an over-

current condition is still present across the battery terminals P+/P-.

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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MONITOR MODE

Analog Multiplexer Selection

The X3100 and X3101 can be used to externally monitor
individual battery cell voltages, and battery current.
Each quantity can be monitored at the analog output pin
(AO), and is selected using the analog select (AS0AS2)
pins (Table 25). Also, see Figure 9.

Current Monitor Function

The voltages monitored at pins

VCS

and VCS

can be

used to calculate current flowing through the battery
terminals, using an off-board microcontroller with an A/D.

Since the value of the sense resistor (R

SENSE

) is small

(typically in the order of tens of m

and since the

resolution of various A/D converters may vary, the
voltage across R

SENSE

(

VCS

and VCS

) is amplified

internally with a gain of between 10 and 160, and output
to pin AO (Figure 9).

Figure 9. X3100/X3101 Monitor Circuit

The internal gain of the X3100 or X3101 current sense
voltage amplifier can be selected by using the WCNTR

Instruction to set bits CSG1 and CSG0 in the control
register (Table 14). The CSG1 and CSG0 bits select one

[3]

-- The device detects the load resistance has risen above 250k

-- Voltages P+ and VCS

return to their normal levels.

-- The test current from pin OVP/LMON is stopped (I

LMON

=0µA)

-- The device has now returned from the load monitor state
-- The internal over-current release time timer begins counting down.
-- Device is still in over-current protection mode.

(3,4)

The internal over-current release timer continues counting for T

OCR

seconds.

[4]

-- The internal over-current release timer times out, and VCS

is still below V

OC.

-- The device returns from over-current protection mode, and is now in normal operation mode.
-- The discharge FET is automatically switched ON (UVP/OCP=Vss)--unless the status of UVPC has

been changed in the control register during the over-current protection mode.

-- The status of the charge FET remains unaffected.
-- Discharge of the battery cells is once again possible.

Table 24. Over-Current Protection Mode--Event Diagram Description (Continued)

Event

Event Description

Table 25. AO Selection Map

AS2

AS1 AS0

AO output

(1)

VCELL

(VCELL

)

VCELL

(VCELL

)

VCELL

(VCELL

)

VCELL

Vss (VCELL

)

VCS

(VCS

)

(2)

VCS2VCS

(VCS

)

(2)

Notes: (1) This is the normal state of the X3100 or X3101. While in

this state Over-charge and Over-discharge Protection
conditions are periodically monitored (See "Periodic Pro-
tection Monitoring" on page 12.)

(2) VCS

, VCS

are read at AO with respect to a DC bias

voltage of 2.5V (See section "Current Monitor Function"
on page 20).

Over-Current

Protection

VCS

CSG1 CSG0

Config

nalog

MUX

AS0

AS1
AS2

SPI

I/F

SCL

SENSE

Gain

Setting

Cross-Bar

Switch

X3100/X3101

OP1

Voltage

Level

Shifters

Cell 1 Voltage

Cell 2 Voltage
Cell 3 Voltage
Cell 4 Voltage

2.5V

P-

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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of four input resistors to Op Amp OP1. The feedback
resistors remain constant. This ratio of input to feedback
resistors determines the gain. Putting external resistors
in series with the inputs reduces the gain of the amplifier.

VCS

and VCS

are read at AO with respect to a DC

bias voltage of 2.5V. Therefore, the voltage range of
VCS

and VCS

changes depending upon the

direction of current flow (i.e. battery cells are in Charge
or Discharge--Table 21).

Table 26. AO Voltage Range for VCS

and VCS

By calculating the difference of VCS

and VCS

the

offset voltage of the internal op-amp circuitry is
cancelled. This allows for the accurate calculation of
current flow into and out of the battery cells.

Pack current is calculated using the following formula:

VOLTAGE REGULATOR

The X3100 and X3101 are able to supply peripheral
devices with a regulated 5VDC±0.5% output at pin
RGO. The voltage regulator should be configured
externally as shown in Figure 10.

The non-inverting input of OP1 is fed with a high
precision 5VDC supply. The voltage at the output of the
voltage regulator (V

RGO

) is compared to this 5V

reference via the inverting input of OP1. The output of
OP1 in turn drives the regulator pnp transistor (Q1). The
negative feedback at the regulator output maintains the
voltage at 5VDC±0.5% (including ripple) despite
changes in load, and differences in regulator transistors.

When power is applied to pin VCC of the X3100 or
X3101, V

RGO

is regulated to 5VDC±10% for a nominal

time of T

+2ms. During this time period, V

RGO

"tuned" to attain a final value of 5VDC±0.5% (Figure 2).

The maximum current that can flow from the voltage
regulator (I

LMT

) is controlled by the current limiting

resistor (R

LMT

) connected between RGP and VCC. When

the voltage across VCC and RGP reaches a nominal

2.5V (i.e. the threshold voltage for the FET), Q2 switches
ON, shorting VCC to the base of Q1. Since the base
voltage of Q1 is now higher than the emitter voltage, Q1
switches OFF, and hence the supply current goes to zero.

Typical values for R

LMT

and I

LMT

are shown in Table 27.

In order to protect the voltage regulator circuitry from
damage in case of a short-circuit, R

LMT

10 should

always be used.

Table 27. Typical Values for R

LMT

and I

LMT

When choosing the value of R

LMT

, the drive limitations

of the PNP transistor used should also be taken into
consideration. The transistor should have a gain of at
least 100 to support an output current of 250mA.

Figure 10. Voltage Regulator Operation

4KBIT EEPROM MEMORY

The X3100 and X3101 contain a CMOS 4k-bit serial
EEPROM, internally organized as 512 x 8 bits. This
memory is accessible via the SPI port, and features the
IDLock function.

The 4kbit EEPROM array can be accessed by the SPI
port at any time, even during a protection mode, except
during sleep mode. After power is applied to VCC of the
X3100 or X3101, EEREAD and EEWRITE Instructions

Cell State

AO Voltage Range

VCS

Charge

2.5V

5.0V

VCS

Discharge

2.5V

VCS

Charge

2.5V

VCS

Discharge

2.5V

5.0V

Pack Current

VCS

(

)

( ) gain setting

(

)(current sense resistor)

----------------------------------------------------------------------------------------------------------

LMT

Voltage Regulator Current Limit (I

LMT

)

250mA ± 50% (Typical)

100mA ± 50% (Typical)

50mA ± 50% (Typical)

VCC

RGC

RGP

RGO

Voltage

Reference

To Internal Voltage
Regulating Circuitry

Regulated
5VDC Output

LMT

Un-Regulated

Input

Voltage

LMT

Precision

X3100/X3101

OP1

5VDC

Tuning

RGO

0.1

µF

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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can be executed only after times t

PUR

(power up to read

time) and t

PUW

(power up to write time) respectively.

IDLock is a programmable locking mechanism which
allows the user to lock data in different portions of the
EEPROM memory space, ranging from as little as one
page to as much as 1/2 of the total array. This is useful
for storing information such as battery pack serial
number, manufacturing codes, battery cell chemistry
data, or cell characteristics.

EEPROM Write Enable Latch

The X3100 and X3101 contain an EEPROM "Write
Enable" latch. This latch must be SET before a write to
EEPROM operation is initiated. The WREN instruction
will set the latch and the WRDI instruction will reset the
latch (Figure 11). This latch is automatically reset upon a
power-up condition and after the completion of a byte or
page write cycle.

IDLock Memory

Xicor's IDLock memory provides a flexible mechanism to
store and lock battery cell/pack information. There are
seven distinct IDLock memory areas within the array
which vary in size from one page to as much as half of
the entire array.

Prior to any attempt to perform an IDLock operation, the
WREN instruction must first be issued. This instruction
sets the "Write Enable" latch and allows the part to
respond to an IDLock sequence. The EEPROM memory
may then be IDLocked by writing the

SET IDL

instruction

(Table 30 and Figure 19), followed by the IDLock
protection byte.

Table 28. IDLock Partition Byte Definition

The IDLock protection byte contains the IDLock bits
IDL2-IDL0, which defines the particular partition to be
locked (Table 28). The rest of the bits [7:3] are unused

and must be written as zeroes. Bringing CS HIGH after
the two byte IDLock instruction initiates a nonvolatile write
to the status register. Writing more than one byte to the
status register will overwrite the previously written
IDLock byte.

Once an IDLock instruction has been completed, that
IDLock setup is held in a nonvolatile IDLock Register
(Table 29) until the next IDLock instruction is issued. The
sections of the memory array that are IDLocked can be
read but not written until IDLock is removed or changed.

Table 29. IDLock Register

X3100/X3101 SPI SERIAL COMMUNICATION

The X3100 and X3101 are designed to interface directly
with the synchronous Serial Peripheral Interface (SPI) of
many popular microcontroller families. This interface
uses four signals, CS, SCK, SI and SO. The signal CS
when low, enables communications with the device. The
SI pin carries the input signal and SO provides the
output signal. SCK clocks data in or out. The X3100 and
X3101 operate in SPI mode 0 which requires SCK to be
normally low when not transferring data. It also specifies
that the rising edge of SCK clocks data into the device,
while the falling edge of SCK clocks data out.

This SPI port is used to set the various internal registers,
write to the EEPROM array, and select various device
functions.

The X3100 and X3101 contain an 8-bit instruction
register. It is accessed by clocking data into the SI input.
CS must be LOW during the entire operation. Table 30
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB
first.

Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock, and then start it again to resume
operations where left off.

IDLock Protection

Bytes

EEPROM Memory Address

IDLocked

0000 0000

None

0000 0001

000h07Fh

0000 0010

080h0FFh

0000 0011

100h17Fh

0000 0100

180h1FFh

0000 0101

000h0FFh

0000 0110

000h00Fh

0000 0111

1F0h1FFh

IDL2

IDL1

IDL0

Note:

Bits [7:3] specified to be "0's"

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Write Enable/Write Disable (WREN/WRDI)

Any write to a nonvolatile array or register, requires the
WREN command be sent prior to the write command.
This command sets an internal latch allowing the write

operation to proceed. The WRDI command resets the
internal latch if the system decides to abort a write
operation. See Figure 11.

Figure 11. EEPROM Write Enable Latch (WREN/WRDI) Operation Sequence

Table 30. X3100/X3101 Instruction Set

Instruction

Name

Instruction

Format*

Description

WREN

0000 0110

Set the write enable latch (write enable operation)--Figure 11

WRDI

0000 0100

Reset the write enable latch (write disable operation)--Figure 11

EEWRITE

0000 0010

Write command followed by address/data (4kbit EEPROM)--Figure 12, Figure 13

EEREAD STAT

0000 0101

Reads IDLock settings & status of EEPROM EEWRITE instruction--Figure 14

EEREAD

0000 0011

Read operation followed by address (for 4kbit EEPROM)--Figure 15

WCFIG

0000 1001

Write to configuration register followed by two bytes of data--Figure 4, Figure 16.
Data stored in SRAM only and will power-up to previous settings--Figure 3

WCNTR

0000 1010

Write to control register, followed by two bytes of data--Figure 17

RDSTAT

0000 1011

Read contents of status register--Figure 18

SET IDL

0000 0001

Set EEPROM ID lock partition followed by partition byte--Figure 19

*Instructions have the MSB in leftmost position and are transferred MSB first.

SCK

High Imped

ance

Instruction

(1 Byte)

WREN

WRDI

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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EEPROM Write Sequence (EEWRITE)

Prior to any attempt to write data into the EEPROM of
the X3100 or X3101, the "Write Enable" latch must first
be set by issuing the WREN instruction (See Table 30
and Figure 11). CS is first taken LOW. Then the WREN
instruction is clocked into the X3100 or X3101. After all
eight bits of the instruction are transmitted, CS must
then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.

To write data to the EEPROM memory array, the user
issues the EEWRITE instruction, followed by the 16 bit
address and the data to be written. Only the last 9 bits of
the address are used and bits [15:9] are specified to be
zeroes. This is minimally a thirty-two clock operation. CS
must go LOW and remain LOW for the duration of the
operation. The host may continue to write up to 16 bytes
of data to the X3100 or X3101. The only restriction is the
16 bytes must reside on the same page. If the address
counter reaches the end of the page and the clock
continues, the counter will "roll over" to the first address
of the page and overwrite any data that may have been
previously written.

For a byte or page write operation to be completed, CS
can only be brought HIGH after bit 0 of the last data byte

to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed.
Refer to Figure 12 and Figure 13 for detailed illustration
of the write sequences and time frames in which CS
going HIGH are valid.

EEPROM Read Status Operation (EEREAD STAT)

If there is not a nonvolatile write in progress, the
EEREAD STAT instruction returns the IDLock byte from
the IDLock register which contains the IDLock bits IDL2-
IDL0 (Table 29). The IDLock bits define the IDLock
condition (Table 28). The other bits are reserved and will
return `0' when read.

If a nonvolatile write to the EEPROM (i.e. EEWRITE
instruction) is in progress, the EEREAD STAT returns a
HIGH on SO. When the nonvolatile write cycle in the
EEPROM is completed, the status register data is read
out.

Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (See Figure 14).

Figure 12. EEPROM Byte Write (EEWRITE) Operation Sequence

SCK

High Impedance

EEWRITE Instruction

(1 Byte)

Byte Address (2 Byte)

Data Byte

15 14

20 21 22 23 24 25 26 27 28 29 30 31

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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EEPROM Read Sequence (EEREAD)

When reading from the X3100 or X3101 EEPROM
memory, CS is first pulled LOW to select the device. The 8-
bit EEREAD instruction is transmitted to the X3100 or
X3101, followed by the 16-bit address, of which the last
9 bits are used (bits [15:9] specified to be zeroes). After
the EEREAD opcode and address are sent, the data
stored in the memory at the selected address is shifted
out on the SO line. The data stored in memory at the next

address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted
out. When the highest address is reached (01FFh), the
address counter rolls over to address 0000h, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
EEPROM Read (EEREAD) operation sequence
illustrated in Figure 15.

Figure 15. EEPROM (EEREAD) Read Operation Sequence

SCK

High Impedance

EEREAD Instruction

(1 Byte)

Byte Address (2 Byte)

Data Out

15 14

20 21 22 23 24 25 26 27 28 29 30

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Write Configuration Register (WCFIG)

The Write Configuration Register (WCFIG) instruction
updates the static part of the Configuration Register.
These new values take effect immediately, for example
writing a new Over-discharge voltage limit. However, to
make these changes permanent, so they remain if the
cell voltages are removed, an EEWRITE operation to
the EEPROM array is required following the WCFIG
command. This command is shown in Figure 16.

Write Control Register (WCNTRL)

The Write Control Register (WCNTRL) instruction
updates the contents of the volatile Control Register.
This command sets the status of the FET control pins,
the cell balancing outputs, the current sense gain and
external entry to the sleep mode. Since this instruction
controls a volatile register, no other commands are
required and there is no delay time needed after the
instruction, before subsequent commands. The
operation of the WCNTRL command is shown in
Figure 17.

Figure 16. Write Configuration Register (WCFIG) Operation Sequence

Figure 17. Write Control Register (WCNTR) Operation Sequence

SCK

High Impedance

WCFIG Instruction

(1 BYTE)

Configuration

15 14

20 21 22 23

(2 BYTE)

SCK

High Impedance

WCNTR Instruction

(1 Byte)

Control

15 14

18 19 20 21

(2 Byte)

Old Control Bits

New Control Bits

Control

Bits

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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Read Status Register (RDSTAT)

The Read Status Register (RDSTAT) command returns
the status of the X3100 or X3101. The Status Register
contains three bits that indicate whether the voltage
regulator is stabilized, and if there are any protection
failure conditions. The operation of the RDSTAT
instruction is shown in Figure 18.

Set ID Lock (SET IDL)

The contents of the EEPROM memory array in the
X3100 or X3101 can be locked in one of eight
configurations using the SET ID lock command. When a
section of the EEPROM array is locked, the contents
cannot be changed, even when a valid write operation
attempts a write to that area. The SET IDL command
operation is shown in Figure 19.

Figure 18. Read Status Register (RDSTAT) Operation Sequence

Figure 19. EEPROM IDLock (SET IDL) Operation Sequence

SCK

High Impedance

Instruction

(1 Byte)

RDSTAT

Status Register Output

SCK

High Impedance

Set IDL

10 11 12 13 14 15

IDLock

Byte

Instruction

L
2

L
1

L
0

X3100/X3101 Preliminary Information

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ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in
the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)

Symbol

Parameter

Min.

Max.

Unit

Storage temperature

-55

125

°C

Operating temperature

-40

°C

DC output current

Lead temperature (soldering 10 seconds)

300

°C

VCC

Power supply voltage

-0.5

+27.0

VCELL

Cell voltage

-0.5

6.75

TERM1

Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1,
VCS2, OVT, UVT, OCT, AO)

-0.5

RGO

+ 0.5

TERM2

Terminal voltage (VCELL1)

-0.5

+ 1.0

TERM3

Terminal voltage (all other pins)

-0.5

+ 0.5

Temperature

Min.

Max.

Supply Voltage

Limits

Commercial

-20°C

+70°C

X3100/X3101

6V to 24V

Symbol

Parameter

Limits

Units

Test Conditions

Min.

Max.

Input leakage current (SCK, SI, CS,
ASO, AS1, AS2)

±10

µA

Output leakage current (SO)

±10

µA

(1)

Input LOW voltage
(SCK, SI, CS, AS0, AS1, AS2)

- 0.3

RGO

x 0.3

(1)

Input HIGH voltage
(SCK, SI, CS, AS0, AS1, AS2)

RGO

x 0.7 V

RGO

+ 0.3

VOL1

Output LOW voltage (SO)

0.4

= 1.0mA

VOH1

Output HIGH voltage (SO)

RGO

- 0.8

= -0.4mA

VOL2

Output LOW voltage
(UVP/OCP, OVP/LMON, CB1-CB4)

0.4

= 100uA

VOH2

Output HIGH voltage
(UVP/OCP, OVP/LMON, CB1-CB4)

-0.4

= -20uA

VOL3

Output LOW voltage (RGC)

0.4

= 2mA, RGP = V

RGO = 5V

VOH3

Output HIGH voltage (RGC)

-4.0

= -20µA, RGP = V

- 4V,

RGO = 5V

Note:

(1) V

min. and V

max. are for reference only and are not 100% tested.

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

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OPERATING CHARACTERISTICS X3100 (Over the recommended operating conditions unless otherwise specified)

Description

Sym

Condition

Min

Typ

(2)

Max

Unit

5V regulated voltage

RGO

On power up or at wake-up

4.5

5.5

After self-tuning
(@10mA V

RGO

current; 25

4.98

4.99

5.00

After self-tuning
(@10mA V

RGO

current; 0 - 50

(5)

4.95

5.02

After self-tuning
(@50mA V

RGO

current)

(5)

4.90

5.00

5VDC voltage regulator current
limit

LMT

(3)

LMT

=10

250

supply current (1)

Icc1

Normal operation

250

µA

supply current (2)

Icc2

during nonvolatile EEPROM write

1.3

2.5

supply current (3)

Icc3

During EEPROM read
SCK=3.3MHz

0.9

1.2

supply current (4)

Icc4

Sleep mode

µA

supply current (5)

Icc5

Monitor mode
AN2, AN1, AN0 not equal to 0.

365

600

µA

Cell over-charge protection mode
voltage threshold
(Default in Boldface)

(4)

= 4.20V (VOV1, VOV0 = 0,0)

C to 50

4.10
4.15

4.275

4.25

= 4.25V (VOV1, VOV0 = 0,1)

C to 50

4.15
4.20

4.325

4.30

= 4.30V (VOV1, VOV0 = 1,0)

C to 50

4.2

4.25

4.375

4.35

= 4.35V (VOV1, VOV0 = 1,1)

C to 50

4.25

4.425

4.30

4.40

Cell over-charge protection mode
release voltage threshold
(Default in Boldface)

OVR

0.25

0.20

0.15

Cell over-charge detection time

(5)

=0.1uF

0.5

1.5

Cell over-discharge protection
mode (SLEEP) threshold.
(Default in Boldface)

(4)

= 1.95V (VUV1, VUV0 = 0,0)

1.85

2.05

= 2.05V (VUV1, VUV0 = 0,1)

1.95

2.15

= 2.15V (VUV1, VUV0 = 1,0)

2.05

2.25

= 2.25V (VUV1, VUV0 = 1,1)

2.15

2.35

Cell over-discharge protection
mode release threshold
(Default in Boldface)

UVR

0.65

0.7

0.75

Cell over-discharge detection time

=0.1µF

(5)

=200pF

0.5

1
2

1.5

Cell over-discharge release time

UVR

=0.1µF

(5)

=200pF

3.5

100

10.5

120

µs

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

31 of 40

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Notes: (2) Typical at 25°C.

(3) See Figure 10 on page 21.
(4) The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register.
(5) For reference only, this parameter is not 100% tested.

Over-current mode detection
voltage
(Default in Boldface)

(4)

= 0.075V (VOC1, VOC0 = 0,0)

C to 50

0.050
0.060

0.100
0.090

= 0.100V (VOC1, VOC0 = 0,1)

C to 50

0.075
0.085

0.125
0.115

= 0.125V (VOC1, VOC0 = 1,0)

C to 50

0.100
0.110

0.150
0.140

= 0.150V (VOC1, VOC0 = 1,1)

C to 50

0.125
0.135

0.175
0.165

Over-current mode detection time

=0.001

(5)

=200pF

5
1

Over-current mode release time

OCR

=0.001

(5)

=200pF

5
1

Load resistance over-current mode
release condition

Releases when OVP/LMON pin >
2.5V

200

250

Cell charge threshold voltage

=1.4V (Default)

(5)

1.30

1.40

1.50

X3100 wake-up voltage

(For Vcc above this voltage, the device
wakes up)

SLR

See Wake-up test circuit

12.5

15.5

X3100 sleep voltage

(For Vcc above this voltage, the device
cannot go to sleep)

SLP

See Sleep test circuit

11.5

14.5

Description

Sym

Condition

Min

Typ

(2)

Max

Unit

Wake-up test circuit (X3100)

Sleep test circuit (X3100)

Vcc

VCELL1

VCELL2

VCELL3

VCELL4

Vss

RGP

RGC

RGO

Increase Vcc until V

RGO

turns on

RGO

Vcc

VCELL1

VCELL2

VCELL3

VCELL4

Vss

RGP

RGC

RGO

Decrease Vcc until V

RGO

turns off

RGO

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

32 of 40

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OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified)

Description

Sym

Condition

Min

Typ

(2)

Max

Unit

5V regulated voltage

RGO

On power up or at wake-up

4.5

5.5

After self-tuning
(@10mA V

RGO

current; 25

4.98

4.99

5.00

After self-tuning
(@10mA V

RGO

current; 0 - 50

(5)

4.95

5.02

After self-tuning
(@50mA V

RGO

current)

(5)

4.90

5.00

5VDC voltage regulator current limit I

LMT

(3)

LMT

=10

250

supply current (1)

Icc1

Normal operation

250

µA

supply current (2)

Icc2

during nonvolatile EEPROM write

1.3

2.5

supply current (3)

Icc3

During EEPROM read
SCK=3.3MHz

0.9

1.2

supply current (4)

Icc4

Sleep mode

µA

supply current (5)

Icc5

Monitor mode
AN2, AN1, AN0 not equal to 0.

365

600

µA

Cell over-charge protection mode
voltage threshold
(Default in Boldface)

(4)

= 4.20V (VOV1, VOV0 = 0,0)

C to 50

4.10
4.15

4.275

4.25

= 4.25V (VOV1, VOV0 = 0,1)

C to 50

4.15
4.20

4.325

4.30

= 4.30V (VOV1, VOV0 = 1,0)

C to 50

4.2

4.25

4.375

4.35

= 4.35V (VOV1, VOV0 = 1,1)

C to 50

4.25

4.425

4.30

4.40

Cell over-charge protection mode
release voltage threshold
(Default in Boldface)

OVR

0.25

0.20

0.15

Cell over-charge detection time

(5)

=0.1uF

0.5

1.5

Cell over-discharge protection
mode (SLEEP) threshold.
(Default in Boldface)

(4)

= 2.25V (VUV1, VUV0 = 0,0)

2.15

2.35

= 2.35V (VUV1, VUV0 = 0,1)

2.25

2.45

= 2.45V (VUV1, VUV0 = 1,0)

2.35

2.55

= 2.55V (VUV1, VUV0 = 1,1)

2.45

2.65

Cell over-discharge protection
mode release threshold
(Default in Boldface)

UVR

0.65

0.7

0.75

Cell over-discharge detection time

=0.1µF

(5)

=200pF

0.5

1
2

1.5

Cell over-discharge release time

UVR

=0.1µF

(5)

=200pF

3.5

100

10.5

120

µs

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

33 of 40

REV 1.1.8 12/10/02

www.xicor.com

Notes: (2) Typical at 25°C.

Over-current mode detection
voltage
(Default in Boldface)

(4)

= 0.075V (VOC1, VOC0 = 0,0)

C to 50

0.050
0.060

0.100
0.090

= 0.100V (VOC1, VOC0 = 0,1)

C to 50

0.075
0.085

0.125
0.115

= 0.125V (VOC1, VOC0 = 1,0)

C to 50

0.100
0.110

0.150
0.140

= 0.150V (VOC1, VOC0 = 1,1)

C to 50

0.125
0.135

0.175
0.165

Over-current mode detection time

=0.001

(5)

=200pF

5
1

Over-current mode release time

OCR

=0.001

(5)

=200pF

5
1

Load resistance over-current mode
release condition

Releases when OVP/LMON pin >
2.5V

200

250

Cell charge threshold voltage

=1.4V (Default)

(5)

1.30

1.50

X3100 wake-up voltage

(For Vcc above this voltage, the device
wakes up)

SLR

See Wake-up test circuit

10.5

12.5

X3100 sleep voltage

(For Vcc above this voltage, the device
cannot go to sleep)

SLP

See Sleep test circuit

9.5

11.5

Description

Sym

Condition

Min

Typ

(2)

Max

Unit

Wake-up test circuit (X3101)

Sleep test circuit (X3101)

Increase Vcc until V

RGO

turns on

Vcc

RGO

Vcc

VCELL1

VCELL2

VCELL3

VCELL4

Vss

RGP

RGC

RGO

Vcc

VCELL1

VCELL2

VCELL3

VCELL4

Vss

RGP

RGC

RGO

Decrease Vcc until V

RGO

turns off

RGO

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

34 of 40

REV 1.1.8 12/10/02

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POWER-UP TIMING

Notes: (6) t

PUR

, t

PUW1

and t

PUW2

are the delays required from the time V

is stable until a read or write can be initiated. These parameters

are not 100% tested.

(7) Whichever is longer.

CAPACITANCE T

=+25°C, f= 1 MHz, V

RGO

=5V

Equivalent A.C. Load Circuit

A.C. TEST CONDITIONS

Symbol

Parameter

Min.

Max.

PUR

(6)

Power-up to SPI read operation (RDSTAT, EEREAD STAT)

+2ms

PUW1

(6)

Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR)

+2ms

PUW2

(6)

Power-up to SPI write operation (WCNTR - bits 10 and 11)

+200ms

(7)

Symbol

Parameter

Max.

Units

Conditions

OUT

(8)

Output capacitance (SO)

OUT

=0V

(8)

Input capacitance (SCK, SI, CS)

=0V

Notes: (8) This parameter is not 100% tested.

2061

3025

30pF

Input pulse levels

0.5 4.5V

Input rise and fall times

10ns

Input and output timing level

2.5V

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

35 of 40

REV 1.1.8 12/10/02

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A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

SERIAL INPUT TIMING

Notes: (9) This parameter is not 100% tested

(10)t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Input Timing

Symbol

Parameter

Voltage

Min.

Max.

Units

SCK

Clock frequency

3.3

MHz

CYC

Cycle time

300

LEAD

CS lead time

150

LAG

CS lag time

150

Clock HIGH time

130

Clock LOW time

130

Data setup time

Data hold time

(9)

Data in rise time

µs

(9)

Data in fall time

µs

CS deselect time

100

(10)

Write cycle time

SCK

MSB IN

LAG

LEAD

LSB IN

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

38 of 40

REV 1.1.8 12/10/02

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TYPICAL OPERATING CHARACTERISTICS

X3100/X3101 Over Charge Trip Voltage (Typical)

4.15

4.20

4.25

4.30

4.35

4.40

-25

Temperature (Deg C)

Voltage (V)

4.2V Setting

4.25V Setting

4.3V Setting

4.35V Setting

X3100 Over Discharge Trip Voltage (Typical)

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

-25

Temperature (Deg C)

Voltage (V)

1.95V Setting

2.05V Setting

2.15V Setting

2.25V Setting

Voltage Regulator Output (Typical)

Vcc = 10.8V to 16V R

lim

= 15 Ohm (I

lim

= 200mA)

4.880

4.900

4.920

4.940

4.960

4.980

5.000

5.020

100

Load (mA)

Regulator Voltage (V)

-25 degC

25 degC

75 degC

Voltage Regulator Output (Typical)

Vcc = 10.8V to 16V R

lim

= 15 Ohm (I

lim

= 200mA)

4.880

4.900

4.920

4.940

4.960

4.980

5.000

5.020

-25

Temperature

Regulated Voltage

1mA Load

10mA Load

50mA Load

100 mA Load

X3101 Over Discharge Trip Voltage (Typical)

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

-25

Temperature (Deg C)

Voltage (V)

2.25V Setting

2.35V Setting

2.45V Setting

2.55V Setting

Norm al Operating Current

100

125

150

-20

Tem perature

Current (uA)

Monitor Mode Current

300

350

400

450

-20

Tem perature

Current (uA)

For typical performance of current and voltage monitoring circuits, please refer to Application Note AN142 and AN143

X3100/X3101 Preliminary Information

Characteristics subject to change without notice.

40 of 40

REV 1.1.8 12/10/02

www.xicor.com

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

ORDERING INFORMATION

Device

X3100

Temperature Range
Blank=Commercial= -20°C to +70°C

Package

VCC Limits
Blank=6V to 24V

V28 = 28-Lead TSSOP

X3101

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X3100

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X3100