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X40010/X40011/X40014/X40015

Dual Voltage Monitor with Integrated CPU Supervisor

FEATURES

· Dual voltage detection and reset assertion

--Standard reset threshold settings

See Selection table on page 2.

--Adjust low voltage reset threshold voltages

using special programming sequence

--Reset signal valid to V

= 1V

--Monitor three voltages or detect power fail

· Independent Core Voltage Monitor (V2MON)
· Fault detection register
· Selectable power on reset timeout (0.05s,

0.2s, 0.4s, 0.8s)

· Selectable watchdog timer interval (25ms, 200ms,

1.4s, off)

· Low power CMOS

--25µA typical standby current, watchdog on
--6µA typical standby current, watchdog off

· 400kHz 2-wire interface
· 2.7V to 5.5V power supply operation
· Available packages

--8-lead SOIC, TSSOP

APPLICATIONS

· Communication Equipment

--Routers, Hubs, Switches
--Disk Arrays, Network Storage

· Industrial Systems

--Process Control
--Intelligent Instrumentation

· Computer Systems

--Computers
--Network Servers

DESCRIPTION

The X40010/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.

Applying voltage to V

activates the power on reset

circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.

Low V

detection circuitry protects the user's system

from low voltage conditions, resetting the system when
V

falls below the minimum V

TRIP1

point. RESET/

RESET is active until V

returns to proper operating

level and stabilizes. A second voltage monitor circuit
tracks the unregulated supply to provide a power fail
warning or monitors different power supply voltage.
Three common low voltage combinations are avail-
able, however, Xicor's unique circuits allows the

BLOCK DIAGRAM

V2FAIL

WDO

RESET

X40010/14

X40011/15

Fault Detection

Status

Data

Command

Decode Test

& Control

Logic

Power on,

Low Voltage

Reset

Generation

V2MON

SDA

SCL

(V1MON)

User Programmable

Threshold

Reset Logic

TRIP1

User Programmable

TRIP2

Watchdog Timer

and

Reset Logic

V2MON

*X40010/11 = V2MON*

X40014/15 = V

· Monitor Voltages: 5V to 0.9V
· Independent Core Voltage Monitor

New Features

Preliminary Datasheet

X40010/X40011/X40014/X40015 Preliminary

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threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.

The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.

The device features a 2-wire interface and software
protocol allowing operation on an I

bus.

Dual Voltage Monitors

*Voltage monitor requires V

to operation. Others are independent of V

PIN CONFIGURATION

Device

Expected System Voltages

Vtrip1(V)

Vtrip2(V)

POR (system)

X40010/11

-A
-B
-C

5V; 3V or 3.3V

5V; 3V

3V; 3.3V; 1.8V

2.04.75*

4.554.65*
4.354.45*
2.852.95*

1.704.75
2.852.95
2.552.65
1.651.75

RESET = X40010
RESET = X40011

X40014/15

-A
-B
-C

3V; 3.3V; 1.5V

3V; 1.5V

3V or 3.3V; 1.1 or 1.2V

2.04.75*

2.852.95*
2.552.65*
2.852.95*

0.903.50*
1.251.35*
1.251.35*
0.951.05*

RESET = X40014
RESET = X40015

PIN DESCRIPTION

Pin

Name

Function

SOIC TSSOP

V2FAIL

V2 Voltage Fail Output.

This open drain output goes LOW when V2MON is less than V

TRIP2

and

goes HIGH when V2MON exceeds V

TRIP2

. There is no power up reset delay circuitry on this pin.

V2MON

V2 Voltage Monitor Input.

When the V2MON input is less than the V

TRIP2

voltage, V2FAIL goes

LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V

when not used.The V2MON comparator is supplied by V2MON (X40010/11) or by V

Input

(X40014/15).

RESET/

RESET

RESET Output.

(X40011/15) This is an active LOW, open drain output which goes active when-

ever V

falls below V

TRIP1

. It will remain active until V

rises above V

TRIP1

and for the t

PURST

thereafter.

RESET Output.

(X40010/14) This is an active HIGH CMOS output which goes active whenever

falls below V

TRIP1

. It will remain active until

rises above V

TRIP1

and for the t

PURST

there-

after.

Ground

SDA

RESET/RESET

V2MON

SCL

WDO

V2FAIL

RESET/RESET

SCL

SDA

V2FAIL

V2MON

WDO

X40010/14, X40011/15

8-Pin SOIC

8-Pin TSSOP

X40010/X40011/X40014/X40015 Preliminary

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PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X40010/11/14/15 activates a
Power On Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.

It prevents the system microprocessor from starting to

operate with insufficient voltage.

It prevents the processor from operating prior to stabili-

zation of the oscillator.

It allows time for an FPGA to download its configuration

prior to initialization of the circuit.

It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power up.

When V

exceeds the device V

TRIP1

threshold value for

PURST

(selectable) the circuit releases the RESET

(X40011) and RESET (X40010) pin allowing the system
to begin operation.

Low Voltage V

(V1 Monitoring)

During operation, the X40010/11/14/15 monitors the V

level and asserts RESET/RESET if supply voltage falls
below a preset minimum V

TRIP1

. The RESET/RESET

signal prevents the microprocessor from operating in a
power fail or brownout condition. The V1FAIL signal
remains active until the voltage drops below 1V. It also
remains active until V

returns and exceeds V

TRIP1

for

PURST

Low Voltage V2 Monitoring

The X40010/11/14/15 also monitors a second voltage
level and asserts V2FAIL if the voltage falls below a
preset minimum V

TRIP2

. The V2FAIL signal is either

ORed with RESET to prevent the microprocessor from
operating in a power fail or brownout condition or used to
interrupt the microprocessor with notification of an

impending power failure. For the X40010/11 the V2FAIL
signal remains active until the V

drops below 1V (V

falling). It also remains active until V2MON returns and
exceeds V

TRIP2

by 0.2V. This voltage sense circuitry

monitors the power supply connected to the V2MON pin.
If V

= 0, V2MON can still be monitored.

For the X40014/15 devices, the V2FAIL signal remains
actice until V

drops below 1Vx and remains active until

V2MON returns and exceeds V

TRIP2

. This sense circuitry

is powered by V

. If V

= 0, V2MON cannot be moni-

tored.

Figure 1. Two Uses of Multiple Voltage Monitoring

610V

Reg

V2MON

X40011-A

Resistors selected so 3V appears on V2MON when unregulated

supply reaches 6V.

Unreg.
Supply

X40014-C

RESET

V2FAIL

System

Reset

RESET

V2FAIL

System
Reset

Notice: No external components required to monitor two voltages.

V2MON

3.3V

Reg

1.2V

Reg

V2MON

(2.9V)

SDA

Serial Data.

SDA is a bidirectional pin used to transfer data into and out of the device. It has an

open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).

Watchdog Input.

A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to

LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this tran-
sition within the watchdog time out period results in WDO going active.

SCL

Serial Clock.

The Serial Clock controls the serial bus timing for data input and output.

WDO

WDO Output.

WDO is an active LOW, open drain output which goes active whenever the

watchdog timer goes active.

Supply Voltage

PIN DESCRIPTION

(Continued)

Pin

Name

Function

SOIC TSSOP

X40010/X40011/X40014/X40015 Preliminary

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Figure 2. V

TRIPX

Set/Reset Conditions

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determines
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40010/
11/14/15 control register (also refer to page 19).

Figure 3. Watchdog Restart

V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)

The X40010/11/14/15is shipped with standard V1 and
V2 threshold (V

TRIP1,

TRIP2

) voltages. These values

will not change over normal operating and storage con-
ditions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X40010/11/14/15trip

points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.

Setting a V

TRIPx

Voltage (x=1, 2)

There are two procedures used to set the threshold
voltages (V

TRIPx

), depending if the threshold voltage to

be stored is higher or lower than the present value. For
example, if the present V

TRIPx

is 2.9 V and the new

TRIPx

is 3.2 V, the new voltage can be stored directly

into the V

TRIPx

cell. If however, the new setting is to be

lower than the present setting, then it is necessary to
"reset" the V

TRIPx

voltage before setting the new value.

Setting a Higher V

TRIPx

Voltage (x=1, 2)

To set a V

TRIPx

threshold to a new voltage which is

higher than the present threshold, the user must apply
the desired V

TRIPx

threshold voltage to the corre-

sponding input pin Vcc(V1MON), or V2MON. The
Vcc(V1MON) and V2MON must be tied together during
this sequence. Then, a programming voltage (Vp) must
be applied to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h, followed by the Byte Address 01h for
V

TRIP1

and 09h for V

TRIP2

, and a 00h Data Byte in

order to program V

TRIPx

. The STOP bit following a

valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.

Note: This operation does not corrupt the memory
array.

/V2MON

TRIPX

A0h

SCL

WDO

SDA

(X = 1, 2)

00h

SCL

SDA

.6µs

1.3µs

Timer Start

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Setting a Lower V

TRIPx

Voltage (x=1, 2)

In order to set V

TRIPx

to a lower voltage than the

present value, then V

TRIPx

must first be "reset" accord-

ing to the procedure described below. Once V

TRIPx

has been "reset", then V

TRIPx

can be set to the desired

voltage using the procedure described in "Setting a
Higher V

TRIPx

Voltage".

Resetting the V

TRIPx

Voltage

To reset a V

TRIPx

voltage, apply the programming volt-

age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V

TRIP1

and 0Bh for V

TRIP2

, followed by 00h for the

Data Byte in order to reset V

TRIPx

. The STOP bit fol-

lowing a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.

After being reset, the value of V

TRIPx

becomes a nomi-

nal value of 1.7V or lesser.

Note: This operation does not corrupt the memory
array.

CONTROL REGISTER

The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.

The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.

The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/
11/14/15 will not acknowledge any data bytes written
after the first byte is entered.

The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should sup-
ply a stop condition to be consistent with the bus proto-
col, but a stop is not required to end this operation.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to "1" prior to a write to the
Control Register.

PUP1 WD1

WD0

RWEL WEL PUP0

Figure 4. Sample V

TRIP

Reset Circuit

SOIC

TRIP1

Adj.

RESET

4.7K

SDA

SCL

µC

Adjust

Run

V2FAIL

TRIP2

Adj.

X4001x

X40010/X40011/X40014/X40015 Preliminary

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Figure 5. V

TRIPX

Set/Reset Sequence (X = 1, 2)

TRIPX

Programming

Apply V

and Voltage

Decrease V

Actual V

TRIPX -

Desired V

TRIPX

DONE

Set Higher V

Sequence

Error < MDE

| Error | < | MDE |

YES

Error > MDE

> Desired V

TRIPX

to V

Desired

Present Value

TRIPX

Execute

YES

Execute

TRIPX

Reset Sequence

Execute

Set Higher V

TRIPX

Sequence

New V

applied =

Old V

applied + | Error |

New V

applied =

Old V

applied - | Error |

Execute Reset V

TRIPX

Sequence

Output Switches?

Note: X = 1, 2

Let: MDE = Maximum Desired Error

Vx = V

, VxMON

MDE

Desired Value

MDE

Acceptable

Error Range

Error = Actual - Desired

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a "1" to the WEL bit and zeros
to the other bits of the control register.

Once set, WEL remains set until either it is reset to 0
(by writing a "0" to the WEL bit and zeros to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.

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PUP1, PUP0: Power Up Bits (Nonvolatile)

The Power Up bits, PUP1 and PUP0, determine the

PURST

time delay. The nominal power up times are

shown in the following table.

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:

Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).

Write a 06H to the Control Register to set the

Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).

Write a one byte value to the Control Register that

has all the control bits set to the desired state. The
Control register can be represented as qxys 001r in
binary, where xy are the WD bits, s isthe BP bit and
qr are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a

nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvola-
tile bits again. If bit 2 is set to `1' in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.

A read operation occurring between any of the

previous operations will not interrupt the register
write operation.

The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.

To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and three Low
Voltage Fail bits are volatile.

The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write
operation directly to the address of the register and
only one data byte is allowed for each register write
operation.

There is no need to set the WEL or RWEL in the
control register to access this fault detection register.

PUP1

PUP0

Power on Reset Delay (

PURST

)

50ms

200ms (factory setting)

400ms

800ms

WD1

WD0

Watchdog Time Out Period

1.4 seconds

200 milliseconds

25 milliseconds

disabled (factory setting)

LV1F

LV2F

WDF

X40010/X40011/X40014/X40015 Preliminary

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Figure 6. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable

Data Change

Data Stable

At power-up, the Fault Detection Register is defaulted
to all "0". The system needs to initialize this register to
all "1" before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a "1"
to a "0" to indicate the failure. At this moment, the sys-
tem should perform a read to the register and noted
the cause of the reset. After reading the register the
system should reset the register back to all "1" again.
The state of the Fault Detection Register can be read
at any time by performing a random read at address
0FFh, using the special preamble.

The FDR can be read by performing a random read at
OFFh address of the register at any time. Only one
byte of data is read by the register read operation.

WDF, Watchdog Timer Fail Bit (Volatile)

The WDF bit will set to "0" when the WDO goes active.

LV1F, Low V

Reset Fail Bit (Volatile)

The LV1F bit will be set to "0" when V

(V1MON) falls

below V

TRIP1

LV2F, Low V2MON Reset Fail Bit (Volatile)

The LV2F bit will be set to "0" when V2MON falls below
V

TRIP2

SERIAL INTERFACE

Interface Conventions

The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.

Serial Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 6.

Serial Stop Condition

All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.

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Figure 7. Valid Start and Stop Conditions

SCL

SDA

Start

Stop

Serial Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 8.

The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled, so
the device will not respond to any requests from the mas-
ter. The SDA output is at high impedance. See Figure 9.

A write to a protected block of memory will suppress
the acknowledge bit.

Figure 8. Acknowledge Response From Receiver

Data Output

from Transmitter

Data Output

from Receiver

Start

Acknowledge

SCL from

Master

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Read Operation

Prior to issuing the Slave Address Byte with the R/W bit
set to one, the master must first perform a "dummy" write
operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then
issues the Word Address Bytes. After acknowledging
receipts of the Word Address Bytes, the master immedi-

ately issues another start condition and the Slave
Address Byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the eight
bit word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. See Figure 12 for the address, acknowledge,
and data transfer sequence.

Figure 9. Read Sequence

Stops and Write Modes

Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte plus
its associated ACK is sent, then the device will reset
itself without performing the write. The contents of the
array will not be effected.

Acknowledge Polling

The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate
the end of the master's byte load operation, the device
initiates the internal high voltage cycle. Acknowledge
polling can be initiated immediately. To do this, the
master issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device
is still busy with the high voltage cycle then no ACK will
be returned. If the device has completed the write oper-
ation, an ACK will be returned and the host can then
proceed with the read or write operation. See Figure
12.

Serial Read Operations

Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.

Current Address Read

Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.

Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See Figure 13 for the
address, acknowledge, and data transfer sequence.

Slave

Address

Byte

Address

A
C
K

r
t

o
p

Slave

Address

Data

A
C
K

r
t

SDA Bus

Signals from

the Slave

Signals from

the Master

1 0 1

0 0

1 1 1 1 1 1 1 1

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

11 of 25

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Figure 10. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.

Random Read

Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a "dummy" write operation. The master

issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condi-
tion and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.

A similar operation called "Set Current Address" where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 13. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.

The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter "rolls
over" to address 0000

and the device continues to out-

put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.

ACK

Returned?

Issue Slave Address
Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

Issue STOP

Continue Normal

Read or Write

Command Sequence

PROCEED

YES

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

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SERIAL DEVICE ADDRESSING

Memory Address Map

CR, Control Register, CR7: CR0
Address: 1FF

hex

FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF

hex

Slave Address Byte

Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:

a device type identifier that is always `101x'. Where

x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.

next two bits are `0'.

next bit that becomes the MSB of the address.

Figure 11. X40010/11/14/15 Addressing

Control Register

Fault Detection Register

Word Address

Slave Byte

R/W

Control Register

Fault Detection Register

Figure 12. Current Address Read Sequence

Figure 13. Random Address Read Sequence

r
t

o
p

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

1 0 1 0

Slave

Address

Byte

Address

A
C
K

r
t

o
p

Slave

Address

Data

A
C
K

r
t

SDA Bus

Signals from

the Slave

Signals from

the Master

1 0 1

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

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One bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.

Word Address

The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.

Operational Notes

The device powers-up in the following state:

The device is in the low power standby state.

The WEL bit is set to `0'. In this state it is not possible

to write to the device.

SDA pin is the input mode.

RESET/RESET Signal is active for

PURST

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

The WEL bit must be set to allow write operations.

The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile write
cycle.

A three step sequence is required before writing into

the Control Register to change Watchdog Timer or
Block Lock settings.

Figure 14. Sequential Read Sequence

Data

(2)

o
p

Slave

Address

Data

(n)

A
C
K

SDA Bus

Signals from

the Slave

Signals from

the Master

Data
(n-1)

A
C
K

(n is any integer greater than 1)

Data

(1)

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias ................... 65°C to +135°C
Storage temperature ........................ 65°C to +150°C
Voltage on any pin with

respect to V

......................................1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

*See Ordering Info

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

40°C

+85°C

Version

Chip Supply

Voltage

Monitored*

Voltages

X40010/11

-A or -B

2.7V to 5.5V

2.6V to 5V

X40010/11-

C, X40014/15

2.7V to 5.5V

1V to 3.6V

D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)

Symbol

Parameter

Min.

Typ.

(4)

Max.

Unit

Test Conditions

CC1

(1)

Active Supply Current (

) Read

1.5

x 0.1

x 0.9,

SCL

= 400kHz

CC2

(1)

Active Supply Current (

) Read

3.0

SB1

(1)(6)

Standby Current (

) AC (WDT off)

µA

x 0.1

VIH =

x 0.9

SCL

, f

SDA

= 400kHz

SB2

(2)(6)

Standby Current (

) DC (WDT on)

µA

SDA

= V

SCL

= V

Others = GND or V

Input Leakage Current (SCL)

µA

= GND to

Output Leakage Current (SDA,
V2FAIL, WDO, RESET)

µA

SDA

= GND to

Device is in Standby

(2)

(3)

Input LOW Voltage (SDA, SCL)

-0.5

x 0.3

(3)

Input HIGH Voltage (SDA, SCL)

x 0.7

+ 0.5

HYS

(6)

Schmitt Trigger Input Hysteresis
· Fixed input level
·

related level

0.2

.05 x

V
V

Output LOW Voltage (SDA, RESET/
RESET, V2FAIL, WDO)

0.4

= 3.0mA (2.75.5V)

= 1.8mA (2.73.6V)

Output (RESET) HIGH Voltage

0.8

0.4

= -1.0mA (2.75.5V)

= -0.4mA (2.73.6V)

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

15 of 25

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Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t

after a stop that ini-

tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.

(3) V

Min. and V

Max. are for reference only and are not tested.

(4) At 25°C, V

= 5V.

(5) See Ordering Information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.

EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)

CAPACITANCE

Note:

(1) This parameter is not 100% tested.

Supply

TRIP1

(5)

Trip Point Voltage Range

2.0

4.75

4.55

4.6

4.65

X40010/11-A

4.35

4.4

4.45

X40010/11-B

2.85

2.9

2.95

X40010/11-C,
X40014/15-A&C

2.55

2.6

2.65

X40014/15-B

RPD2

(6)

TRIP2

to V2FAIL

µS

Second Supply Monitor

V2MON Current

µA

TRIP2

(5)

V2MON Trip Point Voltage Range

1.7
0.9

4.75

3.5

V
V

X40010/11
X40014/15

2.85

2.9

2.95

X40010/11-A

2.55

2.6

2.65

X40010/11-B

1.65

1.7

1.75

X40010/11-C

1.25

1.3

1.35

X40014/15-A&B

0.95

1.0

1.05

X40014/15-C

Symbol

Parameter

Max.

Unit

Test Conditions

OUT

(1)

Output Capacitance (SDA, RESET, RESET, V2FAIL,
WDO)

OUT

= 0V

(1)

Input Capacitance (SCL)

= 0V

D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)

Symbol

Parameter

Min.

Typ.

(4)

Max.

Unit

Test Conditions

REF

RPDX

= 5µs worst case

Output Pin

VxMON

V = 100mV

ref

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

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EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V

= 5V

A.C. TEST CONDITIONS

SYMBOL TABLE

Input pulse levels

x 0.1 to

x 0.9

Input rise and fall times

10ns

Input and output timing levels

x 0.5

Output load

Standard output load

SDA

30pF

V2MON

4.6K

RESET

30pF

2.06K

V2FAIL

OUT

4.6K

30pF

WDO

Must be
steady

Will be
steady

May change
from LOW

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

WAVEFORM

INPUTS

OUTPUTS

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

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A.C. CHARACTERISTICS

Note:

(1) Cb = total capacitance of one bus line in pF.

TIMING DIAGRAMS

Bus Timing

Symbol

Parameter

400kHz

Unit

Min.

Max.

SCL

SCL Clock Frequency

400

kHz

Pulse width Suppression Time at inputs

SCL LOW to SDA Data Out Valid

0.1

0.9

µs

BUF

Time the bus free before start of new transmission

1.3

µs

LOW

Clock LOW Time

1.3

µs

HIGH

Clock HIGH Time

0.6

µs

SU:STA

Start Condition Setup Time

0.6

µs

HD:STA

Start Condition Hold Time

0.6

µs

SU:DAT

Data In Setup Time

100

HD:DAT

Data In Hold Time

µs

SU:STO

Stop Condition Setup Time

0.6

µs

Data Output Hold Time

SDA and SCL Rise Time

20 +.1Cb

(1)

300

SDA and SCL Fall Time

20 +.1Cb

(1)

300

Capacitive load for each bus line

400

SU:STO

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

SCL

SDA IN

SDA OUT

LOW

BUF

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

18 of 25

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Write Cycle Timing

Nonvolatile Write Cycle Timing

Note:

(1) t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Power Fail Timings

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

(1)

Write Cycle Time

SCL

SDA

Bit of Last Byte

ACK

Stop

Condition

Start

Condition

V2MON

V2FAIL or

RPDX

RVALID

V3FAIL

LOWLINE or

TRIPX

RPDX

RPDL

X = 2, 3

[

]

[

]

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

19 of 25

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RESET/RESET Timings

LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS

Notes: (1) V

= 5V at 25°C.

(2) Values based on characterization data only.

Symbol

Parameters

Min.

Typ.

(1)

Max.

Unit

RPD1

(2)

TRIP1

to RESET/RESET (Power down only)

µs

RPDX

(2)

TRIP2

to V2FAIL

µs

PURST

Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
PUP1=1, PUP0=1

200

(2)

400

(2)

800

(2)

ms
ms
ms
ms

CC,

V2MON

Fall Time

µs

CC,

V2MON

Rise Time

µs

RVALID

Reset Valid V

WDO

Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1=1, WD0=1 (factory setting)

1.4

(2)

200

(2)

OFF

ms
ms

RST1

Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1

100

200

300

RST2

Watchdog Reset Time Out Delay WD1=1, WD0=0

12.5

37.5

RSP

Watchdog timer restart pulse width

µs

TRIP1

RESET

PURST

RPD1

RVALID

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

21 of 25

REV 1.3.4 7/12/02

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TRIP1

, V

TRIP2

, Programming Specifications: V

= 2.05.5V; Temperature = 25°C

Parameter

Description

Min.

Max.

Unit

VPS

WDO Program Voltage Setup time

µs

VPH

WDO Program Voltage Hold time

µs

TSU

TRIPX

Level Setup time

µs

THD

TRIPX

Level Hold (stable) time

µs

TRIPX

Program Cycle

VPO

Program Voltage Off time before next cycle

Programming Voltage

TRAN1

TRIP1

Set Voltage Range

2.0

4.75

TRAN2

TRIP2

Set Voltage Range X40010/11

1.7

4.75

TRAN2A

TRIP2

Set to Voltage Range X40014/15

0.9

3.5

TRIPX

Set Voltage variation after programming (-40 to +85°C).

-25

+25

VPS

WDO Program Voltage Setup time

µs

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

24 of 25

REV 1.3.4 7/12/02

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ORDERING INFORMATION

PART MARK INFORMATION

Range

TRIP1

Range

TRIP2

Range

Package

Operating

Temperature

Range

Part Number

with RESET

Part Number

with RESET

2.9-5.5

4.6V±50mV

2.9V±50mV

8L SOIC

C - 70

X40010S8-A

X40011S8-A

-40

C - 85

X40010S8I-A

X40011S8I-A

8L TSSOP

C - 70

X40010V8-A

X40011V8-A

-40

C - 85

X40010V8I-A

X40011V8I-A

2.6-5.5

4.4V±50mV

2.6V±50mV

8L SOIC

C - 70

X40010S8-B

X40011S8-B

-40

C - 85

X40010S8I-B

X40011S8I-B

8L TSSOP

C - 70

X40010V8-B

X40011V8-B

-40

C - 85

X40010V8I-B

X40011V8I-B

1.7-3.6

2.9V±50mV

1.7V±50mV

8L SOIC

C - 70

X40010S8-C

X40011S8-C

-40

C - 85

X40010S8I-C

X40011S8I-C

8L TSSOP

C - 70

X40010V8-C

X40011V8-C

-40

C - 85

X40010V8I-C

X40011V8I-C

1.3-3.6

2.9V±50mV

1.3V±50mV

8L SOIC

C - 70

X40014S8-A

X40015S8-A

-40

C - 85

X40014S8I-A

X40015S8I-A

8L TSSOP

C - 70

X40014V8-A

X40015V8-A

-40

C - 85

X40014V8I-A

X40015V8I-A

1.3-3.6

2.6V±50mV

1.3V±50mV

8L SOIC

C - 70

X40014S8-B

X40015S8-B

-40

C - 85

X40014S8I-B

X40015S8I-B

8L TSSOP

C - 70

X40014V8-B

X40015V8-B

-40

C - 85

X40014V8I-B

X40015V8I-B

1.0-3.6

2.9V±50mV

1.0V±50mV

8L SOIC

C - 70

X40014S8-C

X40015S8-C

-40

C - 85

X40014S8I-C

X40015S8I-C

8L TSSOP

C - 70

X40014V8-C

X40015V8-C

-40

C - 85

X40014V8I-C

X40015V8I-C

8-Lead Package

X4001XX

YYWWXX

I Industrial

0/1/4/5

Package - S/V

Blank Commercial

WW Workweek

YY Year

A, B, or C

X40010/X40011/X40014/X40015 Preliminary

Characteristics subject to change without notice.

25 of 25

REV 1.3.4 7/12/02

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LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS AND TRADEMARKS

Xicor, Inc., the Xicor logo, E

POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X40014S8I-C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X40014S8I-C