ChipFind - документация

Электронный компонент: X40434

Скачать:  PDF   ZIP
REV 1.3.16 7/13/02
Characteristics subject to change without notice.
1 of 26
www.xicor.com
Monitor Voltages: 5V to 0.9V
Memory Security
Independent Core Voltage Monitor
New Features
4Kbit EEPROM
X40430/X40431/X40434/X40435
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
Triple voltage detection and reset assertion
--Standard reset threshold settings. See selec-
tion table on page 2.
--Adjust low voltage reset threshold voltages
using special programming sequence
--Reset signal valid to V
CC
= 1V
--Monitor three separate voltages
Fault detection register
Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
Debounced manual reset input
Low power CMOS
--25A typical standby current, watchdog on
--6A typical standby current, watchdog off
4Kbits of EEPROM
--16 byte page write mode
--5ms write cycle time (typical)
Built-in inadvertent write protection
--Power-up/power-down protection circuitry
--Block lock protect 0, or 1/2, of EEPROM
400kHz 2-wire interface
2.7V to 5.5V power supply operation
Available packages
--14-lead SOIC, TSSOP
APPLICATIONS
Communication Equipment
--Routers, Hubs, Switches
--Disk Arrays, Network Storage
Industrial Systems
--Process Control
--Intelligent Instrumentation
Computer Systems
--Computers
--Network Servers
DESCRIPTION
The X40430/31/34/35 combines power-on reset control,
watchdog timer, supply voltage supervision, second and
third voltage supervision, manual reset, and Block Lock
TM
protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low V
CC
detection circuitry protects the user's system
from low voltage conditions, resetting the system when
V
CC
falls below the minimum V
TRIP1
point. RESET/
RESET is active until V
CC
returns to proper operating
BLOCK DIAGRAM
V3FAIL
V2FAIL
WDO
MR
LOWLINE
RESET
RESET
X40430/34
X40431/35
V3 Monitor
Logic
V2 Monitor
Logic
Fault Detection
Register
Status
Register
EEPROM
Array
Data
Register
Command
Decode Test
& Control
Logic
Power on,
Manual Reset
Low Voltage
Reset
Generation
V
CC
Monitor
Logic
V3MON
V2MON
SDA
WP
SCL
V
CC
(V1MON)
+
-
+
-
Watchdog
and
Reset Logic
V
TRIP3
+
-
V
TRIP2
V
TRIP1
*X40430/31=
V
CC
or
V2MON*
V2MON
X40434/35 =V
CC
Preliminary Datasheet
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
2 of 26
REV 1.3.16 7/13/02
www.xicor.com
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a power
fail warning or monitors different power supply voltage.
Three common low voltage combinations are available.
However, Xicor's unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
specific system level requirements or to fine-tune the
threshold for applications requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor's Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I
2
C bus.
The device utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
*Voltage monitor requires Vcc to operate. Others are independent of Vcc.
PIN CONFIGURATION
Device
Expected System
Voltages
Vtrip1(V)
Vtrip2(V)
Vtrip3(V)
POR
(system)
X40430/31
-A
-B
-C
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
2.04.75*
4.554.65*
4.354.45*
2.953.05*
1.704.75
2.852.95
2.552.65
2.152.25
1.704.75
1.651.75
1.651.75
1.651.75
RESET = X40430
RESET = X40431
X40434/35
-A
-B
-C
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3 or 3.3V; 1.2V
2.04.75*
4.554.65*
4.554.65*
4.554.65*
0.903.50*
1.251.35*
1.251.35*
0.951.05*
1.704.75
3.053.15
2.852.95
2.852.95
RESET = X40434
RESET = X40435
PIN DESCRIPTION
Pin
Name
Function
1
V2FAIL
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and goes
HIGH when V2MON exceeds V
TRIP2
. There is no power up reset delay circuitry on this pin.
2
V2MON
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when not used.
The V2MON comparator is supplied by V2MON (X40430/31) or by the V
CC
input (X40434/35).
3
LOWLINE
Early Low V
CC
Detect.
This CMOS output signal goes LOW when
V
CC
< V
TRIP1
and goes high when
V
CC
> V
TRIP1
.
4
NC
No connect.
5
MR
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t
PURST
thereafter.
V3MON
V
SS
V
CC
SDA
SCL
3
2
4
1
12
13
11
14
LOWLINE
NC
RESET
7
6
5
8
9
10
V2MON
MR
WP
3
2
4
1
12
13
11
14
7
6
5
8
9
10
V3FAIL
WDO
V2FAIL
V3MON
V
CC
SDA
SCL
WP
V3FAIL
WDO
V
SS
LOWLINE
NC
RESET
V2MON
MR
V2FAIL
X40430/34
X40431/35
14-Pin SOIC, TSSOP
14-Pin SOIC, TSSOP
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
3 of 26
REV 1.3.16 7/13/02
www.xicor.com
6
RESET/
RESET
RESET Output.
(X40431/35) This open drain pin is an active LOW output which goes LOW whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
RESET Output.
(X40430/34) This pin is an active HIGH CMOS output which goes HIGH whenever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the programmed
time period (t
PURST
) on power up. It will also stay active until manual reset is released and for t
PURST
thereafter.
7
V
SS
Ground
8
SDA
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
9
SCL
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
10
WP
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10M
typical).
11
V3MON
V3 Voltage Monitor Input.
When the V3MON input is less than the V
TRIP3
voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V
SS
or
V
CC
when not used. The
V3MON comparator is supplied by the V3MON input.
12
V3FAIL
V3 Voltage Fail Output.
This open drain output goes LOW when V3MON is less than V
TRIP3
and goes
HIGH when V3MON exceeds V
TRIP3
. There is no power up reset delay circuitry on this pin.
13
WDO
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
14
V
CC
Supply Voltage
PIN DESCRIPTION
(Continued)
Pin
Name
Function
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40430/31/34/35 activates a
Power On Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
It prevents the system microprocessor from starting
to operate with insufficient voltage.
It prevents the processor from operating prior to sta-
bilization of the oscillator.
It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP1
threshold value
for t
PURST
(selectable) the circuit releases the RESET
(X40431/35) and RESET (X40430/34) pin allowing the
system to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
PURST
there-
after.
V
CC
MR
System
Reset
Manual
Reset
X40430/34
RESET
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
4 of 26
REV 1.3.16 7/13/02
www.xicor.com
Low Voltage V
CC
(V1 Monitoring)
During operation, the X40430/31/34/35 monitors the
V
CC
level and asserts RESET/RESET if supply voltage
falls below a preset minimum V
TRIP1
. The RESET/
RESET signal prevents the microprocessor from oper-
ating in a power fail or brownout condition. The
RESET/RESET signal remains active until the voltage
drops below 1V. It also remains active until V
CC
returns
and exceeds V
TRIP1
for
t
PURST
.
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
TRIP2
. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
For the X40430 and X40431 the V2FAIL signal remains
active until the V2MON drops below 1V (V2MON
fall-
ing). It also remains active until V2MON returns and
exceeds V
TRIP2
. This voltage sense circuitry monitors
the power supply connected to V2MON pin. If V
CC
= 0,
V2MON can still be monitored.
For the X40434 and X40435, the V2FAIL signal
remains active until V
CC
drops below 1V and remains
active until V2MON returns and exceeds V
TRIP2
. This
sense circuitry is powered by V
CC
. If V
CC
=0, V2MON
cannot be monitored.
Low Voltage V3 Monitoring
The X40430/31/34/35 also monitors a third voltage
level and asserts V3FAIL if the voltage falls below a
preset minimum V
TRIP3
. The V3FAIL signal is either
ORed with RESET to prevent the microprocessor from
operating in a power fail or brownout condition or used
to interrupt the microprocessor with notification of an
impending power failure. The V3FAIL signal remains
active until the V3MON drops below 1V (V3MON fall-
ing). It also remains active until V3MON returns and
exceeds V
TRIP3
.
This voltage sense circuitry monitors the power supply
connected to V3MON pin. If V
CC
= 0, V3MON can still
be monitored.
Early Low V
CC
Detection (LOWLINE)
This CMOS output goes LOW earlier than RESET/
RESET whenever V
CC
falls below the V
TRIP1
voltage
and returns high when V
CC
exceeds the V
TRIP1
volt-
age. There is no power up delay circuitry (t
PURST
) on
this pin.
Figure 2. Two Uses of Multiple Voltage Monitoring
6-10V
V
CC
5V
V3MON
X40431-A
Unreg.
Supply
V
CC
X40431-B
RESET
V2FAIL
System
V
CC
Reset
V2FAIL
V3FAIL
System
Reset
Notice: No external components required to monitor three voltages.
1M
V3MON
V3FAIL
V2MON
5V
Reg
3.0V
Reg
1.8V
Reg
3.3V
390K
V2MON
RESET
Power
Fail
Interrupt
V
CC
(1.7V)
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
5 of 26
REV 1.3.16 7/13/02
www.xicor.com
Figure 3. V
TRIPX
Set/Reset Conditions
V
CC
/V2MON/V3MON
V
TRIPX
V
P
t
WC
A0h
0
7
7
0
7
0
SCL
WDO
SDA
(X = 1, 2, 3)
00h
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in the
Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits
by writing to the X40430/31/34/35 control register (also
refer to page 20).
Figure 4. Watchdog Restart
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
The X40430 is shipped with standard V1, V2 and V3
threshold (V
TRIP1,
V
TRIP2,
V
TRIP3
) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430/
31/34/35 trip points may be adjusted. The procedure is
described below, and uses the application of a high volt-
age control signal.
Setting a V
TRIPx
Voltage (x=1, 2, 3)
There are two procedures used to set the threshold
voltages (V
TRIPx
), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V
TRIPx
is 2.9 V and the new
V
TRIPx
is 3.2 V, the new voltage can be stored directly
into the V
TRIPx
cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
"reset" the V
TRIPx
voltage before setting the new value.
Setting a Higher V
TRIPx
Voltage (x=1, 2, 3)
To set a V
TRIPx
threshold to a new voltage which is higher
than the present threshold, the user must apply the
desired V
TRIPx
threshold voltage to the corresponding
input pin Vcc(V1MON), V2MON or V3MON. Then, a pro-
gramming voltage (Vp) must be applied to the WDO pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by the
Byte Address 01h for V
TRIP1
, 09h for V
TRIP2
, and 0Dh for
V
TRIP3
, and a 00h Data Byte in order to program V
TRIPx
.
The STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be brought
LOW to complete the operation. To check if the V
TRIPX
has been set, set VXMON to a value slightly greater than
V
TRIPX
(that was previously set). Slowly ramp down
VXMON and observe when the corresponding outputs
(LOWLINE, V2FAIL and V3FAIL) switch. The voltage at
which this occurs is the V
TRIPX
(actual).
SCL
SDA
.6s
1.3s
WDT Reset
Start
Stop
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
6 of 26
REV 1.3.16 7/13/02
www.xicor.com
C
ASE
A
Now if the desired V
TRIPX
is greater than the V
TRIPX
(actual), then add the difference between V
TRIPX
(desired) V
TRIPX
(actual) to the original V
TRIPX
desired. This is your new V
TRIPX
that should be applied
to VXMON and the whole sequence should be
repeated again (see Figure 5).
C
ASE
B
Now if the V
TRIPX
(actual), is higher than the V
TRIPX
(desired), perform the reset sequence as described in
the next section. The new V
TRIPX
voltage to be applied
to VXMON will now be: V
TRIPX
(desired) (V
TRIPX
(actual) V
TRIPX
(desired)).
Note: This operation does not corrupt the memory array.
Setting a Lower V
TRIPx
Voltage (x=1, 2, 3)
In order to set V
TRIPx
to a lower voltage than the
present value, then V
TRIPx
must first be "reset" accord-
ing to the procedure described below. Once V
TRIPx
has been "reset", then V
TRIPx
can be set to the desired
voltage using the procedure described in "Setting a
Higher V
TRIPx
Voltage".
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
TRIP1
, 0Bh for V
TRIP2
, and 0Fh for V
TRIP3
, followed
by 00h for the Data Byte in order to reset V
TRIPx
. The
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
After being reset, the value of V
TRIPx
becomes a nomi-
nal value of 1.7V or lesser.
Notes: 1. This operation does not corrupt the memory array.
2. Set V
CC
1.5(V2MON or V3MON), when setting
V
TRIP2
or V
TRIP3
respectively.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40430/31/34/
35 will not acknowledge any data bytes written after
the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to "1" prior to a write to the
Control Register.
7
6
5
4
3
2
1
0
PUP1 WD1
WD0
BP
0
RWEL WEL PUP0
Figure 5. Sample V
TRIP
Reset Circuit
1
6
2
7
14
13
9
8
X4043X
V
TRIP1
Adj.
V
P
SDA
SCL
C
Adjust
Run
V2FAIL
V
TRIP2
Adj.
RESET
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
7 of 26
REV 1.3.16 7/13/02
www.xicor.com
Figure 6. V
TRIPX
Set/Reset Sequence (X = 1, 2, 3)
V
TRIPX
Programming
Apply V
CC
and Voltage
Decrease V
X
Actual V
TRIPX -
Desired V
TRIPX
DONE
Set Higher V
X
Sequence
Error < MDE
| Error | < | MDE |
YES
NO
Error > MDE
+
> Desired V
TRIPX
to V
X
Desired
Present Value
V
TRIPX
<
Execute
No
YES
Execute
V
TRIPX
Reset Sequence
Set V
X
= desired V
TRIPX
New V
X
applied =
Old V
X
applied + | Error |
New V
X
applied =
Old V
X
applied - | Error |
Execute Reset V
TRIPX
Sequence
Output Switches?
Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error
Vx = V
CC
, VxMON
MDE
+
Desired Value
MDE
Acceptable
Error Range
Error = Actual - Desired
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a "1" to the WEL bit and
zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a "0" to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
8 of 26
REV 1.3.16 7/13/02
www.xicor.com
BP: Block Protect Bits (Nonvolatile)
The Block Protect Bit BP, determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bit will
prevent write operations to half or none of the array.
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t
PURST
time delay. The nominal power up times are
shown in the following table.
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as qxys 001r in
binary, where xy are the WD bits, s is the BP bit and
qr are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms (max.)
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to `1' in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
Notes: 1. t
PURST
is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped disabled.
FAULT DETECTION REGISTER
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
BP
Protected Addresses
(Size)
Memory Array
Lock
0
None
None
1
100h 1FFh (256 bytes)
Upper Half of
Memory Array
PUP1
PUP0
Power on Reset Delay (
t
PURST
)
0
0
50ms
0
1
200ms (factory setting)
1
0
400ms
1
1
800ms
WD1
WD0
Watchdog Time Out Period
0
0
1.4 seconds
0
1
200 milliseconds
1
0
25 milliseconds
1
1
disabled (factory setting)
7
6
5
4
3
2
1
0
LV1F
LV2F
LV3F
WDF
MRF
0
0
0
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
9 of 26
REV 1.3.16 7/13/02
www.xicor.com
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the FDR is defaulted to all "0". The sys-
tem needs to initialize this register to all "1" before the
actual monitoring can take place. In the event of any
one of the monitored sources fail. The corresponding
bit in the register will change from a "1" to a "0" to indi-
cate the failure. At this moment, the system should per-
form a read to the register and note the cause of the
reset. After reading the register the system should
reset the register back to all "1" again. The state of the
FDR can be read at any time by performing a random
read at address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one byte
of data is read by the register read operation.
MRF, Manual Reset Fail Bit (Volatile)
The MRF bit will be set to "0" when Manual Reset input
goes active.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to "0" when the WDO goes
active.
LV1F, Low V
CC
Reset Fail Bit (Volatile)
The LV1F bit will be set to "0" when V
CC
(V1MON) falls
below V
TRIP1
.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to "0" when V2MON falls below
V
TRIP2
.
LV3F, Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to "0" when the V3MON falls
below V
TRIP3
.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 8.
Serial Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
10 of 26
REV 1.3.16 7/13/02
www.xicor.com
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 9.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled, so
the device will not respond to any requests from the mas-
ter. The SDA output is at high impedance. See Figure 10.
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 9. Acknowledge Response From Receiver
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
SCL from
Master
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
11 of 26
REV 1.3.16 7/13/02
www.xicor.com
Figure 10. Byte Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it "rolls over" and
goes back to `0' on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10 through
15, and the last 6 bytes are written to locations 0
through 5. Afterwards, the address counter would point
to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new
data overwrites the previous data, one byte at a time.
Figure 11. Page Write Operation
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1
n
16)
1 0 1 0
0
0
address
address
10
5 Bytes
n-1
7 Bytes
address
= 6
address pointer
ends here
Addr = 7
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
12 of 26
REV 1.3.16 7/13/02
www.xicor.com
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full data
byte plus its associated ACK is sent, then the device
will reset itself without performing the write. The con-
tents of the array will not be effected.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master's byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 13.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See figure 15 for the
address, acknowledge, and data transfer sequence.
Figure 13. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a "dummy" write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condi-
tion and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 16 for the
address, acknowledge, and data transfer sequence.
ACK
Returned?
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
Continue Normal
Read or Write
Command Sequence
PROCEED
YES
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
13 of 26
REV 1.3.16 7/13/02
www.xicor.com
A similar operation called "Set Current Address" where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter "rolls
over" to address 0000h and the device continues to out-
put data for each acknowledge received. See Figure 17
for the acknowledge and data transfer sequence.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
General Purpose Memory Organization, A8:A0
Address: 000h to 1FFh
General Purpose Memory Array Configuration
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
a device type identifier that is always `101x'. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
next two bits are `0'.
next bit that becomes the MSB of the address.
Figure 14. X40430/31/34/35 Addressing
Memory Address
A8:A0
000h
0FFh
100h
1FFh
Lower 256 bytes
Upper 256 bytes
Block Protect Option
General Purpose Memory
Control Register
Fault Detection Register
1
1
0
0
1
1
0
1
A8 R/W
Word Address
Slave Byte
1
0
1
0
1
1
0
0
0
0
0
0
R/W
R/W
General Purpose Memory
Control Register
Fault Detection Register
A7
1
A6 A5
A4
A1
A0
1
A3 A2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 15. Current Address Read Sequence
.
S
t
a
r
t
S
t
o
p
Slave
Address
Data
SDA Bus
Signals from
the Slave
Signals from
the Master
1
A
C
K
1 0 1 0
0
0
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
14 of 26
REV 1.3.16 7/13/02
www.xicor.com
last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Operational Notes
The device powers-up in the following state:
The device is in the low power standby state.
The WEL bit is set to `0'. In this state it is not possible
to write to the device.
SDA pin is the input mode.
RESET/RESET Signal is active for
t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Figure 17. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
Figure 16. Random Address Read Sequence
0
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
1 0 1
0
0
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
15 of 26
REV 1.3.16 7/13/02
www.xicor.com
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... 65C to +135C
Storage temperature ........................ 65C to +150C
Voltage on any pin with
respect to V
SS
......................................1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
*See Ordering Info
Temperature
Min.
Max.
Commercial
0C
70C
Industrial
40C
+85C
Version
Chip Supply
Voltage
Monitored*
Voltages
X40430/31
2.7V to 5.5V
1.7V to 5.5V
X40434/35
2.7V to 5.5V
1.0V to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Min.
Typ.
(4)
Max.
Unit
Test Conditions
I
CC1
(1)
Active Supply Current (
V
CC
) Read
1.5
mA
V
IL
=
V
CC
x 0.1
V
IH
=
V
CC
x 0.9,
f
SCL
= 400kHz
I
CC2
(1)
Active Supply Current (
V
CC
) Write
3.0
mA
I
SB1
(1)(6)
Standby Current (
V
CC
) AC (WDT off)
6
10
A
V
IL
=
V
CC
x 0.1
VIH =
V
CC
x 0.9
f
SCL
, f
SDA
= 400kHz
I
SB2
(2)(6)
Standby Current (
V
CC
) DC (WDT on)
25
30
A
V
SDA
= V
SCL
= V
CC
Others = GND or V
CC
I
LI
Input Leakage Current (SCL, MR,
WP)
10
A
V
IL
= GND to
V
CC
I
LO
Output Leakage Current (SDA,
V2FAIL, V3FAIL, WDO, RESET)
10
A
V
SDA
= GND to
V
CC
Device is in Standby
(2)
V
IL
(3)
Input LOW Voltage (SDA, SCL, MR,
WP)
-0.5
V
CC
x 0.3
V
V
IH
(3)
Input HIGH Voltage (SDA, SCL, MR,
WP)
V
CC
x 0.7
V
CC
+ 0.5
V
V
HYS
(6)
Schmitt Trigger Input Hysteresis
Fixed input level
V
CC
related level
0.2
.05 x
V
CC
V
V
V
OL
Output LOW Voltage (SDA, RESET/
RESET, LOWLINE, V2FAIL,
V3FAIL, WDO)
0.4
V
I
OL
= 3.0mA (2.7-5.5V)
I
OL
= 1.8mA (2.7-3.6V)
V
OH
Output (RESET, LOWLINE) HIGH
Voltage
V
CC
0.8
V
CC
0.4
V
I
OH
= -1.0mA (2.7-5.5V)
I
OH
= -0.4mA (2.7-3.6V)
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
16 of 26
REV 1.3.16 7/13/02
www.xicor.com
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
WC
after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V
IL
Min. and V
IH
Max. are for reference only and are not tested.
(4) At 25C, V
CC
= 3V
(5) See ordering information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)
CAPACITANCE
Note:
(1) This parameter is not 100% tested.
V
CC
Supply
V
TRIP1
(5)
V
CC
Trip Point Voltage Range
2.0
4.75
V
4.55
4.6
4.65
V
X40430/31-A, X40434/35
4.35
4.4
4.45
V
X40430/31-B
2.85
2.9
2.95
V
X40430/31-C
Second Supply Monitor
I
V2
V2MON Current
15
A
V
TRIP2
(5)
V2MON Trip Point Voltage Range
1.7
0.9
4.75
3.5
V
V
x40430/31
x40434/35
2.85
2.9
2.95
V
X40430/31-A
2.55
2.6
2.65
V
X40430/31-B
2.15
2.2
2.25
V
X40430/31-C
1.25
1.3
1.35
V
X40434/35-A&B
0.95
1.0
1.05
V
X40434/35-C
t
RPD2
(6)
V
TRIP2
to V2FAIL
5
s
Third Supply Monitor
I
V3
V3MON Current
15
A
V
TRIP3
(5)
V3MON Trip Point Voltage Range
1.7
4.75
V
1.65
1.7
1.75
V
X40430/31
3.05
3.1
3.15
V
X40434/35-A
2.85
2.9
2.95
V
X40434/35-B&C
t
RPD3
(6)
V
TRIP3
to V3FAIL
5
s
Symbol
Parameter
Max.
Unit
Test Conditions
C
OUT
(1)
Output Capacitance (SDA, RESET/RESET, LOWLINE,
V2FAIL,V3FAIL, WDO)
8
pF
V
OUT
= 0V
C
IN
(1)
Input Capacitance (SCL, WP, MR) 6
pF
V
IN
= 0V
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Min.
Typ.
(4)
Max.
Unit
Test Conditions
+
V
REF
t
RPDX
= 5s worst case
Output Pin
VxMON
R
C
V = 100mV
V
V
ref
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
17 of 26
REV 1.3.16 7/13/02
www.xicor.com
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V
CC
= 5V
A.C. TEST CONDITIONS
SYMBOL TABLE
Input pulse levels
V
CC
x 0.1 to
V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing levels
V
CC
x 0.5
Output load
Standard output load
5V
SDA
30pF
V2MON, V3MON
4.6K
RESET
30pF
2.06K
V2FAIL,
V
CC
4.6K
30pF
WDO
V3FAIL
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
WAVEFORM
INPUTS
OUTPUTS
to HIGH
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
18 of 26
REV 1.3.16 7/13/02
www.xicor.com
A.C. CHARACTERISTICS
Note:
(1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
Symbol
Parameter
Min.
Max.
Unit
f
SCL
SCL Clock Frequency
400
kHz
t
IN
Pulse width Suppression Time at inputs
50
ns
t
AA
SCL LOW to SDA Data Out Valid
0.1
0.9
s
t
BUF
Time the bus free before start of new transmission
1.3
s
t
LOW
Clock LOW Time
1.3
s
t
HIGH
Clock HIGH Time
0.6
s
t
SU:STA
Start Condition Setup Time
0.6
s
t
HD:STA
Start Condition Hold Time
0.6
s
t
SU:DAT
Data In Setup Time
100
ns
t
HD:DAT
Data In Hold Time
0
s
t
SU:STO
Stop Condition Setup Time
0.6
s
t
DH
Data Output Hold Time
50
ns
t
R
SDA and SCL Rise Time
20 +.1Cb
(1)
300
ns
t
F
SDA and SCL Fall Time
20 +.1Cb
(1)
300
ns
t
SU:WP
WP Setup Time
0.6
s
t
HD:WP
WP Hold Time
0
s
Cb
Capacitive load for each bus line
400
pF
t
SU:STO
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
R
t
DH
t
AA
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
19 of 26
REV 1.3.16 7/13/02
www.xicor.com
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Note:
(1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
WC
(1)
Write Cycle Time
5
10
ms
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1
Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8
th
Bit of Last Byte
ACK
Stop
Condition
Start
Condition
V2MON or
V2FAIL or
t
R
t
F
t
RPDX
V
RVALID
V3MON
V3FAIL
LOWLINE or
V
CC
V
TRIPX
t
RPDX
t
RPDX
t
RPDL
t
RPDL
t
RPDL
X = 2, 3
[
]
[
]
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
20 of 26
REV 1.3.16 7/13/02
www.xicor.com
RESET/RESET/MR Timings
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25C, V
CC
= 5V)
Notes: (1) V
CC
= 5V at 25C.
(2) Values based on characterization data only.
Symbol
Parameters
Min.
Typ.
(1)
Max.
Unit
t
RPD1
(2)
t
RPDL
V
TRIP1
to RESET/RESET (Power down only)
V
TRIP1
to LOWLINE
5
s
t
LR
LOWLINE to RESET/RESET delay (Power down only) [= t
RPD1
-t
RPDL
]
500
ns
t
RPDX
(2)
V
TRIP2
to V2FAIL, or V
TRIP3
to V3FAIL (x = 2, 3)
5
s
t
PURST
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
PUP1=1, PUP0=1
50
(2)
200
400
(2)
800
(2)
ms
ms
ms
ms
t
F
V
CC,
V2MON
,
V3MON
,
Fall Time
20
mV
/
s
t
R
V
CC,
V2MON
,
V3MON
,
Rise Time
20
mV
/
s
V
RVALID
Reset Valid V
CC
1
V
t
MD
(2)
MR to RESET/ RESET delay (activation only)
500
ns
t
in1
Pulse width for MR
5
s
t
WDO
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1=1, WD0=1 (factory setting)
1.4
(2)
200
(2)
25
OFF
s
ms
ms
t
RST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1
100
200
300
ms
t
RST2
Watchdog Reset Time Out Delay WD1=1, WD0=0
12.5
25
37.5
ms
t
RSP
Watchdog timer restart pulse width
1
s
V
CC
V
TRIP1
RESET
RESET
t
PURST
t
PURST
t
R
t
F
t
RPD1
V
RVALID
MR
t
MD
t
IN1
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
21 of 26
REV 1.3.16 7/13/02
www.xicor.com
Watchdog Time Out For 2-Wire Interface
V
TRIPX
Set/Reset Conditions
< t
WDO
t
RST
WDO
SDA
Start
t
WDO
t
RST
SCL
Start
t
RSP
WDT
Restart
Start
SDA
SCL
Minimum Sequence to Reset WDT
Clockin (0 or 1)
SCL
SDA
V
CC
/V2MON/V3MON
(V
TRIPX
)
WDO
t
TSU
t
THD
t
VPH
t
VPS
V
P
t
WC
t
VPO
A0h
0
7
7
0
7
*0Dh
sets V
TRIP1
sets V
TRIP2
sets V
TRIP3
*01h
*09h
*03h
*0Bh
*0Fh
resets V
TRIP3
resets V
TRIP2
resets V
TRIP1
0
Start
* all others reserved
00h
*
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
22 of 26
REV 1.3.16 7/13/02
www.xicor.com
V
TRIP1
, V
TRIP2
, V
TRIP3
Programming Specifications: V
CC
= 2.05.5V; Temperature = 25C
Parameter
Description
Min.
Max.
Unit
t
VPS
WDO Program Voltage Setup time
10
s
t
VPH
WDO Program Voltage Hold time
10
s
t
TSU
V
TRIPX
Level Setup time
10
s
t
THD
V
TRIPX
Level Hold (stable) time
10
s
t
WC
V
TRIPX
Program Cycle
10
ms
t
VPO
Program Voltage Off time before next cycle
1
ms
V
P
Programming Voltage
15
18
V
V
TRAN1
V
TRIP1
Set Voltage Range
2.0
4.75
V
V
TRAN2
V
TRIP2
Set Voltage Range X40430/31
1.7
4.75
V
V
TRAN2A
V
TRIP2
Set to Voltage Range X40434/35
0.9
3.5
V
V
TRAN3
V
TRIP3
Set Voltage Range
1.7
4.75
V
V
tv
V
TRIPX
Set Voltage variation after programming (-40 to +85C).
-25
+25
mV
t
VPS
WDO Program Voltage Setup time
10
s
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
23 of 26
REV 1.3.16 7/13/02
www.xicor.com
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.020 (0.51)
Pin 1
Pin 1 Index
0.050 (1.27)
0.336 (8.55)
0.345 (8.75)
0.004 (0.10)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
14-Lead Plastic Small Outline Gullwing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"Typical
0.030"Typical
14 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 8
X 45
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
24 of 26
REV 1.3.16 7/13/02
www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
25 of 26
REV 1.3.16 7/13/02
www.xicor.com
ORDERING INFORMATION
PART MARK INFORMATION
Monitored
V
CC
Supplies
V
TRIP1
Range
V
TRIP2
Range
V
TRIP3
Range
Package
Operating
Temperature
Range
Part Number
with RESET
Part Number
with RESET
1.7-5.5
4.6V50mV 2.9V50mV 1.7V50mV
14L SOIC
0
o
C70
o
C
X40430S14-A
X40431S14-A
-40
o
C85
o
C
X40430S14I-A
X40431S14I-A
14L TSSOP
0
o
C70
o
C
X40430V14-A
X40431V14-A
-40
o
C85
o
C
X40430V14I-A
X40431V14I-A
1.7-5.5
4.4V50mV 2.6V50mV 1.7V50mV
14L SOIC
0
o
C70
o
C
X40430S14-B
X40431S14-B
-40
o
C85
o
C
X40430S14I-B
X40431S14I-B
14L TSSOP
0
o
C70
o
C
X40430V14-B
X40431V14-B
-40
o
C85
o
C
X40430V14I-B
X40431V14I-B
1.7-3.6
2.9V50mV 2.2V50mV 1.7V50mV
14L SOIC
0
o
C70
o
C
X40430S14-C
X40431S14-C
-40
o
C85
o
C
X40430S14I-C
X40431S14I-C
14L TSSOP
0
o
C70
o
C
X40430V14-C
X40431V14-C
-40
o
C85
o
C
X40430V14I-C
X40431V14I-C
1.3-5.5
4.6V50mV 1.3V50mV 3.1V50mV
14L SOIC
0
o
C70
o
C
X40434S14-A
X40435S14-A
-40
o
C85
o
C
X40434S14I-A
X40435S14I-A
14L TSSOP
0
o
C70
o
C
X40434V14-A
X40435V14-A
-40
o
C85
o
C
X40434V14I-A
X40435V14I-A
1.3-5.5
4.6V50mV 1.3V50mV 2.9V50mV
14L SOIC
0
o
C70
o
C
X40434S14-B
X40435S14-B
-40
o
C85
o
C
X40434S14I-B
X40435S14I-B
14L TSSOP
0
o
C70
o
C
X40434V14-B
X40435V14-B
-40
o
C85
o
C
X40434V14I-B
X40435V14I-B
1.0-5.5
4.6V50mV 1.0V50mV 2.9V50mV
14L SOIC
0
o
C70
o
C
X40434S14-C
X40435S14-C
-40
o
C85
o
C
X40434S14I-C
X40435S14I-C
14L TSSOP
0
o
C70
o
C
X40434V14-C
X40435V14-C
-40
o
C85
o
C
X40434V14I-C
X40435V14I-C
14-Lead Package
X4043XX
YYWWXX
I Industrial
0/1/4/5
Package - S/V
Blank Commercial
WW Workweek
YY Year
A, B, or C
X40430/X40431/X40434/X40435 Preliminary
Characteristics subject to change without notice.
26 of 26
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2001 Patents Pending
REV 1.3.16 7/13/02
www.xicor.com