Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending

7078 1.1 8/9/99 CM

Characteristics subject to change without notice

WATCHDOG

TIMER

X5001

CPU Supervisor

Features

· 200ms Power On Reset Delay
· Low Vcc Detection and Reset Assertion

--Five Standard Reset Threshold Voltages
--Adjust Low Vcc Reset Threshold Voltage using

special programming sequence

--Reset Signal Valid to Vcc=1V

· Selectable Nonvolatile Watchdog Timer

--0.2, 0.6, 1.4 seconds
--Off selection
--Select settings through software

· Long Battery Life With Low Power Consumption

--<50

A Max Standby Current, Watchdog On

--<1

A Max Standby Current, Watchdog Off

· 2.7V to 5.5V Operation
· SPI Mode 0 interface
· Built-in Inadvertent Write Protection

--Power-Up/Power-Down Protection Circuitry
--Watchdog Change Latch

· High Reliability
· Available Packages

--8-Lead TSSOP
--8-Lead SOIC
--8 Pin PDIP

DESCRIPTION

This device combines three popular functions, Power on
Reset, Watchdog Timer, and Supply Voltage Supervision
in one package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET signal after a
selectable time-out interval. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.

The user's system is protected from low voltage condi-
tions by the device's low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET is asserted until Vcc returns to proper
operating levels and stabilizes. Five industry standard
V

TRIP

thresholds are available, however, Xicor's unique

circuits allow the thresold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.

The device utilizes Xicor's proprietary Direct Write

cell

for the Watchdog TImer control bits and the V

TRIP

stor-

age element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.

Block Diagram

DATA

COMMAND

DECODE &

CONTROL

LOGIC

SCK

CS/WDI

7036 FRM 01

WATCHDOG

TRANSITION

DETECTOR

RESET &

WATCHDOG

TIMEBASE

POWER ON/

GENERATION

TRIP

RESET

LOW VOLTAGE

X5001

PIN DESCRIPTION

Figure 1. PIN CONFIGURATION

PIN

(SOIC/PDIP)

PIN

TSSOP

Name

Function

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the Watch-

dog timer. The absence of a HIGH to LOW transition within the watchdog time-
out period results in RESET/RESET going active.

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data

out on this pin. The falling edge of the serial clock (SCK) clocks the data out.

Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.

SCK

Serial Clock.

The Serial Clock controls the serial bus timing for data input and

output. The rising edge of SCK latches in the opcode, address, or watchdog
bits present on the SI pin. The falling edge of SCK changes the data output on
the SO pin.

TRIP

Program Enable.

When V

is LOW, the V

TRIP

point is fixed at the last

valid programmed level. To readjust the V

TRIP

level, requires that the VPE pin

be pulled to a high voltage (15-18V).

Ground

Supply Voltage

RESET

Reset Output

RESET is an active LOW, open drain output which goes active

whenever Vcc falls below the minimum Vcc sense level. It will remain active un-
til Vcc rises above the minimum Vcc sense level for 200ms. RESET goes active
if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW
longer than the selectable Watchdog time-out period. A falling edge of CS/WDI
will reset the Watchdog Timer. RESET goes active on power up at 1V and re-
mains active for 200ms after the power supply stabilizes.

3-5,10-12

No internal connections

8 Lead SOIC/PDIP

X5001

CS/WDI

RESET

VCC

VSS

SCK

VSS

CS/WDI

8 Lead TSSOP

X5001

RESET

X5001

PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X5001 activates a Power On
Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the sys-
tem microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator. When
Vcc exceeds the device V

TRIP

value for 200ms (nominal)

the circuit releases RESET, allowing the processor to
begin executing code.

Low voltage monitoring

During operation, the X5001 monitors the V

level and

asserts RESET if supply voltage falls below a preset mini-
mum V

TRIP

. The RESET signal prevents the microproces-

sor from operating in a power fail or brownout condition.
The RESET signal remains active until the voltage drops
below 1V. It also remains active until Vcc returns and
exceeds V

TRIP

for 200ms.

watchdog timer

The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time-
out period. The state of two nonvolatile control bits in the
Watchdog Register determine the watchdog timer period.

Vcc Threshold Reset Procedure

The X5001 is shipped with a standard Vcc threshold
(V

TRIP

) voltage. This value will not change over normal

operating and storage conditions. However, in applica-
tions where the standard V

TRIP

is not exactly right, or if

higher precision is needed in the V

TRIP

value, the X5001

threshold may be adjusted. The procedure is described
below, and requires the application of a high voltage con-
trol signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher volt-

age value. For example, if the current V

TRIP

is 4.4V and

the new V

TRIP

is 4.6V, this procedure will directly make

the change. If the new setting is to be lower than the cur-
rent setting, then it is necessary to reset the trip point
before setting the new value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold voltage to the Vcc pin and tie the W

pin to the

programming voltage V

. Then a V

TRIP

programming

command sequence is sent to the device over the SPI
interface. This V

TRIP

programming sequence consists of

pulling CS LOW, then clocking in data 03h, 00h and 01h.
This is followed by bringing CS HIGH then LOW and
clocking in data 02h, 00h, and 01h (in order) and bringing
CS HIGH. This initiates the V

TRIP

programming

sequence. V

is brought LOW to end the operation.

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a "native" volt-

age level. For example, if the current V

TRIP

is 4.4V and

the new V

TRIP

must be 4.0V, then the V

TRIP

must be

reset. When V

TRIP

is reset, the new V

TRIP

is something

less than 1.7V. This procedure must be used to set the
voltage to a lower value.

To reset the V

TRIP

voltage, apply greater than 3V to the

Vcc pin and tie the W

pin to the programming voltage

Vp. Then a V

TRIP

command sequence is sent to the

device over the SPI interface. This V

TRIP

programming

sequence consists of pulling CS LOW, then clocking in
data 03h, 00h and 01h. This is followed by bringing CS
HIGH then LOW and clocking in data 02h, 00h, and 03h
(in order) and bringing CS HIGH. This initiates the V

TRIP

programming sequence. V

is brought LOW to end the

operation.

X5001

Figure 2. Sample V

TRIP

Reset Circuit

Figure 3. Set V

TRIP

Level Sequence (Vcc=desired V

TRIP

value. )

Figure 4. Reset V

TRIP

Level Sequence (Vcc > 3V. )

X5001

TRIP

Adj.

RESET

4.7K

SCK

Adjust

Run

2 3 4

5 6

7 8

9 10

SCK

20 21 22 23

16 BITS

0001h

03h

2 3 4

5 6

7 8

9 10

20 21 22 23

16 BITS

0001h

02h

= 15-18V

2 3 4

5 6

7 8

9 10

SCK

20 21 22 23

16 BITS

0001h

03h

2 3 4

5 6

7 8

9 10

20 21 22 23

16 BITS

0003h

02h

= 15-18V

16 BITS

X5001

spi Interface

The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families.

The device monitors the CS/WDI line and asserts RESET
output if there is no activity within user selctable time-out
period. The device also monitors the Vcc supply and
asserts the RESET if Vcc falls below a preset minimum
(V

TRIP

). The device contains an 8-bit Watchdog Timer

All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.

Watchdog Timer Register

Watchdog Timer Control Bits

The Watchdog Timer Control bits, WD

and WD

, select

the Watchdog Time-out Period. These nonvolatile bits are
programmed with the Set Watchdog Timer (SWDT)
instruction.

Write Watchdog Register Operation

Changing the Watchdog Timer Register is a two step pro-
cess. First, the change must be enabled with by setting
the Watchdog Change Latch (see below). This instruction
is followed by the Set Watchdog Timer (SWDT) instruc-
tion, which includes the data to be written (Figure 5). Data
bits 3 and 4 contain the Watchdog settings and data bits
0, 1, 2, 5, 6 and 7 must be "0" .

Watchdog Change Latch

The Watchdog Change Latch must be SET before a Write
Watchdog Timer Operation is initiated. The Enable
Watchdog Change (EWDC) instruction will set the latch
and the Disable Watchdog Change (DWDC) instruction
will reset the latch (See Figure 2.) This latch is automati-
cally reset upon a power-up condition and after the com-
pletion of a valid nonvolatile write cycle.

Read Watchdog Timer Register Operation

If there is not a nonvolatile write in progress, the Read
Watchdog Timer instruction returns the setting of the
watchdog timer control bits. The other bits are reserved
and will return '0' when read. See Figure 3.

If a nonvolatile write is in progress, the Read Watchdog
Timer Register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a seperate Read
Watchdog Timer instruction should be used to determine
the current status of the Watchdog control bits.

RESET Operation

The RESET (X5001) output is designed to go LOW
whenever V

has dropped below the minimum trip point

and/or the Watchdog timer has reached its programmable
time-out limit.

The RESET output is an open drain output and requires a
pull up resistor.

Operational Notes

The device powers-up in the following state:

· The device is in the low power standby state.
· A HIGH to LOW transition on CS is required to enter an

active state and receive an instruction.

· SO pin is high impedance.
· The Watchdog Change Latch is reset.
· The RESET Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent inad-
vertent writes:

· A EWDC instruction must be issued to enable a change

to the watchdog timeout setting.

· CS must come HIGH at the proper clock count in order

to implement the requested changes to the watchdog
timeout setting.

Watchdog Control Bits

Watchdog Time-out

(Typical)

WD1

WD0

1.4 Seconds

600 Milliseconds

200 Milliseconds

Disabled

X5001

Table 1. Instruction Set Definition

Notes: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.

7038 FRM T03

Figure 1. Read Watchdog Timer setting

Figure 2. Enable Watchdog Change/Disable Watchdog Change Sequence

Instruction Format

Instruction Name and Operation

0000 0110

EWDC: Enable Watchdog Change Operation

0000 0100

DWDC: Disable Watchdog Change Operation

0000 0001

SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD

) (WD

)000

See Watchdog Timer Settings and Figure 3.

0000 0101

RWDT: Read Watchdog Timer control bits

SCK

RWDT

INSTRUCTION

...

SCK

HIGH IMPEDANCE

INSTRUCTION

(1 BYTE)

X5001

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

POWER-UP TIMING

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V.

Notes:

(1) V

min. and V

max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Units

Test Conditions

Min.

Typ.

Max.

CC1

Write Current (Active)

SCK = V

x 0.1/V

x 0.9 @ 5MHz,

SO = Open

CC2

Read Current (Active)

0.4

SCK = V

x 0.1/V

x 0.9 @ 5MHz,

SO = Open

SB1

Standby Current WDT=OFF

µA

CS = V

, V

= V

or V

, V

= 5.5V

SB2

Standby Current WDT=ON

µA

CS = V

, V

= V

or V

, V

= 5.5V

SB3

Standby Current WDT=ON

µA

CS = V

, V

= V

or V

, V

=3.6V

Input Leakage Current

0.1

µA

= V

to V

Output Leakage Current

0.1

µA

OUT

= V

to V

(1)

Input LOW Voltage

0.5

x0.3

(1)

Input HIGH Voltage

x0.7

+0.5

OL1

Output LOW Voltage

0.4

> 3.3V, I

= 2.1mA

OL2

Output LOW Voltage

0.4

2V < V

< 3.3V, I

= 1mA

OL3

Output LOW Voltage

0.4

2V, I

= 0.5mA

OH1

Output HIGH Voltage

0.8

> 3.3V, I

= 1.0mA

OH2

Output HIGH Voltage

0.4

2V < V

3.3V, I

= 0.4mA

OH3

Output HIGH Voltage

0.2

2V, I

= 0.25mA

OLRS

Reset Output LOW Voltage

0.4

= 1mA

Symbol

Parameter

Min.

Max.

Units

PUR

(2)

Power-up to Read Operation

PUW

(2)

Power-up to Write Operation

Symbol

Test

Max.

Units

Conditions

OUT

(2)

Output Capacitance (SO, RESET)

OUT

= 0V

(2)

Input Capacitance (SCK, SI, CS)

= 0V

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias ........................65°C to +135°C
Storage Temperature .............................65°C to +150°C
Voltage on any Pin with Respect to V

....... 1.0V to +7V

D.C. Output Current ....................................................5mA
Lead Temperature (Soldering, 10 seconds)............ 300°C

RECOMMENDED OPERATING CONDITIONS

7036 FRM T07

*COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

PT= Package, Temperature

Temp

Min.

Max.

Commercial

0°C

+70°C

Voltage Option

Supply Voltage Limits

1.8

1.8V to 3.6V

2.7 or -2.7A

2.7V to 5.5V

4.5 or -4.5A

4.5V to 5.5V

X5001

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Data Input Timing

Data Output Timing

Notes:

(3) This parameter is periodically sampled and not 100% tested.
(4) t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal

nonvolatile write cycle.

1.8V3.6V

2.7V5.5V

Symbol

Parameter

Min. Max.

Units

SCK

Clock Frequency

MHz

CYC

Cycle Time

1000

500

LEAD

CS Lead Time

400

200

LAG

CS Lag Time

400

200

Clock HIGH Time

400

200

Clock LOW Time

400

200

Data Setup Time

100

Data Hold Time

100

(3)

Input Rise Time

µs

(3)

Input Fall Time

µs

CS Deselect Time

250

150

(4)

Write Cycle Time

1.8V3.6V

2.7V5.5V

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

SCK

Clock Frequency

MHz

DIS

Output Disable Time

400

200

Output Valid from Clock Low

400

200

Output Hold Time

(3)

Output Rise Time

300

150

(3)

Output Fall Time

300

150

Figure 1. EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

OUTPUT

100pF

3.3K

RESET

30pF

1.64K

1.64

Input Pulse Levels

x 0.1 to V

x 0.9

Input Rise and Fall Times

10ns

Input and Output Timing Level

x0.5

X5001

Figure 1. Power-Up and Power-Down Timing

RESET Output Timing

Notes:

(5) This parameter is periodically sampled and not 100% tested.
PT = Package, Temperature

Figure 2. CS vs. RESET Timing

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Units

TRIP

Reset Trip Point Voltage, X5001PT-4.5A
Reset Trip Point Voltage, X5001PT-4.5
Reset Trip Point Voltage, X5001PT-2.7A
Reset Trip Point Voltage, X5001PT-2.7
Reset Trip Point Voltage, X5001PT-1.8

4.50
4.25
2.85
2.55
1.70

4.63
4.38
2.92
2.63
1.75

4.75
4.50
3.00
2.70
1.80

PURST

Power-up Reset Timeout

100

200

280

RPD

(5)

Detect to Reset/Output

500

(5)

Fall Time

0.1

(5)

Rise Time

0.1

RVALID

Reset Valid V

Symbol

Parameter

Min.

Typ.

Max.

Units

WDO

Watchdog Timeout Period,
WD

= 1, WD

= 0

= 0, WD

= 1

= 0, WD

= 0

100
450

200
600

1.4

300
800

ms
ms

sec

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Timeout

100

200

300

VCC

PURST

RPD

RESET (X5001)

0 Volts

TRIP

CST

RESET

WDO

RST

WDO

RST

X5001

TRIP

Programming Parameters

Parameter

Description

Min

Max

Units

VPS

TRIP

Program Enable Voltage Setup time

VPH

TRIP

Program Enable Voltage Hold time

PCS

TRIP

Programming CS inactive time

TSU

TRIP

Setup time

THD

TRIP

Hold (stable) time

TRIP

Write Cycle Time

VPO

TRIP

Program Enable Voltage Off time

(Between successive adjustments)

TRIP

Program Recovery Period

(Between successive adjustments)

Programming Voltage

TRAN

TRIP

Programmed Voltage Range

1.7

5.0

ta1

Initial V

TRIP

Program Voltage accuracy

(Vcc applied - V

TRIP

) (Programmed at 25

C.)

-0.1

+0.4

ta2

Subsequent V

TRIP

Program Voltage accuracy

[(Vcc applied - V

ta1

) - V

TRIP

. Programmed at 25

C.)

-25

+25

TRIP

Program Voltage repeatability

(Successive program operations. Programmed at 25

C.)

-25

+25

TRIP

Program variation after programming (0-75

C).

(Programmed at 25

C.)

-25

+25

TRIP

Programming parameters are periodically sampled and are not 100% Tested.

X5001

Watchdog Timer On (Vcc = 5V)

Watchdog Timer On (Vcc = 3V)

Watchdog Timer Off (Vcc = 3V, 5V)

40C

25C

90C

Temp (c)

Isb (uA)

Vcc Supply Current vs. Temperature (I

)

WDO

vs. Voltage/Temperature (WD1,0=1,1)

TRIP

vs. Temperature (programmed at 25°C)

WDO

vs. Voltage/Temperature (WD1,0=1,0)

PURST

vs. Temperature

WDO

vs. Voltage/Temperature (WD1,0 0=0,1)

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.7

3.1

4.5

90°C

25°C

40°C

Reset (seconds)

Voltage

5.025

5.000

4.975

3.525

3.500

3.475

2.525

2.500

2.475

Voltage

Temperature

Vtrip=5V

Vtrip=3.5V

Vtrip=2.5V

0.85

0.80

0.75

0.70

0.65

0.60

1.7

4.5

Reset (seconds)

Voltage

3.1

90°C

25°C

40°C

275

270

265

260

255

250

245

240

235

Degrees °C

280

Time (ms)

90°C

25°C

40°C

0.28

0.27

0.26

0.25

0.24

0.23

0.22

0.21

0.20

0.29

Reset (seconds)

Voltage

1.7

3.1

4.5

0.35

0.55

1.0

0.30

X5001

Part Mark Information

8-Lead TSSOP

501AG = 1.8 to 3.6V, 0 to +70°C, V

TRIP

=1.7-1.8V

YWW

XXXXX

501AH = 1.8 to 3.6V, -40 to +85°C, V

TRIP

=1.7-1.8V

501F = 2.7 to 5.5V, 0 to +70°C, V

TRIP

=2.55-2.7V

501G = 2.7 to 5.5V, -40 to +85°C, V

TRIP

=2.55-2.7V

501 = 4.5 to 5.5V, 0 to +70°C, V

TRIP

=4.25-4.5V

501I = 4.5 to 5.5V, -40 to +85°C, V

TRIP

=4.25-4.5V

8-Lead SOIC

X5001

YWW XX

AG = 1.8 to 3.6V, 0 to +70°C, V

TRIP

=1.7-1.8V

AH = 1.8 to 3.6V, -40 to +85°C, V

TRIP

=1.7-1.8V

F = 2.7 to 5.5V, 0 to +70°C, V

TRIP

=2.55-2.7V

G = 2.7 to 5.5V, -40 to +85°C, V

TRIP

=2.55-2.7V

I = 4.5 to 5.5V, -40 to +85°C, V

TRIP

=4.25-4.5V

501AN = 2.7 to 5.5V, 0 to +70°C, V

TRIP

=2.85-3.0V

501AP = 2.7 to 5.5V, -40 to +85°C, V

TRIP

=2.85-3.0V

501AL = 4.5 to 5.5V, 0 to +70°C, V

TRIP

=4.5-4.75V

501AM = 4.5 to 5.5V, -40 to +85°C, V

TRIP

=4.5-4.75V

AN = 2.7 to 5.5V, 0 to +70°C, V

TRIP

=2.85-3.0V

AP = 2.7 to 5.5V, -40 to +85°C, V

TRIP

=2.85-3.0V

AL = 4.5 to 5.5V, 0 to +70°C, V

TRIP

=4.5-4.75V

AM = 4.5 to 5.5V, -40 to +85°C, V

TRIP

=4.5-4.75V

Blank = 4.5 to 5.5V, 0 to +70°C, V

TRIP

=4.25-4.5V

YWW = year/work week device is packaged.

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices
from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue
production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976.
Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appro-
priate error detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and

whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result
in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure

of the life support device or system, or to affect its safety or effectiveness.

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