REV 1.1.6 6/25/02

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X5083

CPU Supervisor with 8Kbit SPI EEPROM

FEATURES

· Low V

detection and reset assertion

--Four standard reset threshold voltages

4.63V, 4.38V, 2.93V, 2.63V

--Re-program low V

reset threshold voltage

using special programming sequence.

--Reset signal valid to V

= 1V

· Selectable time out watchdog timer
· Long battery life with low power consumption

--<50µA max standby current, watchdog on
--<1µA max standby current, watchdog off
--<400µA max active current during read

· 8Kbits of EEPROM
· Save critical data with Block Lock

memory

--Block lock first or last page, any 1/4 or lower 1/2

of EEPROM array

· Built-in inadvertent write protection

--Write enable latch
--Write protect pin

· SPI Interface - 3.3MHz clock rate
· Minimize programming time

--16 byte page write mode
--5ms write cycle time (typical)

· SPI modes (0,0 & 1,1)
· Available packages

--8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP

APPLICATIONS

· Communications Equipment

--Routers, Hubs, Switches
--Set Top Boxes

· Industrial Systems

--Process Control
--Intelligent Instrumentation

· Computer Systems

--Desktop Computers
--Network Servers

· Battery Powered Equipment

RESET

SCK

VCC

VSS

RESET

SPI

VCC

VSS

X5083

Typical Application

2.7-5.0V

10K

BLOCK DIAGRAM

Watchdog

Timer

Command

Decode &

Control

Logic

SCK

CS/WDI

POR and Low

Generation

TRIP

RESET (X5083)

Voltage Reset

Protect Logic

8Kbits

EEPROM

Watchdog

Detector

Array

Status

Transition

Reset

Reset & Watchdog

Timebase

X5083

Standard V

TRIP

Level

Suffix

4.63V (+/-2.5%)

-4.5A

4.38V (+/-2.5%)

-4.5

2.93V (+/-2.5%)

-2.7A

2.63V (+/-2.5%)

-2.7

See "Ordering Information" on page 21 for

more details

For Custom Settings, call Xicor.

X5083

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DESCRIPTION

This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Super-
vision, and Block Lock Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.

Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to sta-
bilize before the processor can execute code.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller

fails to restart a timer within a selectable time out interval,
the device activates the RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting
the system when V

falls below the minimum V

trip

point. RESET is asserted until V

returns to the

proper operating level and stabilizes. Five industry
standard V

TRIP

thresholds are available, however, Xicor's

unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold
for applications requiring higher precision.

PIN CONFIGURATION

PIN DESCRIPTION

Pin

(SOIC/

PDIP)

Pin

TSSOP

Name

Function

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at a high

impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in the active power mode. Prior to the
start of any operation after power up, a HIGH to LOW transition on CS is required.

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The

absence of a HIGH to LOW transition within the watchdog time out period results in RESET
going active.

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses, and memory data

on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes
(Table 1), addresses and data MSB first.

SCK

Serial Clock.

The Serial Clock controls the serial bus timing for data input and output. The rising

edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.

Write Protect.

When WP is LOW, nonvolatile write operations to the memory are prohibited.

This "Locks" the memory to protect it against inadvertent changes when WP is HIGH, the
device operates normally.

Ground

Supply Voltage

RESET

Reset Output

. RESET is an active LOW, open drain output which goes active whenever V

falls below the minimum V

sense level. It will remain active until V

rises above the

minimum V

sense level for 250ms. RESET goes active if the watchdog timer is enabled and

CS remains either HIGH or LOW longer than the selectable watchdog time out period.
A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about
1V and remains active for 250ms after the power supply stabilizes.

SCK
SI
V

CS/WDI

1
2
3
4

8
7
6
5

8-Lead TSSOP

X5083

RESET

8-Lead SOIC, PDIP

X5083

CS/WDI

1
2
3
4

RESET

8
7
6
5

SCK
SI

X5083

Characteristics subject to change without notice.

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PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X5083 activates a power on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator.
RESET active also blocks communication to the device
through the SPI interface. When V

exceeds the

device V

TRIP

value for 200ms (nominal) the circuit

releases RESET, allowing the processor to begin exe-
cuting code. While V

< V

TRIP

communications to the

device are inhibited.

Low Voltage Monitoring

During operation, the X5083 monitors the V

level

and asserts RESET if supply voltage falls below a pre-
set minimum V

TRIP

. The RESET signal prevents the

microprocessor from operating in a power fail or
brownout condition and terminates any SPI communi-
cation in progress. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until V

returns and exceeds V

TRIP

for 200ms.

When V

falls below V

TRIP

, any communications in

progress are terminated and communications are
inhibited until V

exceeds V

TRIP

for t

PURST

Watchdog Timer

The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from

HIGH to LOW prior to the expiration of the watchdog time
out period. The state of two nonvolatile control bits in the
status register determine the watchdog timer period. The
microprocessor can change these watchdog bits with no
action taken by the microprocessor these bits remain
unchanged, even after total power failure.

Threshold Reset Procedure

The X5083 is shipped with a standard V

threshold

TRIP

) voltage. This value will not change over normal

operating and storage conditions. However, in applica-
tions where the standard V

TRIP

is not exactly right, or if

higher precision is needed in the V

TRIP

value, the

X5083 threshold may be adjusted. The procedure is
described below, and uses the application of a high
voltage control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher

voltage value. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

is 4.6V, this procedure will directly

make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold voltage to the V

pin and tie the WP pin to

the programming voltage V

. Then send a WREN com-

mand, followed by a write of Data 00h to address 01h.
CS going HIGH on the write operation initiates the
V

TRIP

programming sequence. Bring WP LOW to com-

plete the operation.

Note:

This operation also writes 00h to array address

01h.

Figure 1. Set V

TRIP

Level Sequence (V

= desired V

TRIP

value)

2 3

5 6

SCK

06h

2 3

5 6

7 8

9 10

20 21 22 23

16 Bits

0001h

02h

= 15-18V

00h

WREN

Write

Address

Data

X5083

Characteristics subject to change without notice.

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Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a "native"

voltage level. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

must be 4.0V, then the V

TRIP

must

be reset. When V

TRIP

is reset, the new V

TRIP

is some-

thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.

To reset the new V

TRIP

voltage, apply the desired

TRIP

threshold voltage to the Vcc pin and tie the WP

pin to the programming voltage V

. Then send a WREN

command, followed by a write of data 00h to address
03h. CS going HIGH on the write operation initiates the
V

TRIP

programming sequence. Bring WP

LOW to com-

plete the operation.

Note:

This operation also writes 00h to array address

03h.

Figure 2. Reset V

TRIP

Level Sequence (V

> 3V. WP = 1518V)

Figure 3. Sample V

TRIP

Reset Circuit

2 3

5 6

SCK

06h

2 3

5 6

7 8

9 10

20 21 22 23

16 Bits

0003h

02h

= 15-18V

00h

WREN

Write

Address

Data

3
4

X5083

TRIP

Adj.

RESET

4.7K

SCK

µC

Adjust

Run

X5083

Characteristics subject to change without notice.

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Figure 4. V

TRIP

Programming Sequence

TRIP

Programming

Apply 5V to V

Decrement V

RESET pin

goes active?

Measured V

TRIP

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set V

= V

Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New V

Applied =

Old V

Applied + Error

= V

- 50mV)

Execute

Sequence

Reset V

TRIP

New V

Applied =

Old V

Applied - Error

Error

Emax

Emax < Error < Emax

YES

Error

Emax

Emax = Maximum Desired Error

SPI Serial Memory

The memory portion of the device is a CMOS serial
EEPROM array with Xicor's block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.

The device utilizes Xicor's proprietary Direct Write

cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.

The device monitors the bus and asserts RESET out-
put if the watchdog timer is enabled and there is no bus

activity within the user selectable time out period or the
supply voltage falls below a preset minimum V

TRIP

The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW during the
entire operation.

All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.

X5083

Characteristics subject to change without notice.

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Write Enable Latch

The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 7). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows.

Status Register/Block Lock/WDT Byte

Block Lock Memory

Xicor's block lock memory provides a flexible mecha-
nism to store and lock system ID and parametric infor-
mation. There are seven distinct block lock memory
areas within the array which vary in size from one page
to as much as half of the entire array. These areas and
associated address ranges are block locked by writing
the appropriate two byte block lock instruction to the
device as described in Table 1 and Figure 9. Once a
block lock instruction has been completed, that block
lock setup is held in the nonvolatile status register until
the next block lock instruction is issued. The sections
of the memory array that are block locked can be read
but not written until block lock is removed or changed.

WD1

WD0

BL2

BL1

BL0

Table 1. Instruction Set and Block Lock Protection Byte Definition

Instruction Format

Instruction Name and Operation

0000 0110

WREN: set the write enable latch (write enable operation)

0000 0100

WRDI: reset the write enable latch (write disable operation)

0000 0001

Write status instruction--followed by:
Block lock/WDT byte: (See Figure 1)
000WD

000 --->no block lock: 00h-00h

--->none of the array

000WD

001 --->block lock Q1: 0000h-00FFh --->lower quadrant (Q1)

000WD

010 --->block lock Q2: 0100h-01FFh --->Q2

000WD

011 --->block lock Q3: 0200h-02FFh --->Q3

000WD

100 --->block lock Q4: 0300h-03FFh --->upper quadrant (Q4)

000WD

101 --->block lock H1: 0000h-01FFh --->lower half of the array (H1)

000WD

110 --->block lock P0: 0000h-000Fh

--->lower page (P0)

000WD

111 --->block lock Pn: 03F0h-03FFh --->upper page (PN)

0000 0101

READ STATUS: reads status register & provides write in progress status on SO pin

0000 0010

WRITE: write operation followed by address and data

0000 0011

READ: read operation followed by address

Watchdog Timer

The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction. A change to
the Watchdog Timer, either setting a new time out
period or turning it off or on, takes effect, following
either the next command (read or write) or cycling the
power to the device.

The recommended procedure for changing the Watch-
dog Timer settings is to do a WREN, followed by a
write status register command. Then execute a soft-
ware loop to read the status register until the MSB of
the status byte is zero. A valid alternative is to do a

WREN, followed by a write status register command.
Then wait 10ms and do a read status command.

Table 2. Watchdog Timer Definition

Status Register Bits

Watchdog Time Out

(Typical)

WD1

WD0

1.4 seconds

600 milliseconds

200 milliseconds

disabled (factory default)

X5083

Characteristics subject to change without notice.

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Read Sequence

When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the read
EEPROM array sequence (Figure 5).

To read the status register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Refer to the read status register sequence (Figure 6).

Write Sequence

Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 7). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.

To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the same page and overwrite any data that
may have been previously written.

For a write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 8).

To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits
5, 6 and 7 must be "0".

Read Status Operation

If there is not a nonvolatile write in progress, the read
status instruction returns the block lock setting from the
status register which contains the watchdog timer bits
WD1, WD0, and the block lock bits IDL2-IDL0 (Figure
6). The block lock bits define the block lock condition
(Table 1). The watchdog timer bits set the operation of
the watchdog timer (Table 2). The other bits are
reserved and will return '0' when read. See Figure 6.

During an internal nonvolatile write operaiton, the
Read Status Instruction returns a HIGH on SO in the
first bit following the RDSR instruction (the MSB). The
remaining bits in the output status byte are undefined.
Repeated Read Status Instructions return the MSB as
a `1' until the nonvolatile write cycle is complete. When
the nonvolatile write cycle is completed, the RDSR
instruction returns a `0' in the MSB position with the
remaining bits of the status register undefined. Subse-
quent RDSR instructions return the Status Register
Contents. See Figure 10.

RESET Operation

The RESET output is designed to go LOW whenever
V

has dropped below the minimum trip point and/or

the watchdog timer has reached its programmable time
out limit.

The RESET output is an open drain output and
requires a pull up resistor.

Operational Notes

The device powers-up in the following state:

The device is in the low power standby state.

A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

SO pin is high impedance.

The write enable latch is reset.

Reset signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

A WREN instruction must be issued to set the write

enable latch.

CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

When V

is below V

TRIP

, communications to the

device are inhibited.

X5083

Characteristics subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................. 65°C to +135°C
Storage temperature ....................... 65°C to +150°C
Voltage on any pin with

respect to V

......................................1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

40°C

+85°C

Voltage Option

Limits

2.7

2.7V to 5.5V

Blank

4.5V-5.5V

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

CC1

write current (active)

SCK = V

x 0.1/V

x 0.9 @ 5MHz,

SO = Open

CC2

read current (active)

0.4

SCK = V

x 0.1/V

x 0.9 @ 5MHz,

SO = Open

SB1

standby current

WDT = OFF

µA

CS = V

, V

= V

or V

= 5.5V

SB2

standby current

WDT = ON

µA

CS = V

, V

= V

or V

= 5.5V

SB3

standby current

WDT = ON

µA

CS = V

, V

= V

or V

= 3.6V

Input leakage current

0.1

µA

= V

to V

Output leakage current

0.1

µA

OUT

= V

to V

(1)

Input LOW voltage

0.5

x 0.3

(1)

Input HIGH voltage

x 0.7

+ 0.5

OL1

Output LOW voltage

0.4

> 3.3V, I

= 2.1mA

OL2

Output LOW voltage

0.4

2V < V

3.3V, I

= 1mA

OL3

Output LOW voltage

0.4

2V, I

= 0.5mA

OH1

Output HIGH voltage

0.8

> 3.3V, I

= 1.0mA

OH2

Output HIGH voltage

0.4

2V < V

3.3V, I

= 0.4mA

OH3

Output HIGH voltage

0.2

2V, I

= 0.25mA

OLRS

Reset output LOW voltage

0.4

= 1mA

X5083

Characteristics subject to change without notice.

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POWER-UP TIMING

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V.

Notes: (1) V

min. and V

max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Min.

Max.

Unit

PUR

(2)

Power-up to read operation

PUW

(2)

Power-up to write operation

Symbol

Test

Max.

Unit

Conditions

OUT

(2)

Output capacitance (SO, RESET, RESET)

OUT

= 0V

(2)

Input capacitance (SCK, SI, CS, WP)

= 0V

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

100pF

3.3K

RESET

30pF

1.64K

Output

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Data Input Timing

Symbol Parameter

2.7V5.5V

Unit

Min.

Max.

SCK

Clock frequency

3.3

MHz

CYC

Cycle time

300

LEAD

CS lead time

150

LAG

CS lag time

150

Clock HIGH time

130

Clock LOW time

130

Data setup time

Data hold time

(3)

Input rise time

µs

(3)

Input fall time

µs

CS deselect time

100

(4)

Write cycle time

X5083

Characteristics subject to change without notice.

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Data Output Timing

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Output Timing

Serial Input Timing

Symbol Parameter

2.7V5.5V

Unit

Min.

Max.

SCK

Clock frequency

3.3

MHz

DIS

Output disable time

150

Output valid from clock low

130

Output hold time

(3)

Output rise time

(3)

Output fall time

SCK

MSB Out

MSB1 Out

LSB Out

ADDR

LSB IN

CYC

DIS

LAG

SCK

MSB IN

LAG

LEAD

LSB IN

High Impedance

X5083

Characteristics subject to change without notice.

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Power-Up and Power-Down Timing

RESET Output Timing

Note:

(5) This parameter is periodically sampled and not 100% tested.
(6) PT= Package/Temperature

CS vs. RESET Timing

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset trip point voltage, X5083PT-4.5A (See note 6)
Reset trip point voltage, X5083PT
Reset trip point voltage, X5083PT-2.7A
Reset trip point voltage, X5083PT-2.7

4.5

4.25
2.85
2.55

4.63
4.38
2.93
2.63

4.75

4.5

3.00

2.7

PURST

Power-up reset time out

100

200

280

RPD

(5)

detect to reset/output

500

(5)

fall time

0.1

(5)

rise time

0.1

RVALID

Reset valid V

Symbol

Parameter

Min.

Typ.

Max.

Unit

WDO

Watchdog time out period,
WD1 = 1, WD0 = 1(default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

OFF

200
600

1.4

300
800

ms
ms

sec

CST

CS pulse width to reset the watchdog

400

RST

Reset time out

100

200

300

PURST

RPD

RESET

0 Volts

TRIP

CST

RESET

WDO

RST

WDO

RST

X5083

Characteristics subject to change without notice.

16 of 21

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TRIP

Programming Timing Diagram

TRIP

Programming Parameters

Parameter

Description

Min.

Max.

Unit

VPS

TRIP

program enable voltage setup time

µs

VPH

TRIP

program enable voltage hold time

µs

PCS

TRIP

programming CS inactive time

µs

TSU

TRIP

setup time

µs

THD

TRIP

hold (stable) time

TRIP

write cycle time

VPO

TRIP

program enable voltage off time (between successive adjustments)

µs

TRIP

program recovery period (between successive adjustments)

Programming voltage

TRAN

TRIP

programmed voltage range

2.0

5.0

TRIP

program variation after programming (0-75°C). (programmed at 25°C)

-25

+25

Note 1: V

TRIP programming parameters are periodically sampled and are not 100% tested.

Note

2: For custom V

TRIP settings, Contact Factory.

SCK

0001h (set)

TRIP

)

TSU

THD

VPH

VPS

TRIP

VPO

PCS

02h

06h

0003h (reset)

WREN

Write

Addr.

00
Data

X5083

Characteristics subject to change without notice.

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Ordering Information

Part Mark Convention

Range

TRIP

Range

Package

Operating Temperature Range

Part Number RESET

(Active LOW)

4.5-5.5V

4.5.4.75

8-Pin PDIP

070°C

X5083P-4.5A

8L SOIC

070°C

X5083S8-4.5A

-4085°C

X5083S8I-4.5A

4.5-5.5V

4.25.4.5

8-Pin PDIP

070°C

X5083P

8L SOIC

070°C

X5083S8

-4085°C

X5083S8I

8L TSSOP

070°C

X5083V8

2.7-5.5V

2.85-3.0

8L SOIC

070°C

X5083S8-2.7A

-4085°C

X5083S8I-2.7A

8L TSSOP

070°C

X5083V8-2.7A

2.7-5.5V

2.55-2.7

8L SOIC

00°C

X5083S8-2.7

-4085°C

X5083S8I-2.7

8L TSSOP

070°C

X5083V8-2.7

8-Lead TSSOP

EYWW

XXXXX

583F = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.55-2.7V

583G = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.55-2.7V

X583 = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.25-4.5V

583I = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.25-4.5V

8-Lead SOIC/PDIP

X5083X

F = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.55-2.7V

G = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.55-2.7V

Blank = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.25-4.5V

I = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.25-4.5V

583AN = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.85-3.0V

583AP = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.85-3.0V

583AL = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.5-4.75V

583AM = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.5-4.75V

AN = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.85-3.0V

AP = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.85-3.0V

AL = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.5-4.75V

AM = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.5-4.75V

YWW = year/work week device is packaged.

X5083

Characteristics subject to change without notice.

21 of 21

REV 1.1.6 6/25/02

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LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS AND TRADEMARKS

Xicor, Inc., the Xicor logo, E

POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5083V8-2.7A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5083V8-2.7A