Xicor, Inc. 1999 Patents Pending

9900-3002.10 2/12/99 T0/C0/D0

Characteristics subject to change without notice

X51638

CPU Supervisor with 16Kb SPI EEPROM

FEATURES

· Extended Power-On Reset (800ms Nominal)
· Selectable Watchdog Timer
· Low Vcc Detection and Reset Assertion

--Five Standard Reset Threshold Voltages
--Re-program Low Vcc Reset Threshold Voltage

using special programming sequence

--Reset Signal Valid to Vcc=1V

· Determine Watchdog or Low Voltage Reset with

a Volatile Flag bit

· Long Battery Life With Low Power Consumption

--<50

A Max Standby Current, Watchdog On

--<1

A Max Standby Current, Watchdog Off

--<400

A Max Active Current during Read

· 16Kbits of EEPROM
· Built-in Inadvertent Write Protection

--Power-Up/Power-Down Protection Circuitry
--Protect 0, 1/4, 1/2 or all of EEPROM Array with

Block Lock

Protection

--In Circuit Programmable ROM Mode

· 2MHz SPI Interface Modes (0,0 & 1,1)
· Minimize EEPROM Programming Time

--32 Byte Page Write Mode
--Self-Timed Write Cycle
--5ms Write Cycle Time (Typical)

· 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power

Supply Operation

· Available Packages

--14-Lead TSSOP, 8-Lead SOIC

DESCRIPTION

This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervi-
sion, and Block LockTM Protect Serial EEPROM in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.

Applying power to the device activates a power on reset
circuit which holds RESET active for a period of time.
This allows the power supply and oscillator to stabilize
before the processor can execute code. This device
allows 800ms before releasing the controller.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.

The X51638 low Vcc detection circuitry protects the
user's system from low voltage conditions, resetting the
system when Vcc falls below the minimum Vcc trip point.
RESET is asserted until Vcc returns to proper operating
level and stabilizes. Five industry standard V

TRIP

thresh-

olds are available, however, Xicor's unique circuits allow
the thresold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.

BLOCK DIAGRAM

WATCHDOG

TIMER RESET

DATA

COMMAND

DECODE &

CONTROL

LOGIC

SCK

CS/WDI

RESET &

WATCHDOG

TIMEBASE

POWER ON AND

GENERATION

TRIP

RESET

LOW VOLTAGE

STATUS

PROTECT LOGIC

4K BITS

8K BITS

EEPROM ARRAY

WATCHDOG TRANSITION

DETECTOR

VCC THRESHOLD

RESET LOGIC

X51638

PIN DESCRIPTION

PIN CONFIGURATION

PIN

(SOIC/PDIP)

PIN

TSSOP

Name

Function

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin

is at a high impedance state. Unless a nonvolatile write cycle is underway,
the device will be in the standby power mode. CS LOW enables the device,
placing it in the active power mode. Prior to the start of any operation after
power up, a HIGH to LOW transition on CS is required

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the

Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time-out period results in RESET going active.

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data

out on this pin. The falling edge of the serial clock (SCK) clocks the data out.

Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses,

and memory data on this pin. The rising edge of the serial clock (SCK) latches
the input data. Send all opcodes (Table 1), addresses and data MSB first.

SCK

Serial Clock.

The Serial Clock controls the serial bus timing for data input and

output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.

Write Protect.

The WP pin works in conjunction with a nonvolatile WPEN

bit to "lock" the setting of the Watchdog Timer control and the memory write
protect bits.

Ground

Supply Voltage

RESET

Reset Output

RESET is an active LOW open drain output which goes

active whenever Vcc falls below the minimum Vcc sense level. It will
remain active until Vcc rises above the minimum Vcc sense level for
800ms. RESET goes active if the Watchdog Timer is enabled and CS
remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge of CS will reset the Watchdog Timer. RESET goes
active on power up at 1V and remains active for 800ms after the power
supply stabilizes.

3-5,10-12

No internal connections

8-LEAD SOIC/PDIP

RESET

VCC

14-LEAD TSSOP

VSS

RESET

SCK

VCC

X51638

VSS

SCK

X51638

X51638

PRINCIPLES OF OPERATION

POWER ON RESET

Application of power to the X51638 activates a Power On
Reset Circuit. This circuit goes active at V

sense level

TRIP

) and pulls the RESET pin LOW. This signal pre-

vents the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the oscil-
lator. When Vcc exceeds the device V

TRIP

value for

800ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code.

LOW VOLTAGE MONITORING

During operation, the X51638 monitors the V

level and

asserts RESET if supply voltage falls below a preset mini-
mum V

TRIP

. The RESET signal prevents the microproces-

sor from operating in a power fail or brownout condition.
The RESET signal remains active until the voltage drops
below 1V. It also remains active until Vcc returns and
exceeds V

TRIP

for 800ms.

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time-
out period. The state of two nonvolatile control bits in the
Status Register determine the watchdog timer period. The
microprocessor can change these watchdog bits, or they
may be "locked" by tying the WP pin LOW and setting the
WPEN bit HIGH.

VCC THRESHOLD RESET PROCEDURE

The X51638 is offered with one of several standard Vcc
threshold (V

TRIP

) voltages. This value will not change

over normal operating and storage conditions. However,
in applications where the standard V

TRIP

is not exactly

right, or for higher precision in the V

TRIP

value, the

X51638 threshold may be adjusted.

Setting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a higher voltage value.

For example, if the current V

TRIP

is 4.4V and the new

TRIP

is 4.6V, this procedure directly makes the change. If

the new setting is lower than the current setting, then it is
necessary to reset the trip point before setting the new
value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold to the Vcc pin and tie the CS/WDI pin and the
WP pin HIGH. RESET and SO pins are left unconnected.
Then apply the programming voltage Vp to both SCK and
SI and pulse CS/WDI LOW then HIGH. Remove Vp and
the sequence is complete.

Figure 1. Set V

TRIP

Voltage

Resetting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a "native" voltage level.

For example, if the current V

TRIP

is 4.4V and the V

TRIP

reset, the new V

TRIP

is something less than 1.7V. This

procedure must be used to set the voltage to a lower
value.

To reset the V

TRIP

voltage, apply a voltage between 2.7

and 5.5V to the Vcc pin. Tie the CS/WDI pin, the WP pin,
AND THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage Vp to
the SI pin ONLY and pulse CS/WDI LOW then HIGH.
Remove Vp and the sequence is complete.

Figure 2. Reset V

TRIP

Voltage

SCK

Vcc

X51638

SPI SERIAL MEMORY

The memory portion of the device is a CMOS Serial
EEPROM array with Xicor's Block Lock

Protection. The

array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.

The device utilizes Xicor's proprietary Direct Write

cell,

providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.

The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families. It contains an 8-bit instruction
register that is accessed via the SI input, with data being
clocked in on the rising edge of SCK. CS must be LOW
during the entire operation.

All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 3). This latch is automati-
cally reset upon a power-up condition and after the
completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:

The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a "1", a nonvolatile write
operation is in progress. When set to a "0", no write is in
progress.

WPEN

FLB

WD1 WD0

BL1

BL0

WEL

WIP

Table 1. Instruction Set

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Table 2. Block Protect Matrix

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

SFLB

0000 0000

Set Flag Bit

WRDI/RFLB

0000 0100

Reset the Write Enable Latch/Reset Flag Bit

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

READ

0000 0011

Read Data from Memory Array Beginning at Selected Address

WRITE

0000 0010

Write Data to Memory Array Beginning at Selected Address

WREN CMD

STATUS

REGISTER

DEVICE

PIN

BLOCK

STATUS

REGISTER

WEL

WPEN

WP#

PROTECTED

BLOCK

UNPROTECTED

BLOCK

WPEN, BL0, BL1

WD0, WD1

Protected

Writable

Protected

Writable

Protected

Writable

X51638

The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL=1, the latch is set
HIGH and when WEL=0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.

The Block Lock bits, BL0 and BL1, set the level of Block
Lock

Protection. These nonvolatile bits are pro-

grammed using the WRSR instruction and allow the user
to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is Block Lock
Protected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable Block Lock
Protection of that portion of memory.

The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.

The FLAG bit shows the status of a volatile latch that can
be set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon
power up. This flag can be used by the system to deter-
mine whether a reset occurs as a result of a watchdog
time-out or power failure.

The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all Status Register Write Operations.

In Circuit Programmable ROM Mode

This mechanism protects the Block Lock and Watchdog
bits from inadvertant corruption.

In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is "1". This mode
disables nonvolatile writes to the device's Status Register.

Status

Register Bits

Array Addresses Protected

BL1

BL0

X516x

None

$0600$07FF

$0400$07FF

$0000$07FF

Status Register Bits

Watchdog Time-out

(Typical)

WD1

WD0

1.4 Seconds

600 Milliseconds

400 Milliseconds

Disabled

Figure 5. Read EEPROM Array Sequence

20 21 22 23 24 25

26 27 28 29 30

DATA OUT

SCK

MSB

HIGH IMPEDANCE

INSTRUCTION

16 BIT ADDRESS

15 14 13

X51638

Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.

When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally.
Setting the WPEN bit in the Status Register to "0" blocks
the WP pin function, allowing writes to the Status Regis-
ter when WP is HIGH or LOW. Setting the WPEN bit to
"1" while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin prior
to subsequent Status Register changes. This allows
manufacturing to install the device in a system with WP
pin grounded and still be able to program the Status Reg-
ister. Manufacturing can then load Configuration data,
manufacturing time and other parameters into the
EEPROM, then set the portion of memory to be pro-
tected by setting the Block Lock bits, and finally set the
"OTP mode" by setting the WPEN bit. Data changes now
require a hardware change.

Read Sequence

When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
address $0000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS high. Refer to the Read EEPROM Array Sequence
(Figure 1).

To read the Status Register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS

must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.

To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused
address bits are specified to be "0's". The WRITE opera-
tion minimally takes 32 clocks. CS must go low and
remain low for the duration of the operation. If the
address counter reaches the end of a page and the clock
continues, the counter will roll back to the first address of
the page and overwrite any data that may have been pre-
viously written.

For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).

To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be "0" .

While the write is in progress following a Status Register
or EEPROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.

OPERATIONAL NOTES

The device powers-up in the following state:

· The device is in the low power standby state.
· A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

· SO pin is high impedance.
· The Write Enable Latch is reset.
· The Flag Bit is reset.
· Reset Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent inad-
vertent writes:

· A WREN instruction must be issued to set the Write

Enable Latch.

· CS must come HIGH at the proper clock count in order

to start a nonvolatile write cycle.

X51638

Figure 8. Write Sequence

Figure 9. Status Register Write Sequence

SCK

INSTRUCTION

16 BIT ADDRESS

DATA BYTE 1

DATA BYTE 2

DAT A BYTE 3

DATA BYTE N

SCK

HIGH IMPEDANCE

INSTRUCTION

DATA BYTE

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

Symbol Table

X51638

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Units

Test Conditions

Min.

Typ.

Max.

CC1

Write Current (Active)

SCK = V

x 0.1/V

x 0.9 @ 2MHz,

SO = Open

CC2

Read Current (Active)

0.4

SCK = V

x 0.1/V

x 0.9 @ 2MHz,

SO = Open

SB1

Standby Current

WDT=OFF

µA

CS = V

, V

= V

or V

= 5.5V

SB2

Standby Current

WDT=ON

µA

CS = V

, V

= V

or V

= 5.5V

SB3

Standby Current

WDT=ON

µA

CS = V

, V

= V

or V

=3.6V

Input Leakage Current

0.1

µA

= V

to V

Output Leakage Current

0.1

µA

OUT

= V

to V

(1)

Input LOW Voltage

0.5

x0.3

(1)

Input HIGH Voltage

x0.7

+0.5

OL1

Output LOW Voltage

0.4

> 3.3V, I

= 2.1mA

OL2

Output LOW Voltage

0.4

2V < V

3.3V, I

= 1mA

OL3

Output LOW Voltage

0.4

2V, I

= 0.5mA

OH1

Output HIGH Voltage

0.8

> 3.3V, I

= 1.0mA

OH2

Output HIGH Voltage

0.4

2V < V

3.3V, I

= 0.4mA

OH3

Output HIGH Voltage

0.2

2V, I

= 0.25mA

OLS

Reset Output LOW Voltage

0.4

= 1mA

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias ........................65°C to +135°C
Storage Temperature .............................65°C to +150°C
Voltage on any Pin with Respect to V

....... 1.0V to +7V

D.C. Output Current ....................................................5mA
Lead Temperature (Soldering, 10 seconds)............ 300°C

RECOMMENDED OPERATING CONDITIONS

*COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Temp

Min.

Max.

Commercial

0°C

70°C

Industrial

40°C

+85°C

Voltage Option

Supply Voltage

1.8

1.8V-3.6V

2.7 or -2.7A

2.7V to 5.5V

Blank or -4.5A

4.5V-5.5V

X51638

Power-Up and Power-Down Timing

RESET Output Timing

Notes:

(5) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Min.

Typ.

Max.

Units

TRIP

Reset Trip Point Voltage, X51638-4.5A
Reset Trip Point Voltage, X51638
Reset Trip Point Voltage, X51638-2.7A
Reset Trip Point Voltage, X51638-2.7
Reset Trip Point Voltage, X51638-1.8

4.5

4.25
2.85
2.55

1.7

4.62
4.38
2.92
2.62
1.75

4.75

4.5
3.0
2.7
1.8

(5)

TRIP

Hysteresis

(HIGH to LOW vs. LOW to HIGH V

TRIP

voltage)

PURST

Power-up Reset Timeout

500

800

1400

RPD

(5)

Detect to Reset/Output

500

(5)

Fall Time

100

(5)

Rise Time

100

RVALID

Reset Valid V

VCC

PURST

RPD

RESET

0 Volts

TRIP

X51638

CS/WDI vs. RESET Timing

RESET Output Timing (WD1 = 1, WD0 = 0)

RESET Output Timing (WD1 = 0, WD0 = 1)

RESET Output Timing (WD1 = 0, WD0 = 0)

Symbol

Parameter

Min.

Typ.

Max.

Units

WDO

Watchdog Timeout Period

300

400

550

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Timeout

200

400

600

Symbol

Parameter

Min.

Typ.

Max.

Units

WDO

Watchdog Timeout Period

450

600

800

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Timeout

100

200

300

Symbol

Parameter

Min.

Typ.

Max.

Units

WDO

Watchdog Timeout Period

1.4

sec

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Timeout

100

200

300

CS/WDI

CST

RESET

WDO

RST

WDO

RST

X51638

Table 3. V

TRIP

Programming Specifications: Vcc=1.7-5.5V; Temperature = 0

C to 70

Parameter

Description

Min

Max

Units

VPS

SCK V

TRIP

Program Voltage Setup time

VPH

SCK V

TRIP

Program Voltage Hold time

TRIP

Program Pulse Width

TSU

TRIP

Level Setup time

THD

TRIP

Level Hold (stable) time

TRIP

Write Cycle Time

TRIP

Program Cycle Recovery Period

(Between successive programming cycles)

VPO

SCK V

TRIP

Program Voltage Off time before next cycle

Programming Voltage

TRIP

Programed Voltage

1.7

5.0

Vta

TRIP

Programed Voltage accuracy (Vcc applied - V

TRIP

)

-0.3

+0.3

Vtr

TRIP

Programed Voltage repeatability

(Successive program operations.)

-5

TRIP

Programming parameters are periodically sampled and are not 100% Tested.

X51638

Ordering Information

Part Mark Information

Vcc Range

TRIP

Range

Package

Operating

Temperature Range

PART NUMBER

RESET (Active LOW)

4.5-5.5V

4.5-4.75

8 pin PDIP

C - 70

X51638P-4.5A

8L SOIC

C - 70

X51638S8-4.5A

-40

C - 85

X51638S8I-4.5A

4.5-5.5V

4.25-4.5

8 pin PDIP

C - 70

X51638P

8L SOIC

C - 70

X51638S8

-40

C - 85

X51638S8I

14L TSSOP

0°c - 70°C

X51638V14

2.7-5.5V

2.85-3.0

8L SOIC

C - 70

X51638S8-2.7A

-40

C - 85

X51638S8I-2.7A

14L TSSOP

C - 70

X51638V14-2.7A

2.7-5.5V

2.55-2.7

8L SOIC

C - 70

X51638S8-2.7

14L TSSOP

C - 70

X51638V14-2.7

1.8-3.6V

1.7-1.8V

8L SOIC

C - 70

X51638S8-1.8

14L TSSOP

C - 70

X51638V14-1.8

P = 8-Pin DIP
Blank = 8-Lead SOIC
V = 14 Lead TSSOP

Blank = 5V ±10%, 0°C to +70°C, V

TRIP

=4.25-4.5

AL=5V±10%, 0°C to +70°C, V

TRIP

= 4.5-4.75

I = 5V ±10%, 40°C to +85°C, V

TRIP

=4.25-4.5

AM = 5V ±10%, 40°C to +85°C, V

TRIP

=4.5-4.75

F = 2.7V to 5.5V, 0°C to +70°C, V

TRIP

=2.55-2.7

AN = 2.7V to 5.5V, 0°C to +70°C, V

TRIP

=2.85-3.0

G = 2.7V to 5.5V, 40°C to +85°C, V

TRIP

=2.55-2.7

AP = 2.7V to 5.5V, 40°C to +85°C, V

TRIP

=2.85-3.0

AG = 1.8V to 3.6V, 0°C to +70°C, V

TRIP

=1.7-1.8

AH = 1.8V to 3.6V, 40°C to +85°C, V

TRIP

=1.7-1.8

X51638

X51638

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain

life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or system, or to affect its safety or effectiveness.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X51638S8-2.7A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X51638S8-2.7A