REV 1.1 3/5/01
Characteristics subject to change without notice.
1 of 21
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Replaces X25268/X25169
X5168/X5169
CPU Supervisor with 16Kbit SPI EEPROM
FEATURES
Low V
CC
detection and reset assertion
--Five standard reset threshold voltages
--Re-program low V
CC
reset threshold voltage
using special programming sequence
--Reset signal valid to V
CC
= 1V
Long battery life with low power consumption
--<50A max standby current, watchdog on
--<1A max standby current, watchdog off
--<400A max active current during read
16Kbits of EEPROM
Built-in inadvertent write protection
--Power-up/power-down protection circuitry
--Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock
TM
protection
--In circuit programmable ROM mode
2MHz SPI interface modes (0,0 & 1,1)
Minimize EEPROM programming time
--32-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)
2.7V to 5.5V and 4.5V to 5.5V power supply
operation
Available packages
--14-lead TSSOP, 8-lead SOIC, 8 pin DIP
DESCRIPTION
These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device's low V
CC
detection circuitry protects the
user's system from low voltage conditions by holding
RESET/RESET active when V
CC
falls below a mini-
mum V
CC
trip point. RESET/RESET remains asserted
until V
CC
returns to proper operating level and stabi-
lizes. Five industry standard V
TRIP
thresholds are
available, however, Xicor's unique circuits allow the
threshold to be reprogrammed to meet custom require-
ments or to fine-tune the threshold in applications
requiring higher precision.
BLOCK DIAGRAM
Data
Register
Command
Decode &
Control
Logic
SI
SO
SCK
CS
V
CC
Reset
Timebase
Power On and
Generation
V
TRIP
+
-
RESET/RESET
Reset
Low Voltage
Status
Register
Protect Logic
4Kbits
4Kbits
8Kbits
EEPROM Array
WP
X5168 = RESET
X5169 = RESET
X5168/X5169
Characteristics subject to change without notice.
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PIN CONFIGURATION
PIN DESCRIPTION
Pin
(SOIC/PDIP)
Pin
TSSOP
Name
Function
1
1
CS
Chip Select Input.
CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is un-
derway, the device will be in the standby power mode. CS LOW enables
the device, placing it in the active power mode. Prior to the start of any
operation after power up, a HIGH to LOW transition on CS is required.
2
2
SO
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts
data out on this pin. The falling edge of the serial clock (SCK) clocks the
data out.
5
8
SI
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses,
and memory data on this pin. The rising edge of the serial clock (SCK) latch-
es the input data. Send all opcodes (Table 1), addresses and data MSB first.
6
9
SCK
Serial Clock.
The serial clock controls the serial bus timing for data input
and output. The rising edge of SCK latches in the opcode, address, or data
bits present on the SI pin. The falling edge of SCK changes the data output
on the SO pin.
3
6
WP
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN
bit to "lock" the setting of the watchdog timer control and the memory write
protect bits.
4
7
V
SS
Ground
8
14
V
CC
Supply Voltage
7
13
RESET/
RESET
Reset Output
. RESET/RESET is an active LOW/HIGH, open drain out-
put which goes active whenever V
CC
falls below the minimum V
CC
sense
level. It will remain active until V
CC
rises above the minimum V
CC
sense
level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable
watchdog time out period. A falling edge of CS will reset the watchdog
timer. RESET/RESET goes active on power up at about 1V and remains
active for 200ms after the power supply stabilizes.
3-5,10-12
NC
No internal connections
8-Lead SOIC/PDIP
CS
WP
SO
1
2
3
4
RESET/RESET
8
7
6
5
V
CC
14-Lead TSSOP
SO
WP
V
SS
1
2
3
4
5
6
7
RESET/RESET
SCK
SI
14
13
12
11
10
9
8
NC
V
CC
NC
X5168/69
V
SS
SCK
SI
CS
NC
NC
NC
NC
X5168/69
X5168/X5169
Characteristics subject to change without notice.
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PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5168/X5169 activates a
power on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When V
CC
exceeds the device V
TRIP
value for 200ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing code.
Low Voltage Monitoring
During operation, the X5168/X5169 monitors the V
CC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
V
CC
Threshold Reset Procedure
The X5168/X5169 has a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or
for higher precision in the V
TRIP
value, the X5168/
X5169 threshold may be adjusted.
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage
value. For example, if the current V
TRIP
is 4.4V and the
new V
TRIP
is 4.6V, this procedure directly makes the
change. If the new setting is lower than the current set-
ting, then it is necessary to reset the trip point before
setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the V
CC
pin and tie the CS pin and the WP
pin HIGH. RESET/RESET and SO pins are left uncon-
nected. Then apply the programming voltage V
P
to
both SCK and SI and pulse CS LOW then HIGH.
Remove V
P
and the sequence is complete.
Figure 1. Set V
TRIP
Voltage
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a "native" voltage
level. For example, if the current V
TRIP
is 4.4V and the
V
TRIP
is reset, the new V
TRIP
is something less than
1.7V. This procedure must be used to set the voltage to
a lower value.
To reset the V
TRIP
voltage, apply a voltage between
2.7 and 5.5V to the Vcc pin. Tie the CS pin, the WP pin,
and the SCK pin HIGH. RESET/RESET and SO pins
are left unconnected. Then apply the programming
voltage V
P
to the SI pin ONLY and pulse CS LOW then
HIGH. Remove V
P
and the sequence is complete.
Figure 2. Reset V
TRIP
Voltage
SCK
SI
V
P
V
P
CS
SCK
SI
V
CC
V
P
CS
X5168/X5169
Characteristics subject to change without notice.
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Figure 3. V
TRIP
Programming Sequence Flow Chart
V
TRIP
Programming
Apply 5V to V
CC
Decrement V
CC
RESET pin
goes active?
Measured V
TRIP
-
Desired V
TRIP
DONE
Execute
Sequence
Reset V
TRIP
Set V
CC
= V
CC
Applied =
Desired V
TRIP
Execute
Sequence
Set V
TRIP
New V
CC
Applied =
Old V
CC
Applied + Error
(V
CC
= V
CC
- 10mV)
Execute
Sequence
Reset V
TRIP
New V
CC
Applied =
Old V
CC
Applied - Error
Error
Emax
Error = 0
YES
NO
Error > Emax
Emax = Maximum Desired Error
X5168/X5169
Characteristics subject to change without notice.
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Figure 4. Sample V
TRIP
Reset Circuit
X5168/69
1
2
3
4
8
7
6
5
V
TRIP
Adj.
Program
NC
NC
V
P
Reset V
TRIP
Test
V
TRIP
Set V
TRIP
NC
RESET
4.7K
4.7K
10K
10K
+
SPI SERIAL MEMORY
The memory portion of the device is a CMOS serial
EEPROM array with Xicor's block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
Write Enable Latch
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a "1", a non-
volatile write operation is in progress. When set to a
"0", no write is in progress.
7
6
5
4
3
2
1
0
WPEN
FLB
0
0
BL1
BL0
WEL
WIP
Table 1. Instruction Set
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the write enable latch (enable write operations)
SFLB
0000 0000
Set flag bit
WRDI/RFLB
0000 0100
Reset the write enable latch/reset flag bit
RSDR
0000 0101
Read status register
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN & flag bits)
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
X5168/X5169
Characteristics subject to change without notice.
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Table 2. Block Protect Matrix
WREN CMD
Status Register
Device Pin
Block
Block
Status Register
WEL
WPEN
WP#
Protected Block
Unprotected Block
WPEN, BL0, BL1
WD0, WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to pro-
tect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock pro-
tected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable block lock
protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The flag bit is automatically
reset upon power up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an in-circuit programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog
bits from inadvertent corruption.
In the locked state (
programmable ROM mode) the WP
pin is LOW and the nonvolatile bit WPEN is "1". This
mode disables nonvolatile writes to the device's status
register.
Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the status register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile
writes to the status register operate normally. Setting
the WPEN bit in the status register to "0" blocks the WP
pin function, allowing writes to the status register when
WP is HIGH or LOW. Setting the WPEN bit to "1" while
the WP pin is LOW activates the programmable ROM
mode, thus requiring a change in the WP pin prior to
subsequent status register changes. This allows manu-
facturing to install the device in a system with WP pin
grounded and still be able to program the status regis-
ter. Manufacturing can then load configuration data,
manufacturing time and other parameters into the
EEPROM, then set the portion of memory to be pro-
tected by setting the block lock bits, and finally set the
"OTP mode" by setting the WPEN bit. Data changes
now require a hardware change.
Status
Register Bits
Array Addresses Protected
BL1
BL0
X5168/X5169
0
0
None
0
1
$0600$07FF
1
0
$0400$07FF
1
1
$0000$07FF
X5168/X5169
Characteristics subject to change without notice.
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Figure 5. Read EEPROM Array Sequence
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
16 Bit Address
15 14 13
3
2
1
0
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the read
EEPROM array sequence (Figure 1).
To read the status register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Refer to the read status register sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be "0".
While the write is in progress following a status register
or EEPROM sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be high.
X5168/X5169
Characteristics subject to change without notice.
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OPERATIONAL NOTES
The device powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The write enable latch is reset.
The flag bit is reset.
Reset signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
A WREN instruction must be issued to set the write
enable latch.
CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
Figure 6. Read Status Register Sequence
Figure 7. Write Enable Latch Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
0
1
2
3
4
5
6
7
CS
SI
SCK
High Impedance
SO
X5168/X5169
Characteristics subject to change without notice.
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Figure 8. Write Sequence
Figure 9. Status Register Write Sequence
SYMBOL TABLE
32 33 34 35 36 37 38 39
SCK
SI
CS
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
Instruction
16 Bit Address
Data Byte 1
7
6
5
4
3
2
1
0
CS
40 41 42 43 44 45 46 47
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte N
15 14 13
3
2
1
0
20 21 22 23 24 25 26 27 28 29 30 31
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Instruction
Data Byte
7
6
5
4
3
2
1
0
10
11 12 13 14 15
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X5168/X5169
Characteristics subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ...................65C to +135C
Storage temperature ........................65C to +150C
Voltage on any pin with respect to V
SS
.... 1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0C
70C
Industrial
40C
+85C
Voltage Option
Supply Voltage
2.7 or -2.7A
2.7V to 5.5V
Blank or -4.5A
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
CAPACITANCE T
A
= +25C, f = 1MHz, V
CC
= 5V.
Notes: (1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Typ.
Max.
I
CC1
V
CC
write current (active)
5
mA
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 2MHz,
SO = Open
I
CC2
V
CC
read current (active)
0.4
mA
SCK = V
CC
x 0.1/V
CC
x 0.9 @ 2MHz,
SO = Open
I
SB
V
CC
standby current
WDT = OFF
1
A
CS = V
CC
, V
IN
= V
SS
or V
CC
,
V
CC
= 5.5V
I
LI
Input leakage current
0.1
10
A
V
IN
= V
SS
to V
CC
I
LO
Output leakage current
0.1
10
A
V
OUT
= V
SS
to V
CC
V
IL
(1)
Input LOW voltage
0.5
V
CC
x 0.3
V
V
IH
(1)
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output LOW voltage
0.4
V
V
CC
> 3.3V, I
OL
= 2.1mA
V
OL2
Output LOW voltage
0.4
V
2V < V
CC
3.3V, I
OL
= 1mA
V
OL3
Output LOW voltage
0.4
V
V
CC
2V, I
OL
= 0.5mA
V
OH1
Output HIGH voltage
V
CC
0.8
V
V
CC
> 3.3V, I
OH
= 1.0mA
V
OH2
Output HIGH voltage
V
CC
0.4
V
2V < V
CC
3.3V, I
OH
= 0.4mA
V
OH3
Output HIGH voltage
V
CC
0.2
V
V
CC
2V, I
OH
= 0.25mA
V
OLS
Reset output LOW voltage
0.4
V
I
OL
= 1mA
Symbol
Test
Max.
Unit
Conditions
C
OUT
(2)
Output capacitance (SO, RESET/RESET)
8
pF
V
OUT
= 0V
C
IN
(2)
Input capacitance (SCK, SI, CS, WP)
6
pF
V
IN
= 0V
X5168/X5169
Characteristics subject to change without notice.
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EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
CC
A.C. TEST CONDITIONS
5V
Output
100pF
5V
4.6K
RESET/RESET
30pF
2.06K
3.03K
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Serial Input Timing
Symbol
Parameter
2.75.5V
Unit
Min.
Max.
f
SCK
Clock frequency
0
2
MHz
t
CYC
Cycle time
500
ns
t
LEAD
CS lead time
250
ns
t
LAG
CS lag time
250
ns
t
WH
Clock HIGH time
200
ns
t
WL
Clock LOW time
200
ns
t
SU
Data setup time
50
ns
t
H
Data hold time
50
ns
t
RI
(3)
Input rise time
100
ns
t
FI
(3)
Input fall time
100
ns
t
CS
CS deselect time
500
ns
t
WC
(4)
Write cycle time
10
ms
X5168/X5169
Characteristics subject to change without notice.
12 of 21
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Serial Input Timing
Serial Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
Symbol
Parameter
2.75.5V
Unit
Min.
Max.
f
SCK
Clock frequency
0
2
MHz
t
DIS
Output disable time
250
ns
t
V
Output valid from clock low
200
ns
t
HO
Output hold time
0
ns
t
RO
(3)
Output rise time
100
ns
t
FO
(3)
Output fall time
100
ns
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
High Impedance
SCK
CS
SO
SI
MSB Out
MSB1 Out
LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
X5168/X5169
Characteristics subject to change without notice.
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Power-Up and Power-Down Timing
RESET Output Timing
Note:
(5) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
TRIP
Reset trip point voltage, X5168-4.5A, X5168-4.5A
Reset trip point voltage, X5168, X5169
Reset trip point voltage, X5168-2.7A, X5169-2.7A
Reset trip point voltage, X5168-2.7, X5169-2.7
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.0
2.7
V
V
TH
V
TRIP
hysteresis (HIGH to LOW vs. LOW to HIGH V
TRIP
voltage)
20
mV
t
PURST
Power-up reset time out
100
200
280
ms
t
RPD
(5)
V
CC
detect to reset/output
500
ns
t
F
(5)
V
CC
fall time
100
s
t
R
(5)
V
CC
rise time
100
s
V
RVALID
Reset valid V
CC
1
V
V
CC
t
PURST
t
PURST
t
R
t
F
t
RPD
RESET (X5168)
0 Volts
V
TRIP
V
TRIP
RESET (X5169)
X5168/X5169
Characteristics subject to change without notice.
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V
TRIP
Set Conditions
V
TRIP
Reset Conditions
SCK
SI
V
P
V
P
CS
t
VPS
t
VPH
t
P
t
VPS
t
VPH
t
RP
t
VPO
t
VPO
t
TSU
t
THD
V
TRIP
V
CC
SCK
SI
V
CC
V
P
CS
t
VPS
t
VPH
t
P
t
VPS
t
VP1
t
RP
t
VPO
t
VPO
V
CC
*
*V
CC
> Programmed V
TRIP
X5168/X5169
Characteristics subject to change without notice.
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V
TRIP
Programming Specifications V
CC
= 1.7-5.5V; Temperature = 0C to 70C
Parameter
Description
Min.
Max.
Unit
t
VPS
SCK V
TRIP
program voltage setup time
1
s
t
VPH
SCK V
TRIP
program voltage hold time
1
s
t
P
V
TRIP
program pulse width
1
s
t
TSU
V
TRIP
level setup time
10
s
t
THD
V
TRIP
level hold (stable) time
10
ms
t
WC
V
TRIP
write cycle time
10
ms
t
RP
V
TRIP
program cycle recovery period (between successive programming cycles)
10
ms
t
VPO
SCK V
TRIP
program voltage off time before next cycle
0
ms
V
P
Programming voltage
15
18
V
V
TRAN
V
TRIP
programed voltage range
1.7
5.0
V
V
ta1
Initial V
TRIP
program voltage accuracy (V
CC
appliedV
TRIP
) (programmed at
25C)
-0.1
+0.4
V
V
ta2
Subsequent V
TRIP
program voltage accuracy [(V
CC
appliedV
ta1
)--V
TRIP
)
(programmed at 25C)
-25
+25
mV
V
tr
V
TRIP
program voltage repeatability (successive program operations)
(programmed at 25C)
-25
+25
mV
V
tv
V
TRIP
Program variation after programming (075C). (programmed at 25C)
-25
+25
mV
V
TRIP
programming parameters are periodically sampled and are not 100% tested.
X5168/X5169
Characteristics subject to change without notice.
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TYPICAL PERFORMANCE
18
16
14
12
10
8
6
4
2
0
Watchdog Timer On (V
CC
= 5V)
Watchdog Timer On (V
CC
= 5V)
Watchdog Timer Off (V
CC
= 3V, 5V)
40C
25C
90C
Temp (C)
Isb (A)
V
CC
Supply Current vs. Temperature (I
SB
)
V
TRIP
vs. Temperature (programmed at 25C)
t
PURST
vs. Temperature
5.025
5.000
4.975
3.525
3.500
3.475
2.525
2.500
2.475
0
25
85
Voltage
Temperature
V
TRIP
= 5V
V
TRIP
= 3.5V
V
TRIP
= 2.5V
200
195
190
185
180
175
170
165
160
40
25
90
Degrees C
205
Time (ms)
X5168/X5169
Characteristics subject to change without notice.
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PACKAGING INFORMATION
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.020 (0.51)
0.016 (0.41)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.430 (10.92)
0.360 (9.14)
0.300
(7.62) Ref.
Pin 1 Index
0.145 (3.68)
0.128 (3.25)
0.025 (0.64)
0.015 (0.38)
Pin 1
Seating
0.065 (1.65)
0.045 (1.14)
0.260 (6.60)
0.240 (6.10)
0.060 (1.52)
0.020 (0.51)
Typ. 0.010 (0.25)
0
15
8-Lead Plastic Dual In-Line Package Type P
Half Shoulder Width On
All End Pins Optional
.073 (1.84)
Max.
0.325 (8.25)
0.300 (7.62)
Plane
X5168/X5169
Characteristics subject to change without notice.
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PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050" Typical
0.050"
Typical
0.030"
Typical
8 Places
FOOTPRINT
X5168/X5169
Characteristics subject to change without notice.
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X5168/X5169
Characteristics subject to change without notice.
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Ordering Information
Part Mark Information
V
CC
Range
V
TRIP
Range
Package
Operating
Temperature Range
Part Number RESET
(Active LOW)
Part Number RESET
(Active HIGH)
4.5-5.5V
4.5.4.75
8 pin PDIP
070C
X5168P-4.5A
X5169P-4.5A
8L SOIC
070C
X5168S8-4.5A
X5169S8-4.5A
-4085C
X5168S8I-4.5A
X5169S8I-4.5A
4.5-5.5V
4.25.4.5
8 pin PDIP
070C
X5168P
X5169P
8L SOIC
070C
X5168S8
X5169S8
-4085C
X5168S8I
X5169S8I
14L TSSOP
070C
X5168V14
X5169V14
2.7-5.5V
2.85-3.0
8L SOIC
070C
X5168S8-2.7A
X5169S8-2.7A
-4085C
X5168S8I-2.7A
X5169S8I-2.7A
14L TSSOP
070C
X5168V14-2.7A
X5169V14-2.7A
2.7-5.5V
2.55-2.7
8L SOIC
070C
X5168S8-2.7
X5169S8-2.7
14L TSSOP
070C
X5168V14-2.7
X5169V14-2.7
Blank = 8-Lead SOIC
V = 14 Lead TSSOP
Blank = 5V 10%, 0C to +70C, V
TRIP
= 4.25-4.5
A = 5V10%, 0C to +70C, V
TRIP
= 4.5-4.75
I = 5V 10%, 40C to +85C, V
TRIP
= 4.25-4.5
IA = 5V 10%, 40C to +85C, V
TRIP
= 4.5-4.75
F = 2.7V to 5.5V, 0C to +70C, V
TRIP
= 2.55-2.7
FA = 2.7V to 5.5V, 0C to +70C, V
TRIP
= 2.85-3.0
G = 2.7V to 5.5V, 40C to +85C, V
TRIP
= 2.55-2.7
GA = 2.7V to 5.5V, 40C to +85C, V
TRIP
= 2.85-3.0
W
X5168/69
X
X5168/X5169
Characteristics subject to change without notice.
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Xicor, Inc. 2001 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
Xicor, Inc., the Xicor logo, E
2
POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E
2
KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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