REV 1.8 9/30/02

Characteristics subject to change without notice.

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Preliminary Information

X5563

CPU Supervisor with 256Kbit SPI EEPROM

FEATURES

· Low V

detection and reset assertion

--Four standard reset threshold voltages
--Re-program low V

reset threshold voltage

using special programming sequence

--Reset signal valid to V

= 1V

· Selectable POR time (150ms or 800ms)
· Selectable watchdog time

--(0.15s, 0.4s, 0.8s, off)

· Debounced Manual Reset Input
· Low power consumption

--<90µA max standby current, watchdog on
--<50µA max standby current, watchdog off
--<1.5mA max active current during read

· 256Kbits of EEPROM
· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Protect 0, 1/4, 1/2 or all of EEPROM array with

programmable Block Lock

protection

--In circuit programmable ROM mode

· 10MHz SPI interface modes (0,0 & 1,1)

· Minimize EEPROM programming time

--64 byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· 2.7V to 5.5V power supply operation
· Available packages

--8-lead SOIC

DESCRIPTION

These devices combines power-on reset control,
watchdog timer, supply voltage supervision, manual
reset, block lock protect and serial EEPROM in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.

Applying power to the device activates the power on
reset circuit which holds RESET active for a selected
period of time. This allows the power supply and oscil-
lator to stabilize before the processor can execute
code.

BLOCK DIAGRAM

Watchdog

Timer Reset

Data

Command

Decode, Test &

Control

Logic

SCK

Reset &

Watchdog

Timebase

Power on,

Generation

Monitor

Reset

Low Voltage

Status

Protect Logic

EEPROM Array

Watchdog Transition

Detector

512 X 512

X-Decoder

TRIP

Logic

RESET/MR

X5563 Preliminary Information

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The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the RESET signal. The
user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting
the system when V

falls below the minimum V

trip

point (V

TRIP

). RESET is asserted until V

returns to

proper operating level and stabilizes. Xicor's unique cir-
cuits allow the threshold for either voltage monitor to
be reprogrammed to meet special needs or to fine-tune
the threshold for applications requiring higher preci-
sion.

Ordering Information

PIN CONFIGURATION

Part Number

Vtrip1

Temperature Range

X5563S8-4.5A

4.63

0°C70°C

X5563S8I-4.5A

-40°C85°C

X5563S8

4.38

0°C70°C

X5563S8I

-40°C85°C

X5563S8-2.7A

2.93

0°C70°C

X5563S8I-2.7A

-40°C85°C

X5563S8-2.7

2.63

0°C70°C

X5563S8I-2.7

-40°C85°C

8-Pin SOIC

CS/WDI

RESET/MR

SCK

X5563 Preliminary Information

Characteristics subject to change without notice.

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PIN DEFINITIONS

Pin

Name

Function

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power up, a HIGH to LOW transition on CS is required.

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The

absence of a HIGH to LOW transition within the watchdog time out period results in RESET going
active.

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

Write Protect.

The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting

of the Watchdog Timer control and the memory write protect bits.

Ground

Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on

this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.

SCK

Serial Clock.

The Serial Clock controls the serial bus timing for data input and output. The rising

edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.

RESET/MR

Output/Manual Reset Input

. This is an Input/Output pin.

RESET Output

This is an active LOW, open drain output which goes active whenever V

falls

below the minimum V

sense level. When RESET is active communication to the device is inter-

rupted. RESET remains active until V

rises above the minimum V

sense level for 150ms.

RESET also goes active on power up and remains active for 150ms after the power supply
stabilizes.

MR Input

This is an active LOW debounced input. When MR is active, the RESET pin is asserted.

When MR is released, RESET remains asserted for t

PURST

, and is then released.

Supply Voltage

X5563 Preliminary Information

Characteristics subject to change without notice.

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PRINCIPLES OF OPERATION

Power on Reset

Application of power to the X5563 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscilla-
tor. When V

exceeds the device V

TRIP

value for

150ms (nominal) the circuit releases RESET, allowing
the processor to begin executing code.

Low V

Voltage Monitoring

During operation, the X5563 monitors the V

level

and asserts RESET if supply voltage falls below a pre-
set minimum V

TRIP

. During this time the communica-

tion to the device is interrupted. The RESET signal
also prevents the microprocessor from operating in a
power fail or brownout condition. The RESET signal
remains active until the voltage drops below 1V. The
signal remains active until V

returns and exceeds

TRIP

for t

PURST

Manual Reset

By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The MR/RESET pin is asserted when the
push-button is closed and remain asserted for t

PURST

after the push-button is released. This pin is
debounced so a push-button connected directly to the
device will have both clean falling and rising edges on
MR.

Watchdog Timer

The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS pin. The microproces-
sor must toggle the CS pin HIGH to LOW periodically
prior to the expiration of the watchdog time out period
to prevent a RESET signal. The state of two nonvolatile
control bits in the Status Register determines the
watchdog timer period. The microprocessor can
change these watchdog bits by writing to the status
register.

Threshold Reset Procedure

The X5563 is shipped with standard V

threshold

TRIP

) voltages. These values will not change over

normal operating and storage conditions. However, in
applications where the standard thresholds are not
exactly right, or if higher precision is needed in the

threshold value, the X5563 trip points may be adjusted.
The procedure is described below, and uses the appli-
cation of a high voltage control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher or

lower voltage value. It is necessary to reset the trip
point before setting the new value to a lower level.

To set the new voltage, apply the desired V

TRIP

thresh-

old voltage to the V

pin, then tie the WP pin to the

programming voltage V

. Then, send the WREN com-

mand and write to address 01h to program V

TRIP

, (fol-

lowed by data byte 00h). The CS going high after a
valid write operating initiates the programming
sequence. Bring WP LOW to complete the operation.

Note:

This operation will not alter the contents of the

EEPROM.

ASE

If the V

TRIPX

(actual) is lower than the V

TRIPX

(desired), then add the difference between V

TRIPX

(desired) and V

TRIPX

(actual) to the original V

TRIPX

(desired). This is your new V

TRIPX

voltage that should

be applied to VXMON and the whole sequence
repeated again (see Fig 6).

ASE

If the V

TRIPX

(actual) is higher than the V

TRIPX

(desired), perform the reset sequence as described in
the next section. The new V

TRIPX

voltage to be applied

to VXMON will now be: V

TRIPX

(desired) (V

TRIPX

(desired) V

TRIPX

(actual)).

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a "native"

voltage level. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

must be 4.0V, then the V

TRIP

must

be reset. When the threshold is reset, the new level is
something less than 1.7V. This procedure must be
used to set the voltage to a lower value.

To reset the new V

TRIP

, apply greater than 3V to V

and tie the WP pin to the programming voltage V

Then send the WREN command and write to address
0Bh to reset the V

TRIP

(followed by data byte 00h). The

CS going LOW to HIGH after a valid write operation ini-
tiates the programming sequence. Bring WP LOW to
complete the operation.

Note:

This operation does not change the contents of

the EEPROM array.

X5563 Preliminary Information

Characteristics subject to change without notice.

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SPI SERIAL MEMORY

The memory portion of the device is a CMOS Serial
EEPROM array with Xicor's block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.

The device utilizes Xicor's proprietary Direct Write

cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.

All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 7). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:

The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a "1", a non-
volatile write operation is in progress. When set to a
"0", no write is in progress.

WPEN

WD1

WD0

PUP

BL1

BL0

WEL

WIP

Table 1. Instruction Set

Note:

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Table 2. Block Protect Matrix

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

WRDI

0000 0100

Reset the Write Enable Latch

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register (Watchdog, block lock, WPEN)

READ

0000 0011

Read Data from Memory Array Beginning at Selected Address

WRITE

0000 0010

Write Data to Memory Array Beginning at Selected Address

WREN CMD

Status Register

Device Pin

Block

Status Register

WEL

WPEN

Protected Block Unprotected Block

WPEN, BL0, BL1,

PUP, WD0, WD1

Protected

Writable

Protected

Writable

Protected

Writable

X5563 Preliminary Information

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The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.

The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to pro-
tect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock pro-
tected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable block lock
protection of that portion of memory.

The power on reset time (t

PURST

) bit, PUP sets the

initial power or reset time. There are two standard
settings.

The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.

The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit
programmed HIGH disables all Status Register Write
Operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.

In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is "1".
This mode disables nonvolatile writes to the device's
Status Register.

Status Register Bits

Array Addresses Protected

BL1

BL0

X5563

None

6000h7FFFh

4000h7FFFh

0000h7FFFh

PUP

Time

150 milliseconds (factory settings)

800 milliseconds

Status Register Bits

Watchdog Time Out

(Typical)

WD1

WD0

800 milliseconds

400 milliseconds

150 milliseconds

disabled (factory setting)

Figure 5. Read EEPROM Array Sequence

20 21 22 23 24 25

26 27 28 29 30

Data Out

SCK

MSB

High Impedance

Instruction

16 Bit Address

15 14 13

X5563 Preliminary Information

Characteristics subject to change without notice.

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Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.

When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to "0" blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to "1"
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the "OTP mode" by setting the WPEN bit. Data
changes now require a hardware change.

Read Sequence

When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 5).

To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 6).

Write Sequence

Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 7). CS is first taken LOW,
then the WREN instruction is clocked into the device.

After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.

To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.

For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 8).

To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 9).

While the write is in progress following a Status Register
or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.

Operational Notes

The device powers-up in the following state:

The device is in the low power standby state.

A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

SO pin is high impedance.

The Write Enable Latch is reset.

Reset Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

A WREN instruction must be issued to set the Write

Enable Latch.

CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

X5563 Preliminary Information

Characteristics subject to change without notice.

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Figure 8. Write Sequence

Figure 9. Status Register Write Sequence

SYMBOL TABLE

32 33 34 35 36 37 38 39

SCK

Instruction

16 Bit Address

Data Byte 1

40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte N

15 14 13

20 21 22 23 24 25 26 27 28 29 30 31

SCK

High Impedance

Instruction

Data Byte

11 12 13 14 15

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X5563 Preliminary Information

Characteristics subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................. 65°C to +135°C
Storage temperature ....................... 65°C to +150°C
Voltage on any pin with

respect to V

......................................1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

40°C

+85°C

Device Option

Supply Voltage

Blank or -4.5A

4.5V5.5V

-2.7 or -2.7A

2.7V5.5V

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Notes: (1) Address Byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t

after a stop that initiates a

high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.

(3) Negative number indicate charging current, Positive numbers indicate discharge current.
(4) V

min. and V

max. are for reference only and are not tested.

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

CC1

(1)

Supply Current (Active)

Read Memory array
Write nonvolatile Memory

1.5
3.0

SCK = V

x 0.1/

x 0.9 @ 10MHz

CC2

(2)

Supply Current (Passive)

WDT on, V

= 5V

WDT on, V

= 2.7V

WDT off, V

= 5V

50.0
40.0
30.0

90.0
60.0
50.0

µA

CS = V

, Any

Input= V

or V

RESET, SO = Open

RESET

TRIP

Reset Trip Point Voltage

4.5

4.62

4.75

-4.5A version

4.25

4.38

4.50

-4.5 version

2.85

2.93

3.0

-2.7A version

2.55

2.63

2.7

-2.7 version

OLR

Output (RESET) LOW Voltage

0.4

= 3.0mA (5V)

= 1.0mA (3V)

SPI Interface

ILx

(4)

Input (CS, SI, SCK, WP) LOW Voltage

-0.5

x 0.3

IHx

(4)

Input (CS, SI, SCK, WP) HIGH Voltage

x 0.7

+ 0.5

LIx

Input Leakage Current (CS, SI, SCK, WP)

±10

µA

OLS

Output (SO) LOW Voltage

0.4

= 3.0mA (5V)

= 1.0mA (3V)

OHS

Output (SO) HIGH Voltage

0.8

= -1.0mA (5V)

X5563 Preliminary Information

Characteristics subject to change without notice.

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CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V

Note:

(1) This parameter is periodically sampled and not 100% tested.

Symbol

Test

Max.

Unit

Conditions

OUT

(1)

Output Capacitance (SO, RESET)

OUT

= 0V

(1)

Input Capacitance (SCK, SI, CS, WP)

= 0V

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

30pF

RESET

2.06K

3.03K

1.53K

30pF

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Serial Input Timing

Symbol

Parameter

2.75.5V

Unit

Min.

Max.

SCK

Clock Frequency

MHz

CYC

Cycle Time

100

LEAD

CS Lead Time

LAG

CS Lag Time

200

Clock HIGH Time

Clock LOW Time

Data Setup Time

Data Hold Time

(3)

Input Rise Time

(3)

Input Fall Time

CS Deselect Time

(4)

Write Cycle Time

X5563 Preliminary Information

Characteristics subject to change without notice.

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Serial Input Timing

Serial Output Timing

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Output Timing

Symbol

Parameter

2.75.5V

Unit

Min.

Max.

SCK

Clock Frequency

MHz

DIS

Output Disable Time

Output Valid from Clock Low

Output Hold Time

(3)

Output Rise Time

(3)

Output Fall Time

SCK

MSB IN

LAG

LEAD

LSB IN

High Impedance

SCK

MSB Out

MSB1 Out

LSB Out

ADDR

LSB IN

CYC

DIS

LAG

X5563 Preliminary Information

Characteristics subject to change without notice.

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Power-Up and Power-Down Timing

RESET Output Timing

CS/WDI vs. RESET Timing

RESET Output Timing

Notes: (1) V

= 5V at 25°C.

(2) Based on characterization data only.

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

PURST

RESET Time Out Period
PUP = 0
PUP = 1

500

150
800

250

1200

ms
ms

RPD

(1)

TRIP

to RESET (Power down only)

µs

(2)

Fall Time

1000

µs

(2)

Rise Time

1000

µs

RVALID

Reset Valid V

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

WDO

Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

200
500

150

400

(2)

800

(2)

250
600

1200

ms
ms
ms

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Time Out

150

250

RESET

PURST

RPD

BATT

TRIP

CS/WDI

CST

RESET

WDO

RST

WDO

RST

X5563 Preliminary Information

Characteristics subject to change without notice.

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TRIP

Set/Reset Conditions

TRIP

Programming Specifications V

= 2.55.5V; Temperature = 0°C to 70°C

Parameter

Description

Min.

Max.

Unit

VPS

WP V

TRIP

Program Voltage Setup time

µs

VPH

WP V

TRIP

Program Voltage Hold time

µs

TSU

TRIP

Level Setup time

µs

THD

TRIP

Level Hold (stable) time

TRIP

Write Cycle Time

VPO

WP V

TRIP

Program Voltage Off time before next cycle

Programming Voltage

TRAN

TRIP

Programed Voltage Range

2.5

5.0

TRIP

Program variation after programming (075°C). (Programmed at 25°C

according to the procedure defined in the "principles of operation" section)

-25

+25

TRIP

programming parameters are periodically sampled and are not 100% tested.

SCK

* 0001h Set 0h

02h

THD

VPH

VPS

TRIPX

VPO

PCS

06h

* 000Bh (Reset)

TSU

* all others reserved

clocks

TRIP

)

X5563 Preliminary Information

Characteristics subject to change without notice.

18 of 18

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.8 9/30/02

www.xicor.com

Part Mark Information

S8= 8 Lead SOIC

X5563

YYww

Date

Code

Part

Mark

TRIP

Range

Operating Temperature Range

Part Number RESET

4.54.75

0°C70°C

X5563S8-4.5A

-40°C85°C

X5563S8I-4.5A

Blank

4.254.5

0°C70°C

X5563S8

-40°C85°C

X5563S8I

2.853.0

0°C70°C

X5563S8-2.7A

-40°C85°C

X5563S8I-2.7A

2.552.7

0°C70°C

X5563S8-2.7

-40°C85°C

X5563S8I-2.7

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