Xicor, Inc. 1994, 1995, 1996 Patents Pending

7052 10/7/97 T0/C0/D0 SH

Characteristics subject to change without notice

128K

X76F128

16Kx8+64x8

Functional Diagram

Secure SerialFlash

FEATURES

· 64-bit Password Security

--Five 64-bit Passwords for Read, Program

and Reset

· 16384 Byte+64 Byte Password Protected Arrays

--Seperate Read Passwords
--Seperate Write Passwords
--Reset Password

· Programmable Passwords
· Retry Counter Register

--Allows 8 tries before clearing of both arrays
--Password Protected Reset

· 32-bit Response to Reset (RST Input)
· 64 byte Sector Program
· 400kHz Clock Rate
· 2 wire Serial Interface
· Low Power CMOS

--2.7 to 5.5V operation
--Standby current Less than 1

--Active current less than 3 mA

· High Reliability Endurance:

--100,000 Write Cycles

· Data Retention: 100 years
· Available in:

--SmartCard Module
--TQFP Package

DESCRIPTION

The X76F128 is a Password Access Security Supervisor,
containing one 131072-bit Secure SerialFlash array and
one 512-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.

The X76F128 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.

The X76F128 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.

The X76F128 utilizes Xicor's proprietary Direct Write

cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.

LOGIC

SCL

SDA

RST

INTERFACE

16K BYTE

DATA TRANSFER

ARRAY ACCESS

ENABLE

RESET

RESPONSE REGISTER

PASSWORD ARRAY

AND PASSWORD

VERIFICATION LOGIC

CHIP ENABLE

RETRY COUNTER

SerialFlash ARRAY

64 BYTE

SerialFlash ARRAY

ARRAY 0

ARRAY 1

(PASSWORD PROTECTED)

7052 FM 01

X76F128

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the
device.

Serial Data (SDA)

SDA is a true three state serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.

Chip Enable (CS)

When CS is high, the X76F128 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F128 will be in
standby mode. CS low enables the X76F128, placing it in
the active mode.

Reset (RST)

RST is a device reset pin. When RST is pulsed high
while CS is low the X76F128 will output 32 bits of fixed
data which conforms to the standard for "synchronous
response to reset". CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!

DEVICE OPERATION

There are two primary modes of operation for the
X76F128; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.

The basic method of communication for the device is
established by first enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to `0'.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.

To ensure the correct communication, RST must remain
LOW under all conditions except when running a
"Response to Reset sequence".

Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.

If the X76F128 is in a nonvolatile write cycle a "no ACK"
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.

The basic sequence is illustrated in Figure 1.

PIN NAMES

PIN CONFIGURATION

After each transaction is completed, the X76F128 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.

Symbol

Description

Chip Select Input

SDA

Serial Data Input/Output

SCL

Serial Clock Input

RST

Reset Input

Vcc

Supply Voltage

Vss

Ground

No Connect

RST

SCL

SDA

Smart Card

7052 FM 02

GND

1
2
3
4
5
6
7
8
9
10
11
12

VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RST
SCL

VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC

SDA

7052 FM T01

X76F128

Figure 1. X76F128 Device Operation

Retry Counter

The X76F128 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, all memory areas are cleared and the device is
locked by preventing any read or write array password
matches. The passwords are unaffected. If a correct
password is received prior to retry counter overflow, the
retry counter is reset and access is granted. In order to
reset the operation of a locked up device, a special reset
command must be used with a RESET PASSWORD.

Device Protocol

The X76F128 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
a receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master
will always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F128 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.

Start Condition

All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F128 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.

A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts
are inhibited while a write is in progress.

Stop Condition

All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used
to reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.

Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.

The X76F128 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F128 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.

RESET DEVICE Command

The RESET DEVICE command is used to clear the retry
counter and reactivate the device. When the RESET
DEVICE command is used prior to the retry counter
overflow, the retry counter is reset and no arrays or pass-
words are affected. If the retry counter has overflowed, all
memory areas are cleared and all commands are
blocked and the retry counter is disabled. Issuing a valid
RESET DEVICE command (with reset password) to the
device resets and re-enables the retry counter and re-
enables the other commands. Again, the passwords are
not affected.

RESET PASSWORD Command

A RESET PASSWORD command will clear both arrays
and set all passwords to all zero.

LOAD COMMAND BYTE

LOAD 2 BYTE ADDRESS

LOAD 8-BYTE

PASSWORD

VERIFY PASSWORD

ACCEPTANCE BY

USE OF PASSWORD ACK POLLING

READ/WRITE

DATA BYTES

7052 FM 03

Twc OR DATA ACK POLLING

X76F128

Figure 2. Data Validity

Figure 3. Definition of Start and Stop Conditions

Table 1. X76F128 Instruction Set

Notes:

Illegal command codes will be disregarded. The part will respond with a "no-ACK" to the illegal byte and then return to the standby mode.
All write/read operations require a password.

1st Byte

after Start

1st Byte

after

Password

2nd Byte

after

Password

Command Description

Password

used

1000 0000

High Address

Low address

Read (Array 0)

1000 1000

High Address

Low address

Read (Array 1)

1001 0000

High Address

Low address

Sector Write (Array 0)

Write 0

1001 1000

High Address

Low address

Sector Write (Array 1)

Write 1

1010 0000

0000 0000

Change Read 0 Password

1010 1000

0000 0000

Change Read 1 Password

1011 0000

0000 0000

Change Write 0 Password

Write 0

1011 1000

0000 0000

Change Write 1 Password

Write 1

1100 0000

0000 0000

Change Reset Password

Reset

1110 0000

not used

RESET PASSWORD Command

Reset

1110 1000

not used

RESET DEVICE Command

Reset

1111 0000

not used

ACK Polling command (Ends Password operation)

None

All the rest

Reserved

SCL

SDA

Data Stable

Data

Change

7052 FM 04

SCL

SDA

Start Condition

Stop Condition

7052 FM 05

7052 FM T04

X76F128

PROGRAM OPERATIONS

Sector Programming

The sector program mode requires issuing the 8-bit write
command followed by the password, password Ack com-
mand, the address and then the data bytes transferred
as illustrated in figure 4. Up to 64 bytes may be trans-
ferred. After the last byte to be transferred is acknowl-
edged a stop condition is issued which starts the
nonvolatile write cycle.

Figure 4. Sector Programming

Data 63

COMMAND

A15

A14

A13

A12

A11

A10

Write

Password

Write

Password

Data 0

SDA

Wait t

Data ACK Polling

. . .

Wait t

ACK POLLING

ACK Polling

Repeated

COMMAND

Command

If ACK, Then

Password Matches

7052 FM 07

X76F128

ACK Polling

Once a stop condition is issued to indicate the end of the
host's write sequence, the X76F128 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
immediately. This involves issuing the start condition
followed by the new command code of 8 bits (1st byte of
the protocol.) If the X76F128 is still busy with the
nonvolatile write operation, it will issue a "no-ACK" in
response. If the nonvolatile write operation has
completed, an "ACK" will be returned and the host can
then proceed with the rest of the protocol.

After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F128

requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge polling
the user can either time out for 10ms, and then issue the
ACK polling once, or continuously loop as described in the
flow.

If the password that was inserted was correct, then an
"ACK" will be returned once the nonvolatile cycle is over,
in response to the ACK polling cycle immediately following
it.

If the password that was inserted was incorrect, then a "no
ACK" will be returned even if the nonvolatile cycle is over.
Therefore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.

Data ACK Polling Sequence

ACK

RETURNED

ISSUE NEW

COMMAND

CODE

WRITE SEQUENCE

COMPLETED

ENTER ACK POLLING

ISSUE START

YES

PROCEED

7052 FM 08

Password ACK Polling Sequence

ACK

RETURNED

ISSUE

PASSWORD

ACK COMMAND

PASSWORD LOAD

COMPLETED

ENTER ACK POLLING

ISSUE START

YES

PROCEED

7052 FM 09

Figure 5. Acknowledge Polling

8th clk.

of 8th

pwd. byte

`ACK'

clk

8th

clk

`ACK'

clk

`ACK'

START

condition

8th bit

ACK or

no ACK

SCL

SDA

7052 FM 10

X76F128

READ OPERATIONS

Read operations are initiated in the same manner as write
operations but with a different command code.

Random Read

The master issues the start condition and a Read instruc-
tion and password, performs a Password Ack Polling, then
issues the word address. Once the password has been
acknowledged and first byte has been read, another start
can be issued followed by a new 8-bit address. Random
reads are allowed, but only the low order 8 bits can
change. This limits random reads to a 512 byte block.
Therefore, with a single password cycle only a 512 byte
block of array 0 may be accessed randomly. To randomly
access another block of array 0, a stop must be issued fol-
lowed by a new command/address/password sequence. A
random read of the array 1 can access all locations with-
out another password command sequence.

Sequential Read

The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by the
data from n+1. The address counter for read operations
increments all address bits, allowing the entire memory
array contents to be serially read during one operation. At
the end of the address space (address 3FFFh for array 0,
3Fh for array 1), the counter "rolls over" to address 0 and
the X76F128 continues to output data for each acknowl-
edge received. Refer to figure 7 for the address, acknowl-
edge and data transfer sequence. An acknowledge must
follow each 8-bit data transfer. After the last bit has been
read, a stop condition is generated without a preceding
acknowledge.

Figure 6. Random Read

A7 A6 A5 A4 A3 A2 A1 A0

Data Y

COMMAND

Read

Password

Read

Password

SDA

A15

A14

A13

A12

A11

A10

Data X

Wait t

ACK POLLING

ACK Polling

Repeated

COMMAND

Command

If ACK, then

Password Matches

7052 FM 11

Figure 7. Sequential Read

Data X

COMMAND

Read

Password

Read

Password

SDA

A15

A14

A13

A12

A11

A10

Data 0

If ACK, then

Wait t

ACK POLLING

ACK Polling

Repeated

COMMAND

Command

Password Matches

7052 FM 12

X76F128

PASSWORDS

The sequence in Figure 8 shows how to change (pro-
gram) the passwords. The programming of passwords is
done twice prior to the nonvolatile write cycle in order to
verify that the new password is consistent. After the eight
bytes are entered in the second pass, a comparison
takes place. A mismatch will cause the part to reset and
enter into the standby mode.

Data ACK polling can be used to determine if a password
has been loaded correctly, however the data ACK com-
mand must be issued less than 2ms after the stop bit.

After this time, it cannot be determined if the password
has been loaded correctly, without trying the new pass-
word. To determine if the new password has been loaded
correctly the data ACK polling command is issued imme-
diately following the stop bit. If it returns an ACK, then the
two passes of the new password entry do not match. If it
returns a "no ACK" then the passwords match and a high
voltage cycle is in progress. The high voltage cycle is
complete when a subsequent data ACK command
returns an "ACK".

There is no way to read any of the passwords.

Figure 8. Change Passwords

COMMAND

Old

Password

Old

Password

SDA

New

Password

New

Password

New

Password

If ACK, then

Two bytes of "0"

Wait t

ACK POLLING

ACK Polling

Repeated

COMMAND

Command

Password Matches

If immediate ACK,
then New Password error

Data ACK

Polling

If immediate NACK,

then New Password OK

followed by ACK after ~5ms

7052 FM 13

RESPONSE TO RESET

The X76F128 returns a unique 32 bits response to reset
by implementing the following procedures:

· CS goes LOW

· RST goes HIGH

· SCK toggles Low-HIGH-Low

· RST goes LOW

· Each subsequent clock forces next response to

reset bit onto SO pin.

For the X76F128, the 32 bit sequence is 19h, 28h, AAh,
55h with each byte output LSB first. See Figure 11.

X76F128

Figure 9. Reset Password

Figure 10. Reset Device

Figure 11. Response to RESET (RST)

Reset Password

Reset

Password

Reset

Password

SDA

Wait t

ACK POLLING

ACK Polling

Repeated

COMMAND

Command

If ACK, then

Device reset

COMMAND

7052 FM 14

Reset Device

Reset

Password

Reset

Password

SDA

Wait t

ACK POLLING

ACK Polling

Repeated

COMMAND

Command

If ACK, then

Device reset

COMMAND

7052 FM 15

2 2

SCK

8 7

RST

7052 FM 16

"19"

"SS"

"28"

"AA"

LSB

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias ......................65

C to +135

Storage Temperature ...........................65

C to +150

Voltage on any Pin with

Respect to V

......................................1V to +7V

D.C. Output Current.................................................. 5mA
Lead Temperature

(Soldering, 10 seconds)................................. 300

*COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

X76F128

RECOMMENDED OPERATING CONDITIONS

7052 FM T05

7052 FM T06

Temp

Min.

Max.

Commercial

+70

Extended

+85

Supply Voltage

Limits

X76F128

4.5V to 5.5V

X76F128 2.7

2.7V to 3.6V

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

7052 FM T07

CAPACITANCE

= +25

C, f = 1MHz, V

= 5V

7052 FM T08

NOTES:

(1)

Must perform a stop command after a read command prior to measurement

(2)

min. and V

max. are for reference only and are not tested.

(3)

This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Units

Test Conditions

Min.

Max.

CC1

Supply Current

(Read)

SCL

= V

x 0.1/V

x 0.9 Levels @ 400 KHz,

SDA = Open
RST = CS = V

CC2

(3)

Supply Current

(Write)

SCL

= V

x 0.1/V

x 0.9 Levels @ 400 KHz,

SDA = Open
RST = CS = V

SB1

(1)

Supply Current

(Standby)

= V

x 0.1, V

= V

x 0.9

SCL

= 400 KHz, f

SDA

= 400 KHz

SB2

(1)

Supply Current

(Standby)

SDA

= V

SCC

= V

Other = GND or V

0.3V

Input Leakage Current

= V

to V

Output Leakage Current

OUT

= V

to V

IL1

(2)

Input LOW Voltage

0.5

x 0.3

= 5.5V

IH1

(2)

Input HIGH Voltage

x 0.7 V

+ 0.5

= 5.5V

IL2

(2)

Input LOW Voltage

0.5

x 0.1

= 3.0V

IH2

(2)

Input HIGH Voltage

x 0.9 V

+ 0.5

= 3.0V

Output LOW Voltage

0.4

= 3mA

Symbol

Test

Max.

Units

Conditions

OUT

(3)

Output Capacitance (SDA)

I/O

= 0V

(3)

Input Capacitance (RST, SCL, CS)

= 0V

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

7052 FM T09

1.3K

OUTPUT

100pF

1533

OUTPUT

100pF

7052 FM 17

Input Pulse Levels

x 0.1 to V

x 0.9

Input Rise and Fall Times

10ns

Input and Output Timing Level

x 0.5

Output Load

100pF

X76F128

AC CHARACTERISTICS

AC Specifications (Over the recommended operating conditions)

Notes: 1.

Typical values are for T

= 25°C and V

= 5.0V

Notes: 2.

= Total Capacitance of one bus line in pf.

Symbol

Parameter

Min

Typ

(1)

Max

Units

SCL

SCL Clock Frequency, X76F128

400

KHz

SCL

SCH Clock Frequency, X76F1282.7

250

KHz

(1)

Pulse width of spikes which must be suppressed by
the input filter

100

SCL LOW to SDA Data Out Valid

0.1

0.3

0.9

BUF

Time the bus must be free before a new transmit
can start

1.3

LOW

Clock LOW Time

1.3

HIGH

Clock HIGH Time

0.6

SU:STA

Start Condition Setup Time

0.6

HD:STA

Start Condition Hold Time

0.6

SU:DAT

Data In Setup Time

100

HD:DAT

Data In Hold Time

SU:STO

Stop Condition Setup Time

0.6

Data Output Hold Time

300

SDA and SCL Rise Time

20 + 0.1 x C

(2)

300

SDA and SCL Fall Time

20 + 0.1 x C

(2)

300

SU:CS

CS Setup Time

200

HD:CS

CS Hold Time

100

SCL_RST

SCL Clock Frequency during Response to Reset

400

kHz

Device Select to RST active

200

NOL

RST to SCL Non-Overlap

500

RST

RST High Time

2.25

SU:RST

Response to Reset Setup Time

1.25

LOW_RST

Clock LOW during Response to Reset

1.25

HIGH_RST

Clock HIGH during Response to Reset

1.25

RDV

RST LOW to SDA Valid During Response to Reset

500

CDV

CLK LOW to SDA Valid During Response to Reset

500

DHZ

Device Deselect to SDA high impedance

500

7052 FM T14

X76F128

RESET AC SPECIFICATIONS

Power Up Timing

Notes: 1.

Delays are measured from the time V

is stable until the specified operation can be initiated. These parameters are periodically sampled

and not 100% tested.

Typical values are for T

= 25°C and V

= 5.0V

Nonvolatile Write Cycle Timing

Notes: 1.

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

TIMING DIAGRAMS

Bus Timing

Write Cycle Timing

Symbol

Parameter

Min.

Typ

(2)

Max.

Units

PUR

(1)

Time from Power Up to Read

PUW

(1)

Time from Power Up to Write

Symbol

Parameter

Min.

Typ.(1)

Max.

Units

(1)

Write Cycle Time

SU:STO

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

SCL

SDA IN

SDA OUT

LOW

BUF

7052 FM 18

SCL

SDA

8th bit of last byte

ACK

Stop

Condition

Start

Condition

7052 FM 19

7052 FM T11

7052 FM T12

X76F128

CS Timing Diagram (Selecting/Deselecting the Part)

RST Timing Diagram Response to a Synchronous Reset

GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS

SU:CS

HD:CS

SCL

from

master

7052 FM 20

RST

NOL

HIGH_RST

LOW_RST

CDV

RDV

SU:RST

DATA BIT (1)

DATA BIT (2)

1st

clk

pulse

2nd

clk

pulse

3rd

clk

pulse

I/O

CLK

RST

NOL

DATA BIT (N)

DATA BIT (N+1)

I/O

CLK

RST

DHZ

(N+2)

7052 FM 21

100

Bus capacitance in pF

Pull Up Resistance in K

MIN

MAX

100

MIN

CCMAX

OLMIN

--------------------------

1.8

MAX

BUS

------------------

= maximum allowable SDA rise time

7052 FM 22

X76F128

8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X

0.465

0.002

(11.81

0.05)

SECTION A-A

R. 0.039 (1.00) (4X)

0.285 (7.24) MAX.

0.420

0.002

(10.67

0.05)

0.210

0.002

(5.33

0.05)

0.105

0.002

(2.67

0.05) TYP.

(8x)

0.105

0.002

(2.67

0.05)

0.008

0.001

(0.20

0.03)

0.233

0.002

(5.92

0.05)

0.174

0.002

(4.42

0.05)

0.146

0.002

(3.71

0.05)

DIE

0.0235 (0.60) MAX.

0.015 (0.38) MAX.

0.008 (0.20) MAX.

GLOB SIZE

FR4 TAPE

COPPER, NICKEL PLATED, GOLD FLASH

R. 0.013 (0.33) (8x)

0.270 (6.86) MAX.

0.069 (1.75) MIN EPOXY

FREE AREA (TYP.)

0.088 (2.24) MIN EPOXY

FREE AREA (TYP.)

NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

3003 ILL 03.1

X76F128

ORDERING INFORMATION

Limits

Blank = 5V

10%

2.7 = 2.7V to 3.6V

Temperature Range
Blank = Commercial = 0

C to +70

E = Extended = 20

C to +85

Package
L = 48-Lead TQFP
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Y = Smart Card

Device

X76F128

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec-
tion and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure

to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup-

port device or system, or to affect its safety or effectiveness.

Document Outline

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Document Outline

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