Document Outline
- Table of Contents
- Product Selection
- Data Sheet Alpha
- Ap Note Alpha
X86C64
1
CONTROL
LOGIC
SOFTWARE
DATA
PROTECT
CE
R/W
DS
SEL
A8A11
AS
L
A
T
C
H
E
S
D
E
C
O
D
E
A12
A12
M
U
X
1K BYTES
1K BYTES
1K BYTES
1K BYTES
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0A/D7
WC
1K BYTES
1K BYTES
1K BYTES
1K BYTES
A12
X
Xicor, 1991 Patents Pending
Characteristics subject to change without notice
E
2
Micro-Peripheral
FEATURES
CONCURRENT READ WRITE
TM
--Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
--Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8
Family
High Performance CMOS
--Fast Access Time, 120 ns
--Low Power
60 mA Maximum Active
200
A Maximum Standby
Software Data Protection
Block Protect Register
--Individually Set Write Lock Out in 1K Blocks
Toggle Bit
--Early End of Write Detection
Page Mode Write
--Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
--Endurance: 10,000 Write Cycle
--Data Retention: 100 Years
64K
X86C64
8192 x 8 Bit
DESCRIPTION
The X86C64 is an 8K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
Preliminary Information
Z8
Microcontroller Family Compatible
3819-2.1 7/29/96 T0/C1/D1 SH
Z8
is a registered trademark of Zilog Corporation
CONCURRENT READ WRITE
TM
is a trademark of Xicor, Inc.
FUNCTIONAL DIAGRAM
3819 FHD F02
X86C64
2
PIN DESCRIPTIONS
Address/Data (A/D
0
A/D
7
)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while
AS
is LOW. After
AS
transitions from a LOW to HIGH the addresses are
latched. Once the addresses are latched these pins input
data or output data depending on
DS
, R/
W
, and CE.
Addresses (A
8
A
12
)
High order addresses flow into the device when
AS
= V
IL
and are latched when
AS
goes HIGH.
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. When CE is LOW and
AS
is HIGH, the
X86C64 is placed in the low power standby mode.
Data Strobe (
DS
)
When used with a Z8 the
DS
input is tied directly to the
DS
output of the microcontroller.
Read/Write (R/
W
)
When used with a Z8 the R/
W
input is tied directly to the
R/
W
output of the microcontroller.
Address Strobe (
AS
)
Addresses flow through the latches to address decoders
when
AS
is LOW and are latched when
AS
transitions
from a LOW to HIGH.
Device Select (
SEL
)
Must be connected to V
SS
.
Write Control (
WC
)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input is
useful in applications in which a power failure or proces-
sor RESET could interrupt a page load cycle. In this
case, the microcontroller might drive all signals HIGH,
causing bad data to be latched into the E
2
PROM. If the
Write Control input is driven HIGH (before t
TBLC
Max)
after Read/Write (R/
W
) goes HIGH, the write cycle will
be aborted.
When
WC
is LOW (tied to V
SS
) the X86C64 will be
enabled to perform write operations. When
WC
is HIGH
normal read operations may be performed, but all at-
tempts to write to the device will be disabled.
PIN CONFIGURATION
3819 FHD F01
PIN NAMES
Symbol
Description
AS
Address Strobe
A/D
0
A/D
7
Address Inputs/Data I/O
A
8
A
12
Address Inputs
DS
Data Strobe Input
R/
W
Read/Write Input
CE
Chip Enable
WC
Write Control
SEL
Device Select--Connect to V
SS
V
SS
Ground
V
CC
Supply Voltage
3819 PGM T01
NC
A12
NC
NC
WC
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
R/W
AS
A8
A9
A11
DS
A10
CE
A/D7
A/D6
A/D5
X86C64
DIP/SOIC
X86C64
3
DEVICE OPERATION
Zilog Z8 operation requires the microcontroller's
AS
,
DS
and R/
W
outputs tied to the X86C64
AS
,
DS
and
R/
W
inputs respectively.
The rising edge of
AS
will latch the addresses for both a
read and write operation. The state of R/
W
output
determines the operation to be performed, with the
DS
signal acting as a data strobe.
If R/
W
is HIGH and CE HIGH (read operation) data will
be output on A/D
0
A/D
7
after
DS
transitions LOW. If
R/
W
is LOW and CE is HIGH (write operation) data
presented at A/D
0
A/D
7
will be strobed into the X86C64
on the LOW to HIGH transition of
DS
.
PRINCIPLES OF OPERATION
The X86C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X86C64 provides 8K bytes of 5-volt E
2
PROM which can
be used either for Program Storage, Data Storage or a
combination of both in systems based upon Von
Neumann (86XX) architectures. The X86C64 incorpo-
rates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a " Seamless" interface.
The interface inputs on the X86C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X86C64 is internally organized as two independent
planes of 4K bytes of memory with the A
12
input select-
ing which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X86C64 during a byte or page write to the
device.
The X86C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sec-
tions can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up con-
figuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X86C64 also features a Write Control input (
WC
),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X86C64 also features the industry standard 5-volt
E
2
PROM characteristics such a byte or page mode write
and toggle-bit polling.
Typical Application
P10
P11
P12
P13
P14
P15
P16
P17
P00
P01
P02
P03
P04
P07
AS
DS
R/W
21
22
23
24
25
26
27
28
13
14
15
16
17
20
9
8
7
7
8
9
10
11
13
14
15
21
20
17
19
2
16
5
22
18
23
6
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
CE
WC
AS
DS
R/W
SEL
VCC
24
XTAL
EXTAL
2
3
X86C64
Z8
VSS
12
3819 FHD F03
X86C64
4
MODE SELECTION
CE
DS
R/
W
Mode
I/O
Power
V
SS
X
X
Standby
High Z
Standby (CMOS)
V
IL
X
X
Standby
High Z
Standby (TTL)
V
IH
V
IL
V
IH
Read
D
OUT
Active
V
IH
V
IL
Write
D
IN
Active
3819 PGM T08
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X86C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X86C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of
DS
starts a timer
delaying the internal programming cycle 100
s. There-
fore, each successive write operation must begin within
100
s of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for DS Controlled Operation
Notes: (1) For each successive write within a page write cycle A
5
A
12
must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A
12
of Read = A
12
of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A
12
of Read
A
12
of Write) true data will be returned, facilitating the use of a
single memory component as both program and data store.
tBLC
CE
AS
A/D0A/D7
A8A12
DS
R/W
AIN
DIN
A12=n
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
tWC
3819 FHD F07
AIN
DIN
A12=n
AIN
DIN
A12=n
AIN
DIN
A12=n
AIN
DIN
A12=x
AIN
ADDR
AIN
Next Address
3819 FHD F07
X86C64
5
When the internal cycle is complete the toggling will
cease and the device will be accessible for additional
read or write operations. Due to the dual plane architec-
ture, reads for polling must occur in the plane that was
written; that is, the state of A
12
during write must match
the state of A
12
during polling.
Toggle Bit Polling
Because the X86C64 typical write timing is less than the
specified 5 ms, Toggle Bit Polling has been provided to
determine the early end of write. During the internal
programming cycle I/O
6
will toggle from one to zero and
zero to one on subsequent attempts to read the device.
Toggle Bit Polling
DS
Control
3819 FHD F08
CE
AS
A/D0A/D7
A8A12
DS
R/W
AIN
DIN
A12=n
OPERATION
LAST BYTE
WRITTEN
I/O6=X
X68C64 READY FOR
NEXT OPERATION
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN
A12=n
AIN
ADDR
I/O6=X
I/O6=X
I/O6=X
DOUT
X86C64
6
DATA PROTECTION
The X86C64 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E
2
PROMs and a new Block Protect write lock out
protection providing a second level data security option.
Writing with SDP
Setting write lockout is accomplished by writing a five
byte command sequence opening access to the Block
Protect Register (BPR). After the fifth byte is written the
user writes to the BPR selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BPR, must conform
to the page write timing requirements.
3819 FHD F09
Software Data Protection
Software data protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to
the X86C64, a three byte command sequence must
precede the byte(s) being written.
All write operations, both the command sequence and
any data write operations must conform to the page write
timing requirements.
Block Protect Write Lockout
The X86C64 provides a second level of data security
referred to as Block Protect write lockout. This is ac-
cessed through an extension of the SDP command
sequence. Block Protect allows the user to lock out
writes to 1K x 8 blocks of memory. Unlike SDP which
prevents inadvertent writes, but still allows easy system
access to writing the memory, Block Protect will lock out
all attempts unless it is specifically disabled by the host.
This could be used to set a higher level of protection in
a system where a portion of the memory is used for
Program Store and another portion is used as Data
Store.
Block Protect Register Format
3819 FHD F11
Setting BPR Command Sequence
3819 FHD F12
WRITE AA
TO X555
WRITE 55
TO XAAA
WRITE A0
TO X555
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT tWC
EXIT ROUTINE
X = A
12
:
A
12
= 1 IF DATA TO BE WRITTEN IS WITHIN
ADDRESS 1000 TO 1FFF.
A
12
= 0 IF DATA TO BE WRITTEN IS WITHIN
ADDRESS 0000 TO 0FFF.
6
5
4
3
2
1
0
7
000003FF
040007FF
08000BFF
0C000FFF
100013FF
140017FF
18001BFF
1C001FFF
BLOCK
ADDRESS
1 = Protect, 0 = Unprotect Block Specified
MSB
LSB
WRITE AA
TO X555
WRITE BPR
MASK VALUE TO
ANY ADDRESS
WAIT tWC
EXIT ROUTINE
WRITE 55
TO XAAA
WRITE C0
TO XAAA
WRITE AA
TO X555
WRITE A0
TO X555
X = A
12
:
A
12
= 1 IF PROGRAM BEING EXECUTED IS
WITHIN 0000 TO 0FFF.
A
12
= 0 IF PROGRAM BEING EXECUTED
RESIDES WITHIN 1000 TO 1FFF.
X86C64
7
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X86C64 ........................................ 10
C to +85
C
X86C64I ..................................... 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to V
SS
............................... 1.0V to +7V
D.C. Output Current ............................................ 5 mA
Lead Temperature
(Soldering, 10 Seconds) ............................. 300
C
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reli-
ability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
70
C
Industrial
40
C
+85
C
Military
55
C
+125
C
3819 PGM T02
Supply Voltage
Limits
X86C64
5V
10%
3819 PGM T03
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Active)
60
mA
CE = V
IL
, All I/O's = Open,
Other Inputs = V
CC
,
AS
= V
IL
I
SB1(CMOS)
V
CC
Current (Standby)
500
A
CE = V
SS
,
All I/O's = Open,Other
Inputs = V
CC
0.3V
I
SB2(TTL)
V
CC
Current (Standby)
6
mA
CE = V
IH
, All I/O's = Open, Other
Inputs = V
IH
I
LI
Input Leakage Current
10
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= GND to V
CC
,
DS
= V
IH
V
lL(1)
Input Low Voltage
1.0
0.8
V
V
IH(1)
Input High Voltage
2.0
V
CC
+ 0.5
V
V
OL
Output Low Voltage
0.4
V
I
OL
= 2.1 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 400
A
3819 PGM T04
CAPACITANCE T
A
= 25
C, F = 1.0MHZ, V
CC
= 5V
Symbol
Test
Max.
Units
Conditions
C
I/O(2)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN(2)
Input Capacitance
6
pF
V
IN
= 0V
3819 PGM T05
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR(2)
Power-Up to Read
1
ms
t
PUW(2)
Power-Up to Write
5
ms
3819 PGM T06
Notes: (1) V
IL
MIN and V
IH
MAX are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
X86C64
8
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3.0V
Input Rise and
Fall Times
10ns
Input and Output
Timing Levels
1.5V
3819 PGM T07
Note: (3) This parameter is periodically sampled and not 100% tested.
3819 FHD F05
DS
Controlled Read Cycle
DS
Controlled Read Cycle
Symbol
Parameter
Min.
Max.
Units
PW
ASL
Address Strobe Pulse Width
80
ns
t
AS
Address Setup Time
20
ns
t
AH
Address Hold Time
30
ns
t
ACC
Data Access Time
120
ns
t
DHR
Data Hold Time
0
ns
t
CS
CE Setup Time
7
ns
PW
DSH
DS
Pulse Width
150
ns
t
DSS
DS
Setup Time
30
ns
t
DSH
DS
Hold Time
20
ns
t
RWS
R/
W
Setup Time
20
ns
t
HZ(3)
DS
High to High Z Output
50
ns
t
LZ(3)
DS
Low to Low Z Output
0
ns
3819 PGM T09
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
EQUIVALENT A.C. TEST CIRCUIT
3819 FHD F04
5.0V
1923
100pF
Output
1370
AS
A/D0A/D7
A8A12
R/W
AIN
DOUT
PWASL
CE
tCS
tAS
tAH
A8A12
tDSS
tACC
tDHR
PWDSH
tRWS
tDSH
tDSH
tHZ
tDSH
DS
X86C64
9
DS
Controlled Write Cycle
Symbol
Parameter
Min.
Max.
Units
PW
ASH
Address Strobe Pulse Width
80
ns
t
AS
Address Setup Time
20
ns
t
AH
Address Hold Time
30
ns
t
DSW
Data Setup Time
50
ns
t
DHW
Data Hold Time
30
ns
t
CS
CE Setup Time
7
ns
PW
DSH
DS
Pulse Width
120
ns
t
WC
Write Cycle Time
5
ms
t
DSS
Enable Setup Time
30
ns
t
RWS
R/
W
Setup Time
20
ns
t
DSH
DS
Hold Time
20
ns
t
BLC
Byte Load Time (Page Write)
0.5
100
s
3819 PGM T10
DS
Controlled Write Cycle
3819 FHD F06
Note: (4) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
AS
A/D0A/D7
A8A12
R/W
AIN
DIN
PWASH
CE
tCS
tAS
tAH
A8A12
tDSS
tDSW
tDHW
PWDSH
tRWS
tDSH
tDSH
tDSH
DS
X86C64
10
3926 FHD F03
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.022 (0.56)
0.014 (0.36)
0.150 (3.81)
0.125 (3.18)
0.625 (15.87)
0.600 (15.24)
0.110 (2.79)
0.090 (2.29)
1.265 (32.13)
1.230 (31.24)
1.100 (27.94)
REF.
PIN 1 INDEX
0.162 (4.11)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
PIN 1
SEATING
PLANE
0.065 (1.65)
0.040 (1.02)
0.557 (14.15)
0.530 (13.46)
0.080 (2.03)
0.065 (1.65)
0
15
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
TYP. 0.010 (0.25)
PACKAGING INFORMATION
X86C64
11
PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
PIN 1
PIN 1 INDEX
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0
8
X 45
3926 FHD F24
24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" TYPICAL
0.050"
TYPICAL
0.030" TYPICAL
24 PLACES
FOOTPRINT
X86C64
12
ORDERING INFORMATION
Device
V
CC
Limits
Blank = 5V
10%
Temperature Range
Blank = Commercial = 0
C to +70
C
I = Industrial = 40
C to +85
C
M = Military = 55
C to +128
C
Package
P = 24-Lead Plastic DIP
S = 24-Lead Plastic SOIC
X86C64
X
X
X
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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