Document Outline
- Table of Contents
- Product Selection
- Da ta Sheet Alpha
- Ap Note Alpha
X88257
1
Xicor, Inc. 1994-1997 Patents Pending
Characteristics subject to change without notice
6509-1.9 4/9/96 T2/C5/D8 NS
E
2
Micro-Peripheral
256K
X88257
32,768 x 8 Bit
8051 Microcontroller Family Compatible
DESCRIPTION
The X88257 is an 32K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X88257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
FEATURES
Multiplexed Address/Data Bus
--Direct Interface to Popular 8051 Family
High Performance CMOS
--Fast Access Time, 120ns
--Low Power
--60mA Active Maximum
--500
A Standby Maximum
Software Data Protection
Toggle Bit Polling
--Early End of Write Detection
Page Mode Write
--Allows up to 128 Bytes to be Written in
One Write Cycle
High Reliability
--Endurance: 10,000 Write Cycle
--Data Retention: 100 Years
28-Lead PDIP Package
28-Lead SOIC Package
32-Lead PLCC Package
FUNCTIONAL DIAGRAM
6509 ILL F02.1
CONTROL
LOGIC
SOFTWARE
DATA
PROTECT
CE, CE
WR
RD
PSEN
A8A14
ALE
L
A
T
C
H
E
S
D
E
C
O
D
E
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0A/D7
X
32K x 8
E2PROM
X88257
2
PIN NAMES
Symbol
Description
ALE
Address Latch Enable
A/D
0
A/D
7
Address Inputs/Data I/O
A
8
A
14
Address Inputs
RD
Read Input
WR
Write Input
PSEN
Program Store Enable Input
CE,
CE
Chip Enable
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
6509 PGM T01.1
PIN DESCRIPTIONS
Address/Data (A/D
0
A/D
7
)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while ALE is HIGH. After
ALE transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on
RD
,
WR
,
PSEN
,
and
CE
.
Addresses (A
8
A
14
)
High order addresses flow into the device when ALE =
V
IH
and are latched when ALE goes LOW.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, ALE is LOW, and
CE is LOW, the X88257 is placed in the low power
standby mode. If
CE
is used to select the device, the CE
must be tied LOW.
Chip Enable (CE)
Chip enable is active HIGH. When CE is used to select
the device, the
CE
must be tied HIGH.
Program Store Enable (
PSEN
)
When the X88257 is to be used in a 8051-based system,
PSEN
is tied directly to the microcontroller's
PSEN
output.
Read (
RD
)
When the X88257 is to be used in a 8051-based system,
RD
is tied directly to the microcontroller's
RD
output.
Write (
WR
)
When the X88257 is to be used in a 8051-based system,
WR
is tied directly to the microcontroller's
WR
output.
Address Latch Enable (ALE)
Addresses flow through the latches to address decoders
when ALE is HIGH and are latched when ALE transitions
from a HIGH to LOW.
PIN CONFIGURATION
6509 FHD F01.3
A14
A12
ALE
PSEN
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WR
A13
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
PDIP
SOIC
X88257
6509 FHD F01A.5
ALE
PSEN
CE
NC
NC
NC
NC
NC
NC
A/D0
A8
A9
A11
NC
RD
A10
CE
A/D7
A/D6
A
12
A
14
V
CC
WR
A
13
A/D
1
A/D
2
V
SS
NC
A/D
3
A/D
4
A/D
5
3
2
1 32 31
15 16 17 18 19
5
6
7
8
9
10
11
12
28
27
26
25
24
23
22
X88257
PLCC
NC
4
13
14
20
21
29
30
X88257
3
PRINCIPLES OF OPERATION
The X88257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X88257
provides 32K-bytes of 5V E
2
PROM which can be used
either for program storage, data storage or a combina-
tion of both, in systems based upon Harvard (80XX)
architectures. The X88257 incorporates the interface
circuitry normally needed to decode the control signals
and demultiplex the address/data bus to provide a
"seamless" interface.
The interface inputs on the X88257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip micro-
controller. In the Harvard type system, the reading of
data from the chip is controlled either by the
PSEN
or the
RD
signal, which essentially maps the X88257 into both
the Program and the Data Memory address map.
The X88257 also features the industry standard 5V
E
2
PROM characteristics such as byte or page mode
write and Toggle Bit Polling.
DEVICE OPERATION
Modes--Mixed Program/Data Memory
By properly assigning the address spaces, a single
X88257 can be used as both the program and data
memory. This would be accomplished by connecting all
the 8051 control outputs to the corresponding inputs of
the X88257.
Program Memory Mode
This mode of operation is read-only. The
PSEN
and
ALE
inputs of the X88257 are tied directly to the
PSEN
and
ALE outputs of the microcontroller. The
RD
and
WR
inputs are tied HIGH.
When ALE is HIGH, the A/D
0
A/D
7
and A
8
A
14
ad-
dresses flow into the device. The addresses, both low-
and high-order, are latched when ALE transitions LOW
(V
IL
).
PSEN
will then go LOW and after t
PLDV
; Valid data
is presented on the A/D
0
A/D
7
pins.
CE
must be LOW
during the entire operation.
TYPICAL APPLICATION
6509 ILL F03.3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/P
TXD
RXD
39
38
37
36
35
34
33
32
5
31
19
18
9
EA/VP
X1
U?
X2
RESET
CE
21
22
23
24
25
26
27
28
11
12
12
15
16
17
18
19
25
24
21
23
2
26
1
20
1
2
3
4
5
6
7
8
12
13
14
15
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
A13
A14
CE
RD
WR
PSEN
ALE
17
16
30
11
10
8051
22
27
4
3
29
X88257
X88257
4
MODE SELECTION
CE
PSEN
RD
WR
Mode
I/O
Power
V
CC
X
X
X
Standby
High Z
Standby (CMOS)
HIGH
X
X
X
Standby
High Z
Standby (TTL)
LOW
LOW
HIGH
HIGH
Read
D
OUT
Active
LOW
HIGH
LOW
HIGH
Read
D
OUT
Active
LOW
HIGH
HIGH
Write
D
IN
Active
Page Write Timing Sequence for
WR
Controlled Operation
Notes: (1) For each successive write within a page write cycle A
7
A
14
must be the same.
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88257
supports page mode write operations. This allows the
microcontroller to write from 1 to 128 bytes of data to the
X88257. Each individual write within a page write opera-
tion must conform to the byte write timing requirements.
The falling edge of
WR
starts a timer delaying the
internal programming cycle 100
s. Therefore, each
successive write operation must begin within 100
s of
the last byte written. The following waveforms illustrate
the sequence and timing requirements.
6509 PGM T02
tBLC
CE
ALE
A/D0A/D7
A8A14
WR
PSEN(RD)
AIN
DIN
An
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
tWC
6509 ILL F08.1
AIN
DIN
An
AIN
DIN
An
AIN
DIN
An
AIN DOUT
An
AIN
ADDR
AIN
Next Address
DATA MEMORY MODE
This mode of operation allows both read and write
functions. The
PSEN
input is tied to V
IH
or to V
CC
through a pull-up resistor. The ALE,
RD
, and
WR
inputs
are tied directly to the microcontroller ALE,
RD
, and
WR
outputs.
Read
This operation is quite similar to the program memory
read. A HIGH to LOW transition on ALE latches the
addresses and the data will be output on the AD pins
after
RD
goes LOW (t
RLDV
).
Write
A write is performed by latching the addresses on the
falling edge of ALE. Then
WR
is strobed LOW followed
by valid data being presented at the A/D
0
A/D
7
pins.
The data will be latched into the X88257 on the rising
edge of
WR
. To write to the X88257, a three-byte
command sequence must precede the byte(s) being
written. (See Software Data Protection.)
X88257
5
TOGGLE BIT POLLING
Because the typical write timing is less than the specified
5ms, Toggle Bit Polling has been provided to determine
the early end of write. During the internal programming
cycle I/O
6
will toggle from "1" to "0" and "0" to "1" on
subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the
device will be accessible for additional read or write
operations.
Toggle Bit Polling
RD
/
WR
Control
RD
LAST BYTE
WRITTEN
CE
ALE
A/D0A/D7
A8A14
WR
AIN
DIN
An
OPERATION
AIN DOUT
An
AIN DOUT
An
AIN DOUT
An
AIN DOUT
An
AIN
ADDR
I/O6=X
X88C64 READY FOR
NEXT OPERATION
6509 ILL F09.1
I/O6=X
I/O6=X
I/O6=X
Writing with SDP
WRITE AA
TO 5555
WRITE 55
TO 2AAA
WRITE A0
TO 5555
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT tWC
EXIT ROUTINE
6509 ILL F10.1
SOFTWARE DATA PROTECTION
Software Data Protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to the
X88257, a three-byte command sequence must precede
the byte(s) being written. All write operations, both the
command sequence and any data write operations must
conform to the page write timing requirements.
X88257
6
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to V
SS
.................................. 1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300
C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Military
55
C
+125
C
6509 PGM T03.1
Supply Voltage
Limits
X88257
5V
10%
6509 PGM T04.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Active)
60
mA
CE
=
RD
= V
IL
, All I/O's =
Open,Other Inputs = V
CC
I
SB1(CMOS)
V
CC
Current (Standby)
500
A
CE
= V
CC
0.3V,
All I/O's =
Open,Other Inputs = V
CC
0.3V, ALE = V
IL
I
SB2(TTL)
V
CC
Current (Standby)
6
mA
CE
= V
IH
, All I/O's = Open, Other
Inputs = V
IH
, ALE = V
IL
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
,
RD
= V
IH
=
PSEN
V
lL(3)
Input LOW Voltage
1
0.8
V
V
IH(3)
Input HIGH Voltage
2
V
CC
+ 0.5
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 2.1mA
V
OH
Output HIGH Voltage
2.4
V
I
OH
= 400
A
6509 PGM T05.1
Notes: (3) V
IL
min. and V
IH
max. are for reference only and are not tested.
(4) This parameter is periodically sampled and not 100% tested.
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR(4)
Power-Up to Read
1
ms
t
PUW(4)
Power-Up to Write
5
ms
6509 PGM T07
CAPACITANCE T
A
= +25
C, f = 1MHz, V
CC
= 5V
Symbol
Test
Max.
Units
Conditions
C
I/O(4)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN(4)
Input Capacitance
6
pF
V
IN
= 0V
6509 PGM T06
X88257
7
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
10ns
Input and Output
Timing Levels
1.5V
6509 PGM T08.1
Note: (5) This parameter is periodically sampled and not 100% tested.
PSEN
Controlled Read Timing Diagram
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
PSEN
Controlled Read Cycle
Symbol
Parameter
Min.
Max.
Units
t
LHLL
ALE Pulse Width
80
ns
t
AVLL
Address Setup Time
20
ns
t
LLAX
Address Hold Time
30
ns
t
PLDV
PSEN
Read Access Time
120
ns
t
PHDX
Data Hold Time
0
ns
t
ELLL
Chip Enable Setup Time
7
ns
PW
PL
PSEN
Pulse Width
150
ns
t
PS
PSEN
Setup Time
30
ns
t
PH
PSEN
Hold Time
20
ns
t
PHDZ
(5)
PSEN
Disable to Output in High Z
50
ns
t
PLDX
(5)
PSEN
to Output in Low Z
10
ns
6509 PGM T09
EQUIVALENT A.C. TEST CIRCUIT
ALE
A/D0A/D7
A8A14
PSEN
AIN
tPLDV
DOUT
6509 ILL F05.1
tPH
tPH
tLHLL
tAVLL
tLLAX
tPS
PWPL
ADDRESS
CE
tPLDX
tPHDZ
tPHDX
tELLL
6509 ILL F04.3
5V
1.92K
100pF
OUTPUT
1.37K
X88257
8
RD
Controlled Read Cycle
Symbol
Parameter
Min.
Max.
Units
t
LHLL
ALE Pulse Width
80
ns
t
AVLL
Address Setup Time
20
ns
t
LLAX
Address Hold Time
30
ns
t
RLDV
RD
Read Access Time
120
ns
t
RHDX
Data Hold Time
0
ns
t
ELLL
Chip Enable Setup Time
7
ns
PW
RL
RD
Pulse Width
150
ns
t
RDS
RD
Setup Time
30
ns
t
RDH
RD
Hold Time
20
ns
t
RHDZ
(6)
RD
Disable to Output in High Z
50
ns
t
RLDX
(6)
RD
to Output in Low Z
0
ns
6509 PGM T10
RD
Controlled Read Timing Diagram
ALE
A/D0A/D7
A8A14
RD
AIN
tRLDV
DOUT
tRDH
tRDH
tLHLL
tAVLL
tLLAX
tRDS
PWRL
ADDRESS
CE
tRLDX
tRHDZ
tRHDX
tELLL
6509 ILL F06.1
Note: (6) This parameter is periodically sampled and not 100% tested.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
SYMBOL TABLE
X88257
9
WR
Controlled Write Cycle
Symbol
Parameter
Min.
Max.
Units
t
LHLL
ALE Pulse Width
80
ns
t
AVLL
Address Setup Time
20
ns
t
LLAX
Address Hold Time
30
ns
t
DVWH
Data Setup Time
50
ns
t
WHDX
Data Hold Time
30
ns
t
ELLL
Chip Enable Setup Time
7
ns
t
WLWH
WR
Pulse Width
120
ns
t
WRS
WR
Setup Time
30
ns
t
WRH
WR
Hold Time
20
ns
t
BLC
Byte Load Time (Page Write)
0.5
100
s
t
WC (7)
Write Cycle Time
5
ms
6509 PGM T11
WR
Controlled Write Timing Diagram
Note: (7) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
ALE
A/D0A/D7
A8A14
WR
AIN
tDVWH
DIN
6509 ILL F07.1
tWHDX
tWRH
tWRH
tLHLL
tAVLL
tLLAX
tWRS
tWLWH
ADDRESS
CE
tELLL
X88257
10
NOTES
X88257
11
NOTES
X88257
12
PACKAGING INFORMATION
3926 FHD F04
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.022 (0.56)
0.014 (0.36)
0.160 (4.06)
0.120 (3.05)
0.625 (15.88)
0.590 (14.99)
0.110 (2.79)
0.090 (2.29)
1.470 (37.34)
1.400 (35.56)
1.300 (33.02)
REF.
PIN 1 INDEX
0.160 (4.06)
0.125 (3.17)
0.030 (0.76)
0.015 (0.38)
PIN 1
SEATING
PLANE
0.065 (1.65)
0.040 (1.02)
0.557 (14.15)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
0
15
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
TYP. 0.010 (0.25)
X88257
13
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.299 (7.59)
0.290 (7.37)
0.419 (10.64)
0.394 (10.01)
0.020 (0.508)
0.014 (0.356)
0.0200 (0.5080)
0.0100 (0.2540)
0.050 (1.270)
BSC
0.713 (18.11)
0.697 (17.70)
0.012 (0.30)
0.003 (0.08)
0.105 (2.67)
0.092 (2.34)
0.0350 (0.8890)
0.0160 (0.4064)
0.013 (0.32)
0.008 (0.20)
0
8
X 45
3926 FHD F17
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
SEATING PLANE
BASE PLANE
0.42" MAX
0.030" TYPICAL
28 PLACES
0.050" TYPICAL
0.050"
TYPICAL
FOOTPRINT
X88257
14
PACKAGING INFORMATION
0.021 (0.53)
0.013 (0.33)
0.420 (10.67)
0.050 (1.27) TYP.
TYP. 0.017 (0.43)
0.045 (1.14) x 45
0.300 (7.62)
REF.
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
PIN 1
0.400
(10.16)
REF.
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
3
TYP.
0.048 (1.22)
0.042 (1.07)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.095 (2.41)
0.060 (1.52)
--
0.015 (0.38)
SEATING PLANE
0.004 LEAD
CO PLANARITY
3926 FHD F13
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
0.510"
TYPICAL
0.050"
TYPICAL
0.050"
TYPICAL
0.300"
REF
FOOTPRINT
0.400"
0.410"
0.030" TYPICAL
32 PLACES
X88257
15
ORDERING INFORMATION
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976;
4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
Device
X88257 X X
Temperature Range
Blank = Commercial = 0
C to +70
C
I = Industrial = 40
C to +85
C
M = Military = 55
C to +125
C
Package
P = 28-Lead Plastic DIP
S = 28-Lead SOIC
J = 32-Lead PLCC
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ZIP