REV 1.1.15 5/9/03
Characteristics subject to change without notice.
1 of 21
www.xicor.com
X9111
Single Digitally-Controlled (XDCP
TM
) Potentiometer
FEATURES
1024 Resistor Taps 10-Bit Resolution
SPI Serial Interface for write, read, and transfer
operations of the potentiometer
Wiper Resistance, 40
Typical @ 5V
Four Non-Volatile Data Registers
Non-Volatile Storage of Multiple Wiper Positions
Power On Recall. Loads Saved Wiper Position on
Power Up.
Standby Current < 3
A Max
V
CC
: 2.7V to 5.5V Operation
100K
End to End Resistance
100 yr. Data Retention
Endurance: 100, 000 Data Changes Per Bit Per
Register
14-Lead TSSOP, 15-Lead CSP (Chip Scale
Packaging)
Low Power CMOS
Single Supply version of the X9110
DESCRIPTION
The X9111 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Single Supply / Low Power / 1024-tap / SPI bus
A
PPLICATION
N
OTES
AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 AN115 AN124 AN133 AN134 AN135
FUNCTIONAL DIAGRAM
R
H
R
L
Bus
R
W
Interface &
Control
POT
V
CC
V
SS
SPI
Bus
Address
Data
Status
Write
Read
Wiper
1024-taps
Transfer
NC
100K
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
Control
Interface
Preliminary Information
X9111
Preliminary Information
Characteristics subject to change without notice.
2 of 21
REV 1.1.15 5/9/03
www.xicor.com
CIRCUIT LEVEL APPLICATIONS
Vary the gain of a voltage amplifier
Provide programmable dc reference voltages for
comparators and detectors
Control the volume in audio circuits
Trim out the offset voltage error in a voltage amplifier
circuit
Set the output voltage of a voltage regulator
Trim the resistance in Wheatstone bridge circuits
Control the gain, characteristic frequency and
Q-factor in filter circuits
Set the scale factor and zero point in sensor signal
conditioning circuits
Vary the frequency and duty cycle of timer ICs
Vary the dc biasing of a pin diode attenuator in RF
circuits
Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
Adjust the contrast in LCD displays
Control the power level of LED transmitters in
communication systems
Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
Control the gain in audio and home entertainment
systems
Provide the variable DC bias for tuners in RF
wireless systems
Set the operating points in temperature control
systems
Control the operating point for sensors in industrial
systems
Trim offset and gain errors in artificial intelligent
systems
DETAILED FUNCTIONAL DIAGRAM
CS
SCK
A0
SO
SI
HOLD
WP
Interface
and
Control
Circuitry
V
CC
V
SS
DR0
DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
R
H
R
L
Data
R
W
1024-taps
100K
Control
Power On
Recall
A1
X9111
Preliminary Information
Characteristics subject to change without notice.
3 of 21
REV 1.1.15 5/9/03
www.xicor.com
PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
(TSSOP)
Pin
(CSP) Symbol
Function
1
A3
SO
Serial Data Output
2
B3
A0
Device Address
3
B2, C2
NC
No Connect
4
C3
CS
Chip Select
5
D3
SCK
Serial Clock
6
E3
SI
Serial Data Input
7
E2
V
SS
System Ground
8
D2
WP
Hardware Write Protect
9
E1
A1
Device Address
10
D1
HOLD
Device Select. Pause the Serial Bus
11
C1
R
W
Wiper Terminal of the Potentiometer
12
B1
R
H
High Terminal of the Potentiometer
13
A1
R
L
Low Terminal of the Potentiometer
14
A2
V
CC
System Supply Voltage
V
CC
R
L
V
SS
1
2
3
4
5
6
7
8
14
13
12
11
10
9
NC
R
W
CS
A1
TSSOP
R
H
CSP
A0
SO
SI
HOLD
SCK
X9111
WP
X9111
A
B
C
D
E
R
L
V
CC
SO
R
H
NC
A0
R
W
NC
CS
HOLD
WP
SCK
A1
V
SS
SI
3
2
1
X9111 Preliminary Information
Characteristics subject to change without notice.
4 of 21
REV 1.1.15 5/9/03
www.xicor.com
PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
O
UTPUT
(SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
S
ERIAL
I
NPUT
(SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
S
ERIAL
C
LOCK
(SCK)
The SCK input is used to clock data into and out of the
X9111.
H
OLD
(HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times.
D
EVICE
A
DDRESS
(A
0
, A
1
)
The address inputs are used to set the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input (A1A0)
in order to initiate communication with the X9111.
C
HIP
S
ELECT
(CS)
When CS is HIGH, the X9111 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9111, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin
is the system ground.
Other Pins
N
O
C
ONNECT
(NC)
Pin should be left open. This pin is used for Xicor
manufacturing and test purposes.
PRINCIPLES OF OPERATION
DEVICE DESCRIPTION
Serial Interface
The X9111 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked-in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9111 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 1023 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within the individual array only one switch
may be turned on at a time.
X9111 Preliminary Information
Characteristics subject to change without notice.
5 of 21
REV 1.1.15 5/9/03
www.xicor.com
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Register 0
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
RH
RL
R
W
10
10
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then R
W
= R
L
If
WCR = 3FF[HEX]
then
R
W
=
R
H
Wiper
(WCR)
(DR0)
Circuitry
Register 1
(DR1)
Register 2
(DR2)
Register 3
(DR3)
These switches are controlled by a Wiper Counter
Register (WCR). The 10-bits of the WCR (WCR[9:0])
are decoded to select, and enable, one of 1024
switches.
Wiper Counter Register (WCR)
The X9111 contains a Wiper Counter Register (see
Table 1) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024 switches
along its resistor array. The contents of the WCR can
be altered in one of three ways: (1) it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its Data Register
zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9111 is powered-
down. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the R0 value into the WCR.
Data Registers (DR3 to DR0)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the Wiper Counter Register.
All operations changing data in one of the Data
Registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
A DR[9:0] is used to store one of the 1024 wiper
position (0 ~1023). Table 2.
Status Register (SR)
This 1-bit status register is used to store the system
status (see Table 3).
WIP: Write In Progress status bit, read only.
When WIP=1, indicates that high-voltage write cycle
is in progress.
When WIP=0, indicates that no high-voltage write
cycle is in progress.
X9111 Preliminary Information
Characteristics subject to change without notice.
6 of 21
REV 1.1.15 5/9/03
www.xicor.com
Table 1. Wiper Latch, WL (10-bit), WCR9WCR0: Used to store the current wiper position (Volatile, V)
Table 2. Data Register, DR (10-bit), Bit 9Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
Table 3. Status Register, SR (1-bit)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
WIP
(LSB)
DEVICE INSTRUCTIONS
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device ID for the X9111; this is fixed as 0101[B] (refer
to Table 4).
The A1A0 bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1A0 input pins. The slave address is
externally specified by the user. The X9111 compares
the serial data stream with the address input state; a
successful compare of the address bits is required for
the X9111 to successfully continue the command
sequence. Only the device whose slave address
matches the incoming device address sent by the
master executes the instruction. The A1A0 inputs can
be actively driven by CMOS input signals or tied to V
CC
or V
SS
. The R/W bit is used to set the device to either
read or write mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers. The format is shown in Table 5.
Table 4. Identification Byte Format
Table 5. Instruction Byte Format
ID3
ID2
ID1
ID0
0
A1
A0
R/W
0
1
0
1
(MSB)
(LSB)
Device Type
Identifier
Internal Slave
Address
Read or
Write Bit
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
Instruction
Opcode
Register
Selection
RB
RA
Register
0
0
1
1
0
1
0
1
DR0
DR1
DR2
DR3
X9111 Preliminary Information
Characteristics subject to change without notice.
7 of 21
REV 1.1.15 5/9/03
www.xicor.com
Five of the seven instructions are four bytes in length.
These instructions are:
Read Wiper Counter Register read the current
wiper position of the selected pot,
Write Wiper Counter Register change current
wiper position of the selected pot,
Read Data Register read the contents of the
selected data register;
Write Data Register write a new value to the
selected data register.
Read Status This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
WRL
. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between the potentiometer and one of its associated
registers. The Read Status Register instruction is the
only unique format (see Figure 4).
Two instructions require a two-byte sequence to
complete (see Figure 2). These instructions transfer
data between the host and the X9111; either between
the host and one of the Data Registers or directly
between the host and the Wiper Counter Register.
These instructions are:
XFR Data Register to Wiper Counter Register
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
XFR Wiper Counter Register to Data Register
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command (see
Figure 4).
Power Up and Down Requirements
There are no restrictions on the power-up condition of
V
CC
and the voltages applied to the potentiometer pins
provided that the V
CC
is always more positive than or
equal to the voltages at R
H
, R
L
, and R
W
, i.e., V
CC
R
H
, R
L
, R
W
. There are no restrictions on the power-
down condition. However, the datasheet parameters
for the DCP do not apply until 1millisecond after V
CC
reaches its final value.
Figure 2. Two-Byte Instruction Sequence
ID3 ID2 ID1 ID0
0
A1 A0
I2
I1
I0
RB RA
SCK
SI
CS
0
1
0
1
R/W
Device ID
Internal
Instruction
Opcode
Address
Register
0
0
0
0
Address
0
0
X9111 Preliminary Information
Characteristics subject to change without notice.
8 of 21
REV 1.1.15 5/9/03
www.xicor.com
Figure 3. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)
Figure 4. Four-Byte Instruction Sequence (Read Status Registers)
ID3 ID2 ID1 ID0 0
A0 R/W I2
0 0
SCK
SI
0
0
X X 0
0
X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
I1
I0 0 RB RA
0
1
0
1
0
X X
X
Device ID
Internal
Address
Instruction
Opcode
Register
Address
Wiper
Position
A1
ID3 ID2 ID1 ID0 0
A0 R/W I2
0
0
SCK
SI
1
0
X X 0
0
X X X
WIP
CS
I1
I0
0 RB RA
0
1
0
1
0
X X
X
Device ID
Internal
Address
Instruction
Opcode
Register
Address
Status
Bit
X X
0 0 0 0 0 0 0
A1
X9111
Preliminary Information
Characteristics subject to change without notice.
9 of 21
REV 1.1.15 5/9/03
www.xicor.com
Table 6. Instruction Set
Note:
(1) 1/0 = data is one or zero
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Instruction
Instruction Set
Operation
R/W
I
3
I
2
I
1
0
RB
RA
0
0
Read Wiper Counter
Register
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper
Counter Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
Write new value to the Wiper
Counter Register
Read Data Register
1
1
0
1
0
1/0
1/0
0
0
Read the contents of the Data
Register pointed to RB-RA
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
Write new value to the Data
Register pointed to RB-RA
XFR Data Register to
Wiper Counter Register
1
1
1
0
0
1/0
1/0
0
0
Transfer the contents of the Data
Register pointed to by RB-RA to
the Wiper Counter Register
XFR Wiper Counter
Register to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper
Counter Register to the Data
Register pointed to by RB-RA
Read Status (WIP bit)
1
0
1
0
0
0
0
0
1
Read the status of the internal write
cycle, by checking the WIP bit
(read status register).
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9111 on SO)
Wiper Position
(sent by X9111 on SO)
CS
Rising
Edge
0
1
0
1
0 A1 A0
R/ W
= 1
1
0
0
0
0
0
0
0
X
X
X
X
X
X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Master on SI)
Wiper Position
(Sent by Master on SI)
CS
Rising
Edge
0
1
0
1
0 A1 A0
R/ W
= 0
1
0
1
0
0
0
0
0
X
X
X
X
X
X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9111 on SO)
Wiper Position
(sent by X9111 on SO)
CS
Rising
Edge
0
1
0
1
0 A1 A0
R/ W
= 1
1
0
1
0 RB RA 0
0
X
X
X
X
X
X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
X9111
Preliminary Information
Characteristics subject to change without notice.
10 of 21
REV 1.1.15 5/9/03
www.xicor.com
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Read Status Register (SR)
Notes: (1) "A0 and A1": stand for the device address sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
(3) "X": Don't Care.
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position or Data
(Sent by Master on SI)
Wiper Position or Data
(Sent by Master on SI)
CS
Rising
Edge
HIGH-V
OL
T
A
GE
WRITE CYCLE
0
1
0
1
0 A1 A0
R/ W
= 0
1
1
0
0 RB RA 0
0
X X X X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
CS
Rising
Edge
0
1
0
1
0 A1 A0
R/ W
= 1
1
1
0
0 RB RA 0
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0 A1 A0
R/ W
= 0
1
1
1
0
RB
RA
0
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Status Data
(Sent by Slave on SO)
Status Data
(Sent by Slave on SO)
CS
Rising
Edge
0
1
0
1
0 A1 A0
R/ W
= 1
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0 WIP
X9111
Preliminary Information
Characteristics subject to change without notice.
11 of 21
REV 1.1.15 5/9/03
www.xicor.com
ABSOLUTE MAXIMUM RATINGS
Temperature under bias.................... 65C to +135C
Storage temperature......................... 65C to +150C
Voltage on SCK any address input
with respect to V
SS
................................. 1V to +7V
V = | (VHVL) | ......................................................5V
Lead temperature (soldering, 10 seconds) ........ 300
C
I
W
(10 seconds) ..................................................6mA
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ANALOG CHARACTERISTICS (Over recommended industrial operation conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (R
H
R
L
) / 1023, single pot
(4) n = 0, 1, 2, ...,1023; m =0, 1, 2, ..., 1022.
(5) ESD Rating on RH, RL, RW pins is 1.5KV (HBM, 1.0A leakage maximum), ESD rating on all other pins is 2.0KV.
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
Units
R
TOTAL
End to End Resistance
100
k
End to End Resistance Tolerance
20
%
Power Rating
50
mW
25C, each pot
I
W
Wiper Current
3
mA
R
W
Wiper Resistance
40
110
Wiper Current =
50A,
V
CC
= 5V
150
300
Wiper Current =
50A,
V
CC
= 3V
V
TERM
Voltage on any R
H
or R
L
Pin
V
SS
5
V
V
SS
= 0V
Noise
-120
dBV
Ref: 1V
Resolution
1.6
%
Absolute Linearity
(1)
1
MI
(3)
R
w(n)(actual)
R
w(n)(expected)
,
where n=8 to 1006
1.5
2.0
MI
(3)
R
w(n)(actual)
R
w(n)(expected)
(6)
Relative Linearity
(2)
0.5
MI
(3)
R
w(m + 1)
[R
w(m)
+ MI], where
m=8 to 1006
0.5
1.0
MI
(3)
R
w(m + 1)
[R
w(m)
+ MI]
(6)
Temperature Coefficient of R
TOTAL
300
ppm/C
Ratiometric Temp. Coefficient
20
ppm/C
C
H
/C
L
/C
W
Potentiometer Capacitancies
10/10/25
pF
See Macro model
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Device
Supply Voltage (V
CC
) Limits
X9111
5V
10%
X9111-2.7
2.7V to 5.5V
X9111
Preliminary Information
Characteristics subject to change without notice.
12 of 21
REV 1.1.15 5/9/03
www.xicor.com
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Notes: (6) This parameter is not 100% tested
(7) t
PUR
and t
PUW
are the delays required from the time the (last) power supply (V
CC
-) is stable until the specific instruction can be
issued. These parameters are not 100% tested.
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
Units
I
CC1
V
CC
supply current
(active)
400
A
f
SCK
= 2.5 MHz, SO = Open, V
CC
=5.5V
Other Inputs = V
SS
I
CC2
V
CC
supply current
(nonvolatile write)
1
5
mA
f
SCK
= 2.5MHz, SO = Open, V
CC
=5.5V
Other Inputs = V
SS
I
SB
V
CC
current (standby)
3
A
SCK = SI = V
SS
, Addr. = V
SS
,
CS = V
CC
= 5.5V
I
LI
Input leakage current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output leakage current
10
A
V
OUT
= V
SS
to V
CC
V
IH
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 1
V
V
IL
Input LOW voltage
1
V
CC
x 0.3
V
V
OL
Output LOW voltage
0.4
V
I
OL
= 3mA
V
OL
Output LOW voltage
V
CC
- 0.8
V
I
OH
= -1mA, V
CC
+3V
V
OL
Output LOW voltage
V
CC
- 0.4
V
I
OH
= -0.4mA, V
CC
+3V
Parameter
Min.
Units
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
Symbol
Test
Max.
Units
Test Conditions
C
IN/OUT
(6)
Input/Output capacitance (SI)
8
pF
V
OUT
= 0V
C
OUT
(6)
Output capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
(6)
Input capacitance (A0, CS, WP, HOLD, and SCK)
6
pF
V
IN
= 0V
Symbol
Parameter Min.
Max.
Units
t
r
V
CC
(6)
V
CC
power-up rate
0.2
50
V/ms
t
PUR
(7)
Power-up to initiation of read operation
1
ms
t
PUW
(7)
Power-up to initiation of write operation
50
ms
X9111
Preliminary Information
Characteristics subject to change without notice.
13 of 21
REV 1.1.15 5/9/03
www.xicor.com
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
I
nput pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x 0.5
Symbol
Parameter
Min.
Max.
Units
f
SCK
SSI/SPI clock frequency
2.0
MHz
t
CYC
SSI/SPI clock cycle time
400
ns
t
WH
SSI/SPI clock high time
150
ns
t
WL
SSI/SPI clock low time
150
ns
t
LEAD
Lead time
150
ns
t
LAG
Lag time
150
ns
t
SU
SI, SCK, HOLD and CS input setup time
50
ns
t
H
SI, SCK, HOLD and CS input hold time
50
ns
t
RI
SI, SCK, HOLD and CS input rise time
50
ns
t
FI
SI, SCK, HOLD and CS input fall time
50
ns
t
DIS
SO output disable time
0
500
ns
t
V
SO output valid time
100
ns
t
HO
SO output hold time
0
ns
t
RO
SO output rise time
50
ns
t
FO
SO output fall time
50
ns
t
HOLD
HOLD time
400
ns
t
HSU
HOLD setup time
50
ns
t
HH
HOLD hold time
50
ns
t
HZ
HOLD low to output in high Z
100
ns
t
LZ
HOLD high to output in low Z
100
ns
T
I
Noise suppression time constant at
SI, SCK, HOLD and CS inputs
20
ns
t
CS
CS deselect time
100
ns
t
WPASU
WP, A0, A1 setup time
0
ns
t
WPAH
WP, A0, A1 hold time
0
ns
5V
1462
100pF
SO pin
R
H
10pF
C
L
C
L
R
W
R
TOTAL
C
W
25pF
10pF
R
L
SPICE Macromodel
2714
3V
1382
100pF
SO pin
1217
X9111
Preliminary Information
Characteristics subject to change without notice.
14 of 21
REV 1.1.15 5/9/03
www.xicor.com
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
Symbol
Parameter
Typ.
Max.
Units
t
WR
High-voltage write cycle time (store instructions)
5
10
ms
Symbol
Parameter
Min.
Max.
Units
t
WRPO
Wiper response time after the third (last) power supply is stable
5
10
s
t
WRL
Wiper response time after instruction issued (all load
instructions)
5
10
s
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X9111
Preliminary Information
Characteristics subject to change without notice.
15 of 21
REV 1.1.15 5/9/03
www.xicor.com
TIMING DIAGRAMS
Input Timing
Output Timing
Hold Timing
...
CS
SCK
SI
SO
MSB
LSB
High Impedance
t
LEAD
t
H
t
SU
t
FI
t
CS
t
LAG
t
CYC
t
WL
...
t
RI
t
WH
...
CS
SCK
SO
SI
ADDR
MSB
LSB
t
DIS
t
HO
t
V
...
...
CS
SCK
SO
SI
HOLD
t
HSU
t
HH
t
LZ
t
HZ
t
HOLD
t
RO
t
FO
X9111 Preliminary Information
Characteristics subject to change without notice.
16 of 21
REV 1.1.15 5/9/03
www.xicor.com
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
.
...
CS
SCK
SI
MSB
LSB
R
W
t
WRL
...
SO
High Impedance
CS
WP
A0
A1
t
WPASU
t
WPAH
(Any Instruction)
X9111
Preliminary Information
Characteristics subject to change without notice.
17 of 21
REV 1.1.15 5/9/03
www.xicor.com
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
V
R
RW
+V
R
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Noninverting Amplifier
Voltage Regulator
Offset Voltage Adjustment
Comparator with Hysterisis
+
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)
V
IN
317
+
V
S
V
O
R
2
R
1
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
RL
L
= {R
1
/(R
1
+R
2
)} V
O
(min)
100K
10K
10K
10K
-12V
+12V
TL072
+
V
S
V
O
R
2
R
1
}
}
X9111 Preliminary Information
Characteristics subject to change without notice.
18 of 21
REV 1.1.15 5/9/03
www.xicor.com
Application Circuits (Continued)
Attenuator
Filter
Inverting Amplifier
Equivalent L-R Circuit
+
V
S
V
O
R
3
R
1
V
O
= G V
S
-1/2
G +1/2
G
O
= 1 + R
2
/R
1
fc = 1/(2
RC)
+
V
S
V
O
R
2
R
1
Z
IN
= R
2
+ s R
2
(R
1
+ R
3
) C
1
= R
2
+ s Leq
(R
1
+ R
3
) >> R
2
+
V
S
Function Generator
R
2
R
4
R
1
= R
2
= R
3
= R
4
= 10k
+
V
S
R
2
R
1
R
C
}
}
V
O
= G V
S
G = - R
2
/R
1
R
2
C
1
R
1
R
3
Z
IN
+
R
2
+
R
1
}
}
R
A
R
B
frequency
R
1
, R
2
, C
amplitude
R
A
, R
B
C
V
O
X9111 Preliminary Information
Characteristics subject to change without notice.
19 of 21
REV 1.1.15 5/9/03
www.xicor.com
Package Dimensions
Symbol
Millimeters
Min
Nominal
Max
Package Width
a
2.535
2.565
2.595
Package Length
b
3.272
3.302
3.332
Package Height
c
0.644
0.677
0.710
Body Thickness
d
0.444
0.457
0.470
Ball Height
e
0.200
0.220
0.240
Ball Diameter
f
0.300
0.320
0.340
Ball Pitch - Width
j
0.5
Ball Pitch - Length
k
0.5
Ball to Edge Spacing Width
l
0.758
0.783
0.808
Ball to Edge Spacing - Length
m
0.626
0.651
0.676
Ball Matrix
* True no-connect bump
3
2
1
A
SO
Vcc
R
L
B
A0
NC*
R
H
C
CS
NC*
R
W
D
SCK
WP
HOLD
E
SI
Vss
A1
9111TBZ
YWW I
Lot#
15-Bump Chip Scale Package (CSP B15)
Package Outline Drawing
a
f
k
m
j
l
b
d
e
c
e
Top View (Sample Marking)
Bottom View (Bumped Side)
Side View
Side View
A3
A2
A1
B3
B2
B1
C3
C2
C1
D3
D2
D1
E3
E2
E1
X9111 Preliminary Information
Characteristics subject to change without notice.
20 of 21
REV 1.1.15 5/9/03
www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Code V14
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.041 (1.05)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X9111 Preliminary Information
Characteristics subject to change without notice.
21 of 21
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2003 Patents Pending
REV 1.1.15 5/9/03
www.xicor.com
ORDERING INFORMATION
Device
V
CC
Limits
Blank = 5V
10%
2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0
C to +70C
I = Industrial = 40
C to +85C
Package
V14 = 14-Lead TSSOP
B15 = 15-Lead CSP
Potentiometer Organization
Pot
T =
100K
X9111
P
T
V
Y
PDF 
ZIP