REV 1.1.13 12/09/02

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X9241A

Quad Digitally Controlled Potentiometer (XDCP

)

FEATURES

· Four potentiometers in one package
· 2-wire serial interface
· Register oriented format

--Direct read/write/transfer of wiper positions
--Store as many as four positions per

potentiometer

· Terminal Voltages: +5V, -3.0V
· Cascade resistor arrays
· Low power CMOS
· High Reliability

--Endurance100,000 data changes per bit per

register

--Register data retention100 years

· 16-bytes of nonvolatile memory
· 3 resistor array values

--2K

to 50K

mask programmable

--Cascadable for values of 500

to 200K

· Resolution: 64 taps each pot
· 20-lead plastic DIP, 20-lead TSSOP and 20-lead

SOIC packages

DESCRIPTION

The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

Low Power/2-Wire Serial Bus

BLOCK DIAGRAM

Data

Wiper

Counter

(WCR)

Array
Pot 1

Wiper

Counter

(WCR)

SCL

SDA

A0
A1
A2

Interface

and

Control

Circuitry

Array
Pot 2

Wiper

Counter

(WCR)

Array
Pot 3

Wiper

Counter

(WCR)

PPLICATION

OTE

A V A I L A B L E

AN20 · AN4248 · AN50-53 · AN73 · AN99 · AN115 · AN120 · AN124 · AN133 · AN134 · AN135

X9241A

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PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9241A.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Address

The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9241A.

Potentiometer Pins

--V

), V

--V

)

The R

and R

inputs are equivalent to the terminal

connections on either end of a mechanical
potentiometer.

--V

)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

PIN CONFIGURATION

PIN NAMES

PRINCIPLES OF OPERATION

The X9241A is a highly integrated microcircuit
incorporating four resistor arrays, their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Symbol

Description

SCL

Serial Clock

SDA

Serial Data

A0A3

Address

Potentiometer Pins
(terminal equivalent)

Potentiometer Pins
(wiper equivalent)

SDA

SCL

DIP/SOIC/TSSOP

X9241A

X9241A

Characteristics subject to change without notice.

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Serial Interface

The X9241A supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9241A will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

HIGH

). The X9241A continuously

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.

The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9241A will respond with a final acknowledge.

Array Description

The X9241A is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9241A
this is fixed as 0101[B].

Figure 1. Slave Address

The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9241A compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9241A to respond with an acknowledge.

Device Type

Identifier

Device Address

X9241A

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Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9241A
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241A is still busy with the write operation no ACK
will be returned. If the X9241A has completed the
write operation an ACK will be returned and the
master can then proceed with the next operation.

Flow 1. ACK Polling Sequence

Instruction Structure

The next byte sent to the X9241A contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of four pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits define the instruction. The next
two bits (P1 and P0) select which one of the four
potentiometers is to be affected by the instruction. The
last two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed t

STPWV

. A

transfer from WCR current wiper position, to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all four of the
potentiometers and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9241A; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected Data Register. The
sequence of operations is shown in Figure 4.

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

FurTher

OperaTion?

Issue

Instruction

Proceed

Issue STOP

Yes

Proceed

Issue STOP

Potentiometer

Select

Instructions

X9241A

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The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9241A has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (t

HIGH

)

while SDA is HIGH, the selected wiper will move one

resistor segment towards the V

terminal. Similarly,

for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
the V

terminal. A detailed illustration of the

sequence and timing for this operation are shown in
Figures 5 and 6 respectively.

Figure 3. Two-Byte Instruction Sequence

Figure 4. Three-Byte Instruction Sequence

Figure 5. Increment/Decrement Instruction Sequence

A
R

P1 P0

R1 R0

SCL

SDA

O
P

C
K

A
C
K

S
T

A3 A2 A1 A0 A

I1 I0

P1 P0 R1 R0

SCL

SDA

CM DW D5 D4 D3 D2

D1 D0

A3 A2 A1 A0

P1 P0 R1 R0

SCL

SDA

N
C

E
C

X9241A

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Figure 6. Increment/Decrement Timing Limits

Table 1. Instruction Set

Notes: (10) 1/0 = data is one or zero

(11) X = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)

Instruction

Instruction Format

Operation

Read WCR

1/0

(10)

1/0

(11)

Read the contents of the Wiper Counter
Register pointed to by P

Write WCR

1/0

Write new value to the Wiper Counter
Register pointed to by P

Read Data
Register

1/0

Read the contents of the Register
pointed to by P

and R

Write Data
Register

1/0

Write new value to the Register pointed
to by P

and R

XFR Data
Register to
WCR

1/0

Transfer the contents of the Register
pointed to by P

and R

to its

associated WCR

XFR WCR to
Data Register

1/0

Transfer the contents of the WCR
pointed to by P

to the Register

pointed to by R

Global XFR
Data Register to
WCR

1/0

Transfer the contents of the Data
Registers pointed to by R

of all four

pots to their respective WCR

Global XFR
WCR to Data
Register

1/0

Transfer the contents of all WCRs to their
respective data Registers pointed to by
R

of all four pots

Increment/
Decrement
Wiper

1/0

Enable Increment/decrement of the
WCR pointed to by P

SCL

SDA

INC/DEC

CMD

ISSUED

Voltage Out

CLWV

X9241A

Characteristics subject to change without notice.

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Figure 7. Acknowledge Response from Receiver

SCL from

Data Output

from Transmitter

START

Acknowledge

Master

Data Output

from Receiver

DETAILED OPERATION

All four XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a Wiper Counter
Register and four Data Registers. A detailed discussion
of the register organization and array operation follows.

Wiper Counter Register

The X9241A contains four volatile Wiper Counter
Registers (WCR), one for each XDCP potentiometer.
The WCR can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it may
be written directly by the host via the Write WCR
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction
(parallel load); it can be modified one step at a time by
the increment/decrement instruction; finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9241A is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be different
from the value present at power-down.

Data Registers

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

X9241A

Characteristics subject to change without notice.

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Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial
Bus
Input

Parallel
Bus
Input

Wiper

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCL

UP/DN

If WCR = 00[H] then V

= V

If WCR = 3F[H] then V

= V

o
u
n

e
c
o
d

Cascade

Control

Logic

Cascade Mode

The X9241A provides a mechanism for cascading the
arrays. That is, the sixty-three resistor elements of one
array may be cascaded (linked) with the resistor
elements of an adjacent array. The V

of the higher

order array must be connected to the V

of the

lower order array (See Figure 9).

Cascade Control Bits

The data byte, for the three-byte commands, contains 6
bits (LSBs) for defining the wiper position plus two high
order bits, CM (Cascade Mode) and DW (Disable
Wiper, normal operation).

The state of the CM bit (bit 7 of WCR) enables or
disables cascade mode. When the CM bit of the WCR
is set to "0" the potentiometer is in the normal operation
mode. When the CM bit of the WCR is set to "1" the
potentiometer is cascaded with its adjacent higher
order potentiometer. For example; if bit 7 of WCR2 is
set to "1", pot 2 will be cascaded to pot 3.

The state of DW enables or disables the wiper. When
the DW bit of the WCR is set to "0" the wiper is enabled;
when set to "1" the wiper is disabled. If the wiper is
disabled, the wiper terminal will be electrically isolated
and float.

When operating in cascade mode V

, V

and

the wiper terminals of the cascaded arrays must be
electrically connected externally. All but one of the
wipers must be disabled. The user can alter the wiper
position by writing directly to the WCR or indirectly by
transferring the contents of the Data Registers to the
WCR or by using the Increment/Decrement command.

When using the Increment/Decrement command the
wiper position will automatically transition between
arrays. The current position of the wiper can be
determined by reading the WCR registers; if the DW bit
is "0", the wiper in that array is active. If the current
wiper position is to be maintained on power-down a
global XFR WCR to Data Register command must be
issued to store the position in NV memory before
power-down.

X9241A

Characteristics subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias ........................65 to +135°C
Storage temperature .............................65 to +150°C
Voltage on SCK, SCL or any address

input with respect to V

.........................1V to +7V

Voltage on any V

, V

or V

referenced to V

....................................... +6V/-4V

V = |V

| .............................................. 10V

Lead temperature (soldering, 10 seconds)........ 300°C
I

(10 seconds).................................................. ±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Product

Temperature Range

Min.

Max.

Supply Voltage

X9241A

Commercial

Industrial

0°C

40°C

+70°C
+85°C

5V ±10%
5V ±10%

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Limits

Unit

Test Condition

Min.

Typ.

Max.

TOTAL

End to end resistance

+20

Power rating

25°C, each pot

Wiper current

See Note 7, 8

Wiper resistance

130

Wiper Current = ± 1mA
See Note 7

TERM

Voltage on any V

, V

3.0

Noise

120

dBV

Ref: 1KHz See Note 5

Resolution

(4)

1.6

0.4

See Note 5

Absolute linearity

(1)

±1

(3)

w(n)(actual)

w(n)(expected)

Relative linearity

(2)

±0.2

(3)

w(n + 1)

w(n) + MI

]

Temperature Coefficient of R

TOTAL

±300

ppm/°C

See Note 5

Ratiometric temperature coefficient

±20

ppm/C

See Note 5

Potentiometer capacitances

15/15/25

See Circuit #3 and Note 5

, R

leakage current

0.1

µA

= V

TERM

. Device is in

stand-by mode.

X9241A

Characteristics subject to change without notice.

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D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten-

tiometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R

)/63, single pot

(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER-UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc
reach 90% of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification
should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc
should not reverse polarity by more than 0.5V.

Notes: (5) This parameter is guaranteed by characterization or sample testing.

(6) t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated. These parameters

are guaranteed by design.

(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse

width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure
to the device.

Symbol

Parameter

Limits

Unit

Test Condition

Min.

Typ.

Max.

Supply current (active)

SCL

= 100kHz, SDA = Open,

Other Inputs = V

current (standby)

200

500

µA

SCL = SDA = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

+ 1

Input LOW voltage

0.8

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Symbol

Parameter

Max.

Unit

Test Condition

I/O

(5)

Input/output capacitance (SDA)

I/O

= 0V

(5)

Input capacitance (A0, A1, A2, A3 and SCL)

= 0V

Symbol

Parameter

Min. Typ.

Max.

Unit

PUR

(6)

Power-up to initiation of read operation

PUW

(6)

Power-up to initiation of write operation

Power up ramp rate

0.2

V/msec

X9241A

Characteristics subject to change without notice.

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A.C. CONDITIONS OF TEST

SYMBOL TABLE

Equivalent A.C. Test Circuit

Circuit #3 SPICE Macro Model

Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors

DCP Wiper Current De-rating Curve

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing levels

x 0.5

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

1533

100pF

SDA Output

10pF

TOTAL

25pF

10pF

Macro Model

120

100

80 100 120

Bus Capacitance (pF)

Min.

Resistance

Max.
Resistance

MAX

BUS

MIN

OL MIN

CC MAX

=1.8K

Resistance (K

)

Ambient Temperature (°C)

Maximum DCP Wiper Current

X9241A

Characteristics subject to change without notice.

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A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Figure 10. Input Bus Timing

Figure 11. Output Bus Timing

Symbol

Parameter

Limits

Unit

Reference

Figure

Min.

Max.

SCL

(5)

SCL clock frequency

100

kHz

LOW

(5)

Clock LOW period

4700

HIGH

(5)

Clock HIGH period

4000

(5)

SCL and SDA rise time

1000

(5)

SCL and SDA fall time

300

(5)(9)

Noise suppression time constant (glitch filter)

SU:STA

(5)

Start condition setup time (for a repeated start condition)

4700

10 & 12

HD:STA

(5)

Start condition hold time

4000

10 & 12

SU:DAT

(5)

Data in setup time

250

HD:DAT

(5)

Data in hold time

(5)

SCL LOW to SDA data out valid

3500

(5)

Data out hold time

SU:STO

(5)

Stop condition setup time

4700

10 & 12

BUF

(5)

Bus free time prior to new transmission

4700

(5)

Write cycle time (nonvolatile write operation)

STPWV

(5)

Wiper response time from stop generation

500

µs

CLWV

(5)

Wiper response from SCL LOW

1000

µs

power-up rate

0.2

mV/µs

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

LOW

SU:STO

BUF

SCL

SDA

(Data in)

SCL

SDA

OUT

(ACK)

SDA

OUT

SDA

OUT

X9241A

Characteristics subject to change without notice.

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LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.1.13 12/09/02

www.xicor.com

Ordering Information

Device

Limits

Blank = 5V ±10%

Temperature Range
Blank = Commercial = 0 to +70°C
I = Industrial = 40 to +85°C

Package
P = 20-Lead Plastic DIP
S = 20-Lead SOIC
V = 20-Lead TSSOP

Potentiometer Organization

Pot 0 Pot 1 Pot 2 Pot 3

Y = 2K

W = 10K

10K

U = 50K

50K

M = 2K

10K

50K

Y P T V

X9241A

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